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1 digital media system-on-chip (dmsoc) 1.1 features tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 (flexible ram/cache allocation) high-performance digital media soc arm926ej-s core ? 594-, 729-mhz c64x+? clock rate ? support for 32-bit and 16-bit (thumb? ? 297-, 364.5-mhz arm926ej-s? clock rate mode) instruction sets ? eight 32-bit c64x+ instructions/cycle ? dsp instruction extensions and single ? 4752, 5832 c64x+ mips cycle mac ? fully software-compatible with c64x / ? arm? jazelle? technology arm9? ? embeddedice-rt? logic for real-time ? supports smartreflex? class 0 [-594 only] debug 1.05-v and 1.2-v adaptive core voltage arm9 memory architecture ? extended temp available [-594 only] ? 16k-byte instruction cache ? industrial temp available [-729 only] ? 8k-byte data cache advanced very-long-instruction-word (vliw) ? 32k-byte ram tms320c64x+? dsp core ? 8k-byte rom ? eight highly independent functional units embedded trace buffer? (etb11?) with 4kb six alus (32-/40-bit), each supports memory for arm9 debug single 32-bit, dual 16-bit, or quad 8-bit arithmetic per clock cycle endianness: little endian for arm and dsp two multipliers support four 16 x 16-bit dual programmable high-definition video multiplies (32-bit results) per clock image co-processor (hdvicp) engines cycle or eight 8 x 8-bit multiplies (16-bit ? supports a range of encode, decode, and results) per clock cycle transcode operations ? load-store architecture with non-aligned h.264, mpeg2, vc1, mpeg4 sp/asp support 99-/108-mhz video port interface (vpif) ? 64 32-bit general-purpose registers ? two 8-bit sd (bt.656), single 16-bit hd ? instruction packing reduces code size (bt.1120), or single raw (8-/10-/12-bit) ? all instructions conditional video capture channels ? additional c64x+? enhancements ? two 8-bit sd (bt.656) or single 16-bit hd protected mode operation (bt.1120) video display channels exceptions support for error detection video data conversion engine (vdce) and program redirection ? horizontal and vertical downscaling hardware support for modulo loop ? chroma conversion (4:2:2 ? 4:2:0) operation two transport stream interface (tsif) c64x+ instruction set features modules ? byte-addressable (8-/16-/32-/64-bit data) (one parallel/serial and one serial only) ? 8-bit overflow protection ? tsif for mpeg transport stream ? bit-field extract, set, clear ? simultaneous synchronous or ? normalization, saturation, bit-counting asynchronous input/output streams ? compact 16-bit instructions ? absolute time stamp detection ? additional instructions to support complex ? pid filter with 7 pid filter tables multiplies ? corresponding clock reference generator c64x+ l1/l2 memory architecture (crgen) modules for system time-clock ? 32k-byte l1p program ram/cache (direct recovery mapped) ? 32k-byte l1d data ram/cache (2-way set-associative) ? 128k-byte l2 unified mapped ram/cache please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this document. all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2007?2009, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com external memory interfaces (emifs) one serial peripheral interface (spi) with two ? 32-bit ddr2 sdram memory controller chip-selects with 512m-byte address space (1.8-v i/o) master/slave inter-integrated circuit (i 2 c ? asynchronous16-bit wide emif (emifa) bus?) with 128m-byte address reach two multichannel audio serial ports (mcasps) flash memory interfaces ? one four serializer transmit/receive port ? nor (8-/16-bit-wide data) ? one single dit transmit port for s/pdif ? nand (8-/16-bit-wide data) 32-bit host port interface (hpi) enhanced direct-memory-access (edma) vlynq? interface (fpga interface) controller (64 independent channels) two pulse width modulator (pwm) outputs ? programmable default burst size ata/atapi i/f (ata/atapi-6 specification) 10/100/1000 mb/s ethernet mac (emac) up to 33 general-purpose i/o (gpio) pins ? ieee 802.3 compliant (3.3-v i/o only) (multiplexed with other device functions) ? supports mii and gmii media independent interfaces on-chip arm rom bootloader (rbl) ? management data i/o (mdio) module individual power-saving modes for arm/dsp usb port with integrated 2.0 phy flexible pll clock generators ? usb 2.0 high-/full-speed client ieee-1149.1 (jtag) boundary- ? usb 2.0 high-/full-/low-speed host scan-compatible (mini-host, supporting one external 529-pin pb-free bga package device) (zut suffix), 0.8-mm ball pitch 32-bit, 33-mhz, 3.3 v peripheral component 0.09- m m/7-level cu metal process (cmos) interconnect (pci) master/slave interface 3.3-v and 1.8-v i/o, 1.2-/1.05-v internal ? conforms to pci specification 2.3 applications: two 64-bit general-purpose timers (each ? video encode/decode/transcode/transrate configurable as two 32-bit timers) ? digital media one 64-bit watch dog timer ? networked media encode/decode three configurable uart/irda/cir modules ? video imaging (one with modem control signals) ? video infrastructure ? supports up to 1.8432 mbps uart ? video conferencing ? sir and mir (0.576 mbaud) ? cir with programmable data encoding digital media system-on-chip (dmsoc) 2 submit documentation feedback
1.2 description tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the tms320dm6467 (also referenced as dm6467) leverages ti?s davinci? technology to meet the networked media encode and decode application processing needs of next-generation embedded devices. the dm6467 enables oems and odms to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. the dual-core architecture of the dm6467 provides benefits of both dsp and reduced instruction set computer (risc) technologies, incorporating a high-performance tms320c64x+ dsp core and an arm926ej-s core. the arm926ej-s is a 32-bit risc processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. the core uses pipelining so that all parts of the processor and memory system can operate continuously. the arm core incorporates: a coprocessor 15 (cp15) and protection module data and program memory management units (mmus) with table look-aside buffers. separate 16k-byte instruction and 8k-byte data caches. both are four-way associative with virtual index virtual tag (vivt). the tms320c64x+? dsps are the highest-performance fixed-point dsp generation in the tms320c6000? dsp platform. it is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (vliw) architecture developed by texas instruments (ti), making these dsp cores an excellent choice for digital media applications. the c64x is a code-compatible member of the c6000? dsp platform. the tms320c64x+ dsp is an enhancement of the c64x+ dsp with added functionality and an expanded instruction set. any reference to the c64x dsp or c64x cpu also applies, unless otherwise noted, to the c64x+ dsp and c64x+ cpu, respectively. with performance of up to 5832 million instructions per second (mips) at a clock rate of 729 mhz, the c64x+ core offers solutions to high-performance dsp programming challenges. the dsp core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. the c64x+ dsp core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units?two multipliers for a 32-bit result and six arithmetic logic units (alus). the eight functional units include instructions to accelerate the performance in video and imaging applications. the dsp core can produce four 16-bit multiply-accumulates (macs) per cycle for a total of 2376 million macs per second (mmacs), or eight 8-bit macs per cycle for a total of 4752 mmacs. for more details on the c64x+ dsp, see the tms320c64x/c64x+ dsp cpu and instruction set reference guide (literature number spru732). the dm6467 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other c6000 dsp platform devices. the dm6467 core uses a two-level cache-based architecture. the level 1 program cache (l1p) is a 256k-bit direct mapped cache and the level 1 data cache (l1d) is a 640k-bit 2-way set-associative cache. the level 2 memory/cache (l2) consists of an 512k-bit memory space that is shared between program and data space. l2 memory can be configured as mapped memory, cache, or combinations of the two. the peripheral set includes: a configurable video port; a 10/100/1000 mb/s ethernet mac (emac) with a management data input/output (mdio) module; a 4-bit transfer/4-bit receive vlynq interface; an inter-integrated circuit (i2c) bus interface; a multichannel audio serial port (mcasp0) with 4 serializers; a secondary multichannel audio serial port (mcasp1) with a single transmit serializer; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a configurable 32-bit host port interface (hpi); up to 33-pins of general-purpose input/output (gpio) with submit documentation feedback digital media system-on-chip (dmsoc) 3
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com programmable interrupt/event generation modes, multiplexed with other peripherals; 3 uart/irda/cir interfaces with modem interface signals on uart0; 2 pulse width modulator (pwm) peripherals; an ata/atapi-6 interface; a 33-mhz peripheral component interface (pci); and 2 external memory interfaces: an asynchronous external memory interface (emifa) for slower memories/peripherals, and a higher speed synchronous memory interface for ddr2. the ethernet media access controller (emac) provides an efficient interface between the dm6467 and the network. the dm6467 emac support both 10base-t and 100base-tx, or 10 mbits/second (mbps) and 100 mbps in either half- or full-duplex mode; and 1000base-tx (1 gbps) in full-duplex mode with hardware flow control and quality of service (qos) support. the management data input/output (mdio) module continuously polls all 32 mdio addresses in order to enumerate all phy devices in the system. once a phy candidate has been selected by the arm, the mdio module transparently monitors its link state by reading the phy status register. link change events are stored in the mdio module and can optionally interrupt the arm, allowing the arm to poll the link status of the device without continuously performing costly mdio accesses. the pci, hpi, i2c, spi, usb2.0, and vlynq ports allow the dm6467 to easily control peripheral devices and/or communicate with host processors. the dm6467 also includes a high-definition video/imaging co-processor (hdvicp) and video data conversion engine (vdce) to offload many video and imaging processing tasks from the dsp core, making more dsp mips available for common video and imaging algorithms. for more information on the hdvicp enhanced codecs, such as h.264 and mpeg4, please contact your nearest ti sales representative. the rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. for details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. the dm6467 has a complete set of development tools for both the arm and dsp. these include c compilers, a dsp assembly optimizer to simplify programming and scheduling, and a windows? debugger interface for visibility into source code execution. digital media system-on-chip (dmsoc) 4 submit documentation feedback
1.3 functional block diagram tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 figure 1-1 shows the functional block diagram of the device. figure 1-1. tms320dm6467 functional block diagram submit documentation feedback digital media system-on-chip (dmsoc) 5 jt ag interface system control plls/clock generator input clock(s) power/sleep controller pin multiplexing arm subsystem arm926ej-s cpu 16 kb i-cache 32 kb ram 8 kb d-cache 8 kb rom dsp subsystem c64x+ dsp cpu 32 kb l1 pgm 128 kb l2 ram 32 kb l1 data high definition video-imaging coprocessor (hdvicp0) switched central resource (scr) peripherals edma i 2 c spi uart serial interfaces ddr2 mem ctlr (16b/32b) async emif/ nand/ smartmedia ata program/data storage watchdog timer pwm system general- purpose timer usb 2.0 phy vlynq emac with mdio connectivity hpi mcasp video port i/f pci (33 mhz) tsif high definition video-imaging coprocessor (hdvicp1) crgen vdce
contents tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com 1 digital media system-on-chip (dmsoc) ............ 1 behavior ............................................ 145 1.1 features .............................................. 1 7.3 power supplies .................................... 146 7.4 external clock input from dev_mxi/dev_clkin 1.2 description ............................................ 3 and aux_mxi/aux_clkin pins .................. 155 1.3 functional block diagram ............................ 5 7.5 clock plls ......................................... 158 2 revision history ......................................... 7 7.6 enhanced direct memory access (edma3) 3 device overview ......................................... 9 controller ........................................... 166 3.1 device characteristics ................................ 9 7.7 reset ............................................... 186 3.2 device compatibility ................................. 11 7.8 interrupts ........................................... 197 3.3 arm subsystem .................................... 11 7.9 external memory interface (emif) ................. 203 3.4 dsp subsystem ..................................... 15 7.10 ddr2 memory controller .......................... 210 3.5 memory map summary ............................. 20 7.11 video port interface (vpif) ........................ 223 3.6 pin assignments .................................... 24 7.12 transport stream interface (tsif) ................. 231 3.7 terminal functions .................................. 30 7.13 clock recovery generator (crgen) .............. 241 3.8 device support ...................................... 81 7.14 video data conversion engine (vdce) .......... 244 3.9 documentation support ............................. 83 7.15 peripheral component interconnect (pci) ......... 247 4 device configurations ................................. 84 7.16 ethernet mac (emac) ............................. 254 4.1 system module registers ........................... 84 7.17 management data input/output (mdio) .......... 264 4.2 power considerations ............................... 86 7.18 host-port interface (hpi) peripheral ............... 266 4.3 clock considerations ................................ 89 7.19 usb 2.0 ............................................ 274 4.4 boot sequence ...................................... 97 7.20 ata controller ..................................... 284 4.5 configurations at reset ............................ 103 7.21 vlynq ............................................. 299 4.6 configurations after reset ......................... 106 7.22 multichannel audio serial port (mcasp0/1) 4.7 multiplexed pin configurations ..................... 114 peripherals ......................................... 304 4.8 debugging considerations ......................... 137 7.23 serial peripheral interface (spi) ................... 316 5 system interconnect ................................. 139 7.24 universal asynchronouse receiver/transmitter (uart) ............................................. 331 6 device operating conditions ....................... 140 7.25 inter-integrated circuit (i2c) ....................... 338 6.1 absolute maximum ratings over operating case temperature range (unless otherwise noted) ... 140 7.26 pulse width modulator (pwm) ..................... 342 6.2 recommended operating conditions ............. 141 7.27 timers .............................................. 344 6.3 electrical characteristics over recommended 7.28 general-purpose input/output (gpio) ............. 347 ranges of supply voltage and operating 7.29 ieee 1149.1 jtag ................................. 350 temperature (unless otherwise noted) ........... 142 8 mechanical packaging and orderable 7 peripheral information and electrical information ............................................. 353 specifications ......................................... 144 8.1 thermal data for zut .............................. 353 7.1 parameter information ............................. 144 8.1.1 packaging information ............................. 353 7.2 recommended clock and control signal transition contents 6 submit documentation feedback
2 revision history tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 this data manual revision history highlights the technical changes made to the sprs403e device-specific data manual to make it an sprs403f revision. scope: applicable updates to the dm646x dmsoc device family, specifically relating to the tms320dm6467 device (all silicon revisions 3.0, 1.1, and 1.0) which is now in the production data (pd) stage of development have been incorporated. increased the vpif operating frequency from 99 mhz to 108 mhz for -729 devices updated pci terminal functions pin descriptions including the disabling of the ipus/ipds in pci mode (pcien = 1) and the addition of the pci_rsv[0:5] pin descriptions (pins: a9, e9, b10, d10, a11, and d11) the dm6467 devices now support 512 mb of ddr2 memory updated/changed pin b10 to " pci_rsv2/intrq/gp[18]/ em_rsv0" see additions/modifications/deletions global added, where applicable, the support of 108-mhz operating frequency for the video port interface (vpif) peripheral for -729 devices added, where applicable, the pci_rsv[0:5] pin descriptions [a9, e9, b10, e10, a11, and d11], associated footnotes, and muxing functionality added, where applicable, the disabling of the ipus/ipds on all pci pins when in pci mode (pcien = 1); it is recommended that additional external resistors be added on pci_rsv[0:5] pins. updated/changed, where applicable, the emu rsv pin function from "rsv" to "emu_rsv0" added, where applicable, ddr2 memory has been updated/changed to support 512 mb vs. 256 mb section 3.1 table 3-1 , characteristics of the dm6467 processor: device characteristics added to the "configurable video port interface (vpif)" both 99 mhz and 108 mhz operating frequency ranges updated/changed, under the pll options, the dev_clkin frequency multiplier (pllc2) (27-mhz reference) descriptions section 3.6 section 3.6.1 , pin map (bottom view): pin assignments updated/changed figure 3-6 , pin map [section e] pin names for a9, a11, b10, e9, e10, and d11 section 3.7.7 table 3-11 , peripheral component interconnect (pci) terminal functions: peripheral component added the "also, in pci mode (pcien = 1), the internal ..." paragraph under note: interconnect (pci) section 4.3.1.2 table 4-3 , dm6467 default module states: module clock state updated/changed default module state description of lpsc #1 and #21 updated/changed lpsc # 16 and 17 to be used in combination for the video port added associated footnote explanation section 4.7.3 section 4.7.3.7 , crgen signal muxing: pin multiplexing details updated/changed "the two crgen modules shared pin with ..." lead-in sentence [cleared documentation feedback issue] section 4.8 section 4.8.1 , pullup/pulldown resistors: debugging considerations added "for most systems, a 20-k w resistor can also be used as an external pu/pd ..." paragraph section 6 section 6.1 , absolute maximum ratings over operating case temperature range (unless otherwise noted): device operating updated/changed the supply voltage ranges, i/o, 3.3v from "0 v to 3.8 v" to "?0.3 v to 3.8 v" conditions updated/changed the supply voltage ranges, i/o, 1.8v from "0 v to 2.6 v" to "?0.3 v to 2.6 v" updated/changed the storage temperature range, t stg , (default) from "?65 c to 150 c" to "?55 c to 150 c" section 7.3.4 table 7-2 , dm6467 clock domains: dm6467 power and clock updated/changed the vpif fixed ratio vs. sysclk1 frequency under vpif for -594 and -729 domains updated/changed the vpif pll mode for -594 from "74.25" to "99" mhz updated/changed the vpif pll mode for -729 from "72.9" to "104.14" mhz submit documentation feedback revision history 7
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com see additions/modifications/deletions section 7.10.2 figure 7-27 , dm6467 32-bit ddr2 high level schematic: ddr2 interface updated/changed the resistor tolerance value to "5%' for the ddr_zn and ddr_zp signals figure 7-28 , dm6467 16-bit ddr2 high level schematic: updated/changed the resistor tolerance value to "5%' for the ddr_zn and ddr_zp signals section 7.11.4 table 7-47 , timing requirements for vpif vp_clkinx inputs: vpif electrical data/timing updated/changed cycle time, vp_clkin for 0, 1, 2, and 3 into one row split -729 device into separate column table 7-48 , timing requirements for vpif channels 0/1 video capture data and control inputs: split -729 device into separate column table 7-49 , switching characteristics over recommended operating conditions for video data shown with respect to vp_clko2/3: split -729 device into separate column section 7.23.3 master mode ? additional: spi electrical data/timing table 7-118 , additional output switching characteristics of 4-pin chip-select option in master mode: updated/changed references of "vbusper" to "p" added associated "p = " footnote table 7-119 , additional output switching characteristics of 5-pin option in master mode: updated/changed all references of "vbusper" to "p" section 7.29.1 updated/changed "the jtag id register is a read-only ..." paragraph [cleared documentation jtag id (jtagid) register feedback issue] description(s) figure 7-96 , jtag id register description - dm6467 register value - 0xxb77 002f: updated/changed the variant reset value to "000 x"; silicon revision specific [cleared documentation feedback issue] table 7-150 , jtag id register selection bit descriptions: updated/changed the "variant (4-bit) value. dm6467 value:" description; silicon revision specific [cleared documentation feedback issue] revision history 8 submit documentation feedback
3 device overview 3.1 device characteristics tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-1 provides an overview of the tms320dm6467 soc. the table shows significant features of the device, including the capacity of on-chip ram, peripherals, internal peripheral bus frequency relative to the c64x+ dsp, and the package type with pin count. table 3-1. characteristics of the dm6467 processor hardware features dm6467 ddr2 memory controller ddr2 (16/32-bit bus width) asynchronous (8/16-bit bus width) ram, flash asynchronous emif (emifa) (nor, nand) 64 independent channels edma 8 qdma channels 2 64-bit general purpose (each configurable as 2 timers separate 32-bit timers) 1 64-bit watchdog 3 (with sir, mir, cir support and rts/cts flow uart control) (uart0 supports modem interface) spi 1 (supports 2 slave devices) i 2 c 1 (master/slave) 2 (one transmit/receive with 4 serializers, multichannel audio serial port (mcasp) one dit transmit only with 1 serializer for s/pdif output) 10/100/1000 ethernet mac with management data 1 (with mii/gmii interface) input/output (mdio) peripherals vlynq 1 not all peripherals pins are general-purpose input/output port (gpio) up to 33 pins available at the same time pwm 2 outputs (for more detail, see the ata 1 (ata/atapi-6) device configurations section). pci 1 (32-bit, 33 mhz) hpi 1 (16-/32-bit multiplexed address/data) 1 [horizontal and vertical downscaling, vdce chroma conversion (4:2:2 ? 4:2:0)] clock recovery generator (crgen) 1 power sleep controller (psc) 1 (peripheral/module clock gating) 2 8-bit bt.656 capture channels or configurable video port interface (vpif) 1 16-bit y/c capture channel or 99-mhz (-594) 1 8-/10-/12-bit raw video capture channel and 108-mhz (-729) 2 8-bit bt.656 display channels or 1 16-bit y/c display channel mpeg transport stream interface 1 with 8-bit parallel or serial input and output transport stream interface (tsif) 1 with serial-only input and output each with corresponding clock recovery generator (crgen) for external vcxo control. high- and full-speed device usb 2.0 high-, full-, and low-speed host submit documentation feedback device overview 9
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-1. characteristics of the dm6467 processor (continued) hardware features dm6467 size (bytes) 248kb ram, 8kb rom dsp 32kb l1 program (l1p)/cache (up to 32kb) 32kb l1 data (l1d)/cache (up to 32kb) 128kb unified mapped ram/cache (l2) on-chip memory organization arm 16kb i-cache 8kb d-cache 32kb ram 8kb rom cpu id + cpu rev id control status register (csr.[31:16]) 0x1000 c64x+ megamodule revision id register (mm_revid[15:0]) 0x0000 revision (address location: 0x0181 2000) jtagid register see section 7.29.1 , jtag id (jtagid) register jtag bsdl_id (address location: 0x01c4 0028) description(s) dsp 594 mhz (-594) dsp 729 mhz (-729) cpu frequency mhz arm926 297 mhz(-594) arm926 364.5 mhz(-729) dsp 1.68 ns (-594) dsp 1.37 ns (-729) cycle time ns arm926 3.37 ns (-594) arm926 2.74 ns (-729) normal 1.2 v (-594, -594a, -729, -729d) core (v) 1.2 v (-594v, -594av) smartreflex voltage (see table 4-39 ) 1.05 v (-594v, -594av) i/o (v) 1.8 v, 3.3 v (-594, -729) dev_clkin frequency multiplier (pllc1) x1 (bypass), x14 to x22 (-594) (27-mhz reference) x1 (bypass), x14 to x27 (-729) pll options dev_clkin frequency multiplier (pllc2) x1 (bypass), x14 to x22 (-594) (27-mhz reference) x1 (bypass), x14 to x23 (-729) aux_clkin frequency 24/48-mhz reference bga package 19 x 19 mm 529-pin bga (zut) process technology m m 0.09 m m product preview (pp), product status (1) advance information (ai), pd or production data (pd) (1) production data information is current as of publication date. products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. device overview 10 submit documentation feedback
3.2 device compatibility 3.3 arm subsystem 3.3.1 arm926ej-s risc cpu tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the arm926ej-s risc cpu is compatible with other arm9 cpus from arm holdings plc. the c64x+ dsp core is code-compatible with the c6000? dsp platform and supports features of the c64x dsp family. the arm subsystem is designed to give the arm926ej-s (arm9) master control of the device. in general, the arm is responsible for configuration and control of the device; including the dsp subsystem, the vpss subsystem, and a majority of the peripherals and external memories. the arm subsystem includes the following features: arm926ej-s risc processor armv5tej (32/16-bit) instruction set little endian operation co-processor 15 (cp15) mmu 16kb instruction cache 8kb data cache write buffer 32kb internal tightly-coupled memory (tcm) ram (32-bit wide access) 8kb internal rom (arm bootloader for non-emifa boot options) embedded trace module and embedded trace buffer (etm/etb) arm interrupt controller pll controller power and sleep controller (psc) system module the arm subsystem integrates the arm926ej-s processor. the arm926ej-s processor is a member of arm9 family of general-purpose microprocessors. this processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. the arm926ej-s processor supports the 32-bit arm and 16 bit thumb instruction sets, enabling the user to trade off between high performance and high code density. specifically, the arm926ej-s processor supports the armv5tej instruction set, which includes features for efficient execution of java byte codes, providing java performance similar to just in time (jit) java interpreter, but without associated code overhead. the arm926ej-s processor supports the arm debug architecture and includes logic to assist in both hardware and software debug. the arm926ej-s processor has a harvard architecture and provides a complete high performance subsystem, including: arm926ej -s integer core cp15 system control coprocessor memory management unit (mmu) separate instruction and data caches write buffer separate instruction and data tightly-coupled memories (tcms) [internal ram] interfaces separate instruction and data ahb bus interfaces embedded trace module and embedded trace buffer (etm/etb) submit documentation feedback device overview 11
3.3.2 cp15 3.3.3 mmu 3.3.4 caches and write buffer tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com for more complete details on the arm9, refer to the arm926ej-s technical reference manual, available at http://www.arm.com the arm926ej-s system control coprocessor (cp15) is used to configure and control instruction and data caches, tightly-coupled memories (tcms), memory management unit (mmu), and other arm subsystem functions. the cp15 registers are programmed using the mrc and mcr arm instructions, when the arm in a privileged mode such as supervisor or system mode. the arm926ej-s mmu provides virtual memory features required by operating systems such as linux?, windows? ce, ultron?, threadx?, etc. a single set of two level page tables stored in main memory is used to control the address translation, permission checks and memory region attributes for both data and instruction accesses. the mmu uses a single unified translation lookaside buffer (tlb) to cache the information held in the page tables. the mmu features are: standard arm architecture v4 and v5 mmu mapping sizes, domains and access protection scheme. mapping sizes are: ? 1mb (sections) ? 64kb (large pages) ? 4kb (small pages) ? 1kb (tiny pages) access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions) hardware page table walks invalidate entire tlb, using cp15 register 8 invalidate tlb entry, selected by mva, using cp15 register 8 lockdown of tlb entries, using cp15 register 10 the size of the instruction cache is 16kb, data cache is 8kb. additionally, the caches have the following features: virtual index, virtual tag, and addressed using the modified virtual address (mva) four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with two dirty bits in the dcache dcache supports write-through and write-back (or copy back) cache operation, selected by memory region using the c and b bits in the mmu translation tables. critical-word first cache refilling cache lockdown registers enable control over which cache ways are used for allocation on a line fill, providing a mechanism for both lockdown, and controlling cache corruption dcache stores the physical address tag (pa tag) corresponding to each dcache entry in the tag ram for use during the cache line write-backs, in addition to the virtual address tag stored in the tag ram. this means that the mmu is not involved in dcache write-back operations, removing the possibility of tlb misses related to the write-back address. cache maintenance operations provide efficient invalidation of, the entire dcache or icache, regions of the dcache or icache, and regions of virtual memory. the write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. a separate buffer is incorporated in the dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. the main write buffer has 16-word data buffer and a four-address buffer. the dcache write-back has eight data word entries and a single address entry. device overview 12 submit documentation feedback
3.3.5 tightly coupled memory (tcm) 3.3.6 advanced high-performance bus (ahb) 3.3.7 embedded trace macrocell (etm) and embedded trace buffer (etb) 3.3.8 arm memory mapping 3.3.8.1 arm internal memories 3.3.8.2 external memories tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 arm internal ram is provided for storing real-time and performance-critical code/data and the interrupt vector table. arm internal rom enables non-emifa boot options, such as nand and uart. the ram and rom memories interfaced to the arm926ej-s via the tightly coupled memory interface that provides for separate instruction and data bus connections. since the arm tcm does not allow instructions on the d-tcm bus or data on the i-tcm bus, an arbiter is included so that both data and instructions can be stored in the internal ram/rom. the arbiter also allows accesses to the ram/rom from extra-arm sources (e.g., edma or other masters). the arm926ej-s has built-in dma support for direct accesses to the arm internal memory from a non-arm master. because of the time-critical nature of the tcm link to the arm internal memory, all accesses from non-arm devices are treated as dma transfers. instruction and data accesses are differentiated via accessing different memory map regions, with the instruction region from 0x0000 through 0x7fff and data from 0x10000 through 0x17fff. the instruction region at 0x0000 and data region at 0x10000 map to the same physical 32-kb tcm ram. placing the instruction region at 0x0000 is necessary to allow the arm interrupt vector table to be placed at 0x0000, as required by the arm architecture. the internal 32-kb ram is split into two physical banks of 16kb each, which allows simultaneous instruction and data accesses to be accomplished if the code and data are in separate banks. the arm subsystem uses the ahb port of the arm926ej-s to connect the arm to the config bus and the external memories. arbiters are employed to arbitrate access to the separate d-ahb and i-ahb by the config bus and the external memories bus. to support real-time trace, the arm926ej-s processor provides an interface to enable connection of an embedded trace macrocell (etm). the arm926es-j subsystem in the dm6467 also includes the embedded trace buffer (etb). the etm consists of two parts: trace port provides real-time trace capability for the arm9. triggering facilities provide trigger resources, which include address and data comparators, counter, and sequencers. the dm6467 trace port is not pinned out and is instead only connected to the embedded trace buffer. the etb has a 4kb buffer memory. etb enabled debug tools are required to read/interpret the captured trace data. the arm memory map is shown in section 3.5 , memory map summary of this document. the arm has access to memories shown in the following sections. the arm has access to the following arm internal memories: 32kb arm internal ram on tcm interface, logically separated into two 16kb pages to allow simultaneous access on any given cycle if there are separate accesses for code (i-tcm bus) and data (d-tcm) to the different memory regions. 8kb arm internal rom the arm has access to the following external memories: ddr2 synchronous dram asynchronous emif / nor flash / nand flash ata submit documentation feedback device overview 13
3.3.8.3 dsp memories 3.3.8.4 arm-dsp integration 3.3.9 peripherals 3.3.10 pll controller (pllc) 3.3.11 power and sleep controller (psc) 3.3.12 arm interrupt controller (aintc) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the arm has access to the following dsp memories: l2 ram l1p ram l1d ram dm6467 arm and dsp integration features are as follows: dsp visibility from arm?s memory map, see section 3.5 , memory map summary, for details boot modes for dsp - see device configurations section, section 4.4.1 , dsp boot, for details arm control of dsp boot / reset - see device configurations section, section 4.4.2.4 , arm boot, for details arm control of dsp isolation and powerdown / powerup - see section 4 , device configurations, for details arm & dsp interrupts - see section 7.8.1 , arm cpu interrupts, and section 7.8.2 , dsp interrupts, for details the arm9 has access to all of the peripherals on the dm6467 device. the arm subsystem includes the pll controller. the pll controller contains a set of registers for configuring dm6467?s two internal plls (pll1 and pll2). the pll controller provides the following configuration and control: pll bypass mode set pll multiplier parameters set pll divider parameters pll power down oscillator power down the plls are briefly described in this document in the clocking section. for more detailed information on the plls and pll controller register descriptions, see the tms320dm646x dmsoc arm subsystem reference guide (literature number spruep9 ). the arm subsystem includes the power and sleep controller (psc). through register settings accessible by the arm9, the psc provides two levels of power savings: peripheral/module clock gating and power domain shut-off. brief details on the psc are given in section 7.3 , power supplies. for more detailed information and complete register descriptions for the psc, see the tms320dm646x dmsoc arm subsystem reference guide (literature number spruep9 ). the arm interrupt controller (aintc) accepts device interrupts and maps them to either the arm?s irq (interrupt request) or fiq (fast interrupt request). the arm interrupt controller is briefly described in this document in the interrupts section. for detailed information on the arm interrupt controller, see the tms320dm646x dmsoc arm subsystem reference guide (literature number spruep9 ). device overview 14 submit documentation feedback
3.3.13 system module 3.3.14 power management 3.4 dsp subsystem 3.4.1 c64x+ dsp cpu description tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the arm subsystem includes the system module. the system module consists of a set of registers for configuring and controlling a variety of system functions. for details and register descriptions for the system module, see section 4 , device configurations and see the tms320dm646x dmsoc arm subsystem reference guide (literature number spruep9 ). dm6467 has several means of managing power consumption. there is extensive use of clock gating, which reduces the power used by global device clocks and individual peripheral clocks. clock management can be utilized to reduce clock frequencies in order to reduce switching power. for more details on power management techniques, see section 4 , device configurations, section 7 , peripheral and electrical specifications, and see the tms320dm646x dmsoc arm subsystem reference guide (literature number spruep9 ). dm6467 gives the programmer full flexibility to use any and all of the previously mentioned capabilities to customize an optimal power management strategy. several typical power management scenarios are described in the following sections. the dsp subsystem includes the following features: c64x+ dsp cpu 32kb l1 program (l1p)/cache (up to 32kb) 32kb l1 data (l1d)/cache (up to 32kb) 128kb unified mapped ram/cache (l2) little endian the c64x+ central processing unit (cpu) consists of eight functional units, two register files, and two data paths as shown in figure 3-1 . the two general-purpose register files (a and b) each contain 32 32-bit registers for a total of 64 registers. the general-purpose registers can be used for data or can be data address pointers. the data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 lsbs of data placed in an even register and the remaining 8 or 32 msbs in the next upper register (which is always an odd-numbered register). the eight functional units (.m1, .l1, .d1, .s1, .m2, .l2, .d2, and .s2) are each capable of executing one instruction every clock cycle. the .m functional units perform all multiply operations. the .s and .l units perform a general set of arithmetic, logical, and branch functions. the .d units primarily load data from memory to the register file and store results from the register file into memory. the c64x+ cpu extends the performance of the c64x core through enhancements and new features. each c64x+ .m unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). there is also support for galois field multiplication for 8-bit and 32-bit data. many communications algorithms such as ffts and modems require complex multiplication. the complex multiply (cmpy) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. there are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. the 32 x 32 bit multiply instructions provide the extended precision necessary for audio and other high-precision algorithms on a variety of signed and unsigned 32-bit data types. submit documentation feedback device overview 15
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the .l or (arithmetic logic unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. there are also saturated forms of these instructions. the c64x+ core enhances the .s unit in several ways. in the c64x core, dual 16-bit min2 and max2 comparisons were only available on the .l units. on the c64x+ core they are also available on the .s unit which increases the performance of algorithms that do searching and sorting. finally, to increase data packing and unpacking throughput, the .s unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. unpack instructions prepare 8-bit data for parallel 16-bit operations. pack instructions return parallel results to output precision including saturation support. other new features include: sploop - a small instruction buffer in the cpu that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. the sploop buffer reduces the code size associated with software pipelining. furthermore, loops in the sploop buffer are fully interruptible. compact instructions - the native instruction size for the c6000 devices is 32 bits. many common instructions such as mpy, and, or, add, and sub can be expressed as 16 bits if the c64x+ compiler can restrict the code to use certain registers in the register file. this compression is performed by the code generation tools. instruction set enhancement - as noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit galois field multiplication. exceptions handling - intended to aid the programmer in isolating bugs. the c64x+ cpu is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration). privilege - defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. local memory is divided into multiple pages, each with read, write, and execute permissions. time-stamp counter - primarily targeted for real-time operating system (rtos) robustness, a free-running time-stamp counter is implemented in the cpu which is not sensitive to system stalls. for more details on the c64x+ cpu and its enhancements over the c64x architecture, see the following documents: tms320c64x/c64x+ dsp cpu and instruction set reference guide (literature number spru732) tms320c64x technical overview (literature number spru395) 16 device overview submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 figure 3-1. tms320c64x+? cpu (dsp core) data paths submit documentation feedback device overview 17 src2 src2 .d1 .m1 .s1 .l1 long src odd dst src2 src1 src1src1 src1 even dsteven dst odd dst dst1 dst src2 src2 src2 long src da1 st1bld1b ld1a st1a data path a odd register file a (a1, a3, a5...a31) odd register file b (b1, b3, b5...b31) .d2 src1 dst src2 da2 ld2a ld2b src2 .m2 src1 dst1 .s2 src1 even dst long src odd dst st2a st2b long src .l2 even dst odd dst src1 data path b control register 32 msb 32 lsb dst2 (a) 32 msb 32 lsb 2x1x 32 lsb 32 msb 32 lsb 32 msb dst2 (b) (b) (a) 8 8 8 8 32 32 32 32 (c) (c) even register file a (a0, a2, a4...a30) even register file b (b0, b2, b4...b30) (d) (d) (d) (d) a. on .m unit, dst2 is 32 msb. b. on .m unit, dst1 is 32 lsb. c. on c64x cpu .m unit, src2 is 32 bits; on c64x+ cpu .m unit, src2 is 64 bits. d. on .l and .s units, odd dst connects to odd register files and even dst connects to even register files.
3.4.2 dsp memory mapping 3.4.2.1 arm internal memories 3.4.2.2 external memories 3.4.2.3 dsp internal memories 3.4.2.4 c64x+ cpu tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the dsp memory map is shown in section 3.5 , memory map summary. configuration of the control registers for ddr2, emifa, and arm internal ram is supported by the arm. the dsp has access to memories shown in the following sections. the dsp has access to the 32kb arm internal ram on the arm d-tcm interface (i.e., data only). the dsp has access to the following external memories: ddr2 synchronous dram asynchronous emif / nor flash ata the dsp has access to the following dsp memories: l2 ram l1p ram l1d ram the c64x+ core uses a two-level cache-based architecture. the level 1 program memory/cache (l1p) consists of 32 kb memory space that can be configured as mapped memory or direct mapped cache. the level 1 data memory/cache (l1d) consists of 32 kb that can be configured as mapped memory or 2-way set associated cache. the level 2 memory/cache (l2) consists of a 128 kb ram memory space that is shared between program and data space. l2 memory can be configured as mapped memory, cache, or a combination of both. table 3-2 shows a memory map of the c64x+ cpu cache registers for the device. table 3-2. c64x+ cache registers hex address range register acronym description 0x0184 0000 l2cfg l2 cache configuration register 0x0184 0020 l1pcfg l1p size cache configuration register 0x0184 0024 l1pcc l1p freeze mode cache configuration register 0x0184 0040 l1dcfg l1d size cache configuration register 0x0184 0044 l1dcc l1d freeze mode cache configuration register 0x0184 0048 - 0x0184 0ffc - reserved 0x0184 1000 edmaweight l2 edma access control register 0x0184 1004 - 0x0184 1ffc - reserved 0x0184 2000 l2alloc0 l2 allocation register 0 0x0184 2004 l2alloc1 l2 allocation register 1 0x0184 2008 l2alloc2 l2 allocation register 2 0x0184 200c l2alloc3 l2 allocation register 3 0x0184 2010 - 0x0184 3fff - reserved 0x0184 4000 l2wbar l2 writeback base address register 0x0184 4004 l2wwc l2 writeback word count register 0x0184 4010 l2wibar l2 writeback invalidate base address register 0x0184 4014 l2wiwc l2 writeback invalidate word count register 0x0184 4018 l2ibar l2 invalidate base address register 0x0184 401c l2iwc l2 invalidate word count register device overview 18 submit documentation feedback
3.4.3 peripherals 3.4.4 dsp interrupt controller tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-2. c64x+ cache registers (continued) hex address range register acronym description 0x0184 4020 l1pibar l1p invalidate base address register 0x0184 4024 l1piwc l1p invalidate word count register 0x0184 4030 l1dwibar l1d writeback invalidate base address register 0x0184 4034 l1dwiwc l1d writeback invalidate word count register 0x0184 4038 - reserved 0x0184 4040 l1dwbar l1d block writeback 0x0184 4044 l1dwwc l1d block writeback 0x0184 4048 l1dibar l1d invalidate base address register 0x0184 404c l1diwc l1d invalidate word count register 0x0184 4050 - 0x0184 4fff - reserved 0x0184 5000 l2wb l2 writeback all register 0x0184 5004 l2wbinv l2 writeback invalidate all register 0x0184 5008 l2inv l2 global invalidate without writeback 0x0184 500c - 0x0184 5027 - reserved 0x0184 5028 l1pinv l1p global invalidate 0x0184 502c - 0x0184 5039 - reserved 0x0184 5040 l1dwb l1d global writeback 0x0184 5044 l1dwbinv l1d global writeback with invalidate 0x0184 5048 l1dinv l1d global invalidate without writeback 0x0184 8000 - 0x0184 803c mar0 - mar15 reserved (corresponds to byte address 0x0000 0000 - 0x0fff ffff) memory attribute registers for arm tcm (corresponds to byte address 0x0184 8040 mar16 0x1000 0000 - 0x10ff ffff) 0x0184 8044 - 0x0184 80fc mar17 - mar63 reserved (corresponds to byte address 0x1100 0000 - 0x3fff ffff) 0x0184 8100 mar64 reserved (corresponds to byte address 0x4000 0000 - 0x40ff ffff) 0x0184 8104 mar65 reserved (corresponds to byte address 0x4100 0000 - 0x41ff ffff) memory attribute registers for emifa (corresponds to byte address 0x4200 0x0184 8108 - 0x0184 8124 mar66 - mar73 0000 - 0x49ff ffff) 0x0184 8128 - 0x0184 812c mar74 - mar75 reserved (corresponds to byte address 0x4a00 0000 - 0x4bff ffff) memory attribute registers for vlynq (corresponds to byte address 0x0184 8130 - 0x0184 813c mar76 - mar79 0x4c00 0000 - 0x4fff ffff) 0x0184 8140 - 0x0184 81fc mar80 - mar127 reserved (corresponds to byte address 0x5000 0000 - 0x7fff ffff) memory attribute registers for ddr2 (corresponds to byte address 0x8000 0x0184 8200 - 0x0184 82fc mar128 - mar191 0000 - 0xbfff ffff) 0x0184 8300 - 0x0184 83fc mar192 - mar255 reserved (corresponds to byte address 0xc000 0000 - 0xffff ffff) the dsp has access/controllability of the following peripherals: hdvicp0/1 edma mcasp0/1 2 timers (timer0 and timer1) that can each be configured as 1 64-bit or 2 32-bit timers the dsp interrupt controller accepts device interrupts and appropriately maps them to the dsp?s available interrupts. the dsp interrupt controller is briefly described in this document in the interrupts section. for more detailed on the dsp interrupt controller, see the tms320c64x+ dsp megamodule reference guide (literature number spru871 ). submit documentation feedback device overview 19
3.5 memory map summary tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-3 shows the memory map address ranges of the device. table 3-4 depicts the expanded map of the configuration space (0x0180 0000 through 0x0fff ffff). the device has multiple on-chip memories associated with its two processors and various subsystems. to help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters. 20 device overview submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-3. memory map summary master peripheral accessibility (1) start end size edma/ arm c64x+ video tsif address address (bytes) peripheral vdce emac hpi pci usb vlynq ata port (0/1) 0x0000 0000 0x0000 3fff 16k arm ram0 (instruction) 0x0000 4000 0x0000 7fff 16k arm ram1 (instruction) 0x0000 8000 0x0000 ffff 32k arm rom (instruction) 0x0001 0000 0x0001 3fff 16k arm ram0 (data) 0x0001 4000 0x0001 7fff 16k arm ram1 (data) 0x0001 8000 0x0001 ffff 32k arm rom (data) reserved reserved 0x0002 0000 0x000f ffff 896k 0x0010 0000 0x003f ffff 3m 0x0040 0000 0x004f ffff 1m 0x0050 0000 0x005f ffff 1m reserved 0x0060 0000 0x006f ffff 1m 0x0070 0000 0x007f ffff 1m 0x0080 0000 0x0080 ffff 64k 0x0081 0000 0x0081 7fff 32k reserved hole (mppa disable) (2) reserved 0x0081 8000 0x0083 7fff 128k l2 ram/cache 0x0083 8000 0x008f ffff 800k reserved 0x0090 0000 0x0092 ffff 192k 0x0093 0000 0x009f ffff 832k 0x00a0 0000 0x00df ffff 4m reserved 0x00e0 0000 0x00e0 7fff 32k l1p ram/cache 0x00e0 8000 0x00ef ffff 992k reserved 0x00f0 0000 0x00f0 7fff 32k l1d ram/cache reserved 0x00f0 8000 0x017f ffff 9184k reserved 0x0180 0000 0x01bb ffff 3840k 0x01bc 0000 0x01bc 0fff 4k arm etb memory 0x01bc 1000 0x01bc 17ff 2k arm etb registers cfg space 0x01bc 1800 0x01bc 18ff 256 arm icecrusher 0x01bc 1900 0x01bc 1bff 768 reserved 0x01bc 1c00 0x01bf ffff 249k 0x01c0 0000 0x0fff ffff 228m cfg bus peripherals cfg bus peripherals cfg bus peripherals (3) (3) (3) 0x1000 0000 0x1000 ffff 64k reserved 0x1001 0000 0x1001 3fff 16k arm ram0 (data) arm ram0 (data) 0x1001 4000 0x1001 7fff 16k arm ram1 (data) arm ram1 (data) 0x1001 8000 0x1001 ffff 32k arm rom (data) arm rom (data) 0x1002 0000 0x10ff ffff 16256k 0x1100 0000 0x113f ffff 4m reserved 0x1140 0000 0x114f ffff 1m 0x1150 0000 0x115f ffff 1m reserved reserved 0x1160 0000 0x116f ffff 1m 0x1170 0000 0x117f ffff 1m 0x1180 0000 0x1180 ffff 64k 0x1181 0000 0x1181 7fff 32k reserved hole (mppa disable) (2) reserved 0x1181 8000 0x1183 7fff 128k l2 ram/cache l2 ram/cache l2 ram/cache 0x1183 8000 0x118f ffff 800k reserved reserved reserved 0x1190 0000 0x11df ffff 5m 0x11e0 0000 0x11e0 7fff 32k l1p ram/cache l1p ram/cache l1p ram/cache 0x11e0 8000 0x11ef ffff 992k reserved reserved reserved (1) these peripherals have their own dma engine or master port interface to the dmsoc system bus and do not use the edma for data transfers. the symbol indicates that the peripheral has a valid connection through the device switch fabric to the memory region identified in the edma access column. (2) mppa should be used to disable the hole. for more information on mppa, see the tms320c64x+ dsp megamodule reference guide (spru871 ). (3) the hpi's, pci's, and vlynq's access to the configuration bus peripherals is limited, see table 3-4 , configuration memory map summary for the details. submit documentation feedback device overview 21
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-3. memory map summary (continued) master peripheral accessibility (1) start end size edma/ arm c64x+ video tsif address address (bytes) peripheral vdce emac hpi pci usb vlynq ata port (0/1) 0x11f0 0000 0x11f0 7fff 32k l1d ram/cache l1d ram/cache l1d ram/cache 0x11f0 8000 0x11ff ffff 992k reserved reserved reserved 0x1200 0000 0x1fff ffff 224m 0x2000 0000 0x2000 7fff 32k ddr2 control ddr2 control ddr2 control registers registers registers 0x2000 8000 0x2000 ffff 32k emifa control emifa registers emifa registers registers 0x2001 0000 0x2001 7fff 32k vlynq control vlynq registers vlynq registers registers 0x2001 8000 0x200f ffff 928k reserved reserved reserved 0x2010 0000 0x2fff ffff 255m 0x3000 0000 0x3fff ffff 256m pci data pci data pci data 0x4000 0000 0x403f ffff 4m reserved reserved reserved 0x4040 0000 0x4043 ffff 256k 0x4044 0000 0x4047 ffff 256k 0x4048 0000 0x404b ffff 256k 0x404c 0000 0x404f ffff 256k 0x4050 0000 0x405f ffff 1m 0x4060 0000 0x4063 ffff 256k reserved reserved reserved 0x4064 0000 0x4067 ffff 256k 0x4068 0000 0x406b ffff 256k 0x406c 0000 0x406f ffff 256k 0x4070 0000 0x41ff ffff 25m 0x4200 0000 0x43ff ffff 32m emifa data ( cs2) (4) emifa data ( cs2) (4) emifa data ( cs2) (4) 0x4400 0000 0x45ff ffff 32m emifa data ( cs3) (4) emifa data ( cs3) (4) emifa data ( cs3) (4) 0x4600 0000 0x47ff ffff 32m emifa data ( cs4) (4) emifa data ( cs4) (4) emifa data ( cs4) (4) 0x4800 0000 0x49ff ffff 32m emifa data ( cs5) (4) emifa data ( cs5) (4) emifa data ( cs5) (4) 0x4a00 0000 0x4bff ffff 32m reserved reserved reserved 0x4c00 0000 0x4fff ffff 64m vlynq (remote data) vlynq (remote data) vlynq (remote data) 0x5000 0000 0x7fff ffff 768m reserved reserved reserved 0x8000 0000 0x9fff ffff 512m ddr2 memory ddr2 memory ddr2 memory 0xa000 0000 0xbfff ffff 512m reserved reserved reserved 0xc000 0000 0xffff ffff 1g reserved reserved reserved (4) emifa cs0 and cs1 are not functionally supported on the dm6467, and therefore, are not pinned out. device overview 22 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-4. configuration memory map summary master peripheral start end size accessibility arm/edma c64x+ address address (bytes) hpi pci vlynq 0x0180 0000 0x0180 ffff 64k c64x+ interrupt controller 0x0181 0000 0x0181 0fff 4k c64x+ powerdown controller 0x0181 1000 0x0181 1fff 4k c64x+ security id 0x0181 2000 0x0181 2fff 4k c64x+ revision id reserved 0x0182 0000 0x0182 ffff 64k c64x+ emc 0x0183 0000 0x0183 ffff 64k reserved 0x0184 0000 0x0184 ffff 64k c64x+ memory system 0x0185 0000 0x01bb ffff 3520k reserved 0x01bc 0000 0x01bc 00ff 256 0x01bc 0100 0x01bc 01ff 256 arm etb memory 0x01bc 0200 0x01bc 0fff 3.5k reserved 0x01bc 1000 0x01bc 17ff 2k arm etb registers 0x01bc 1800 0x01bc 18ff 256 arm ice crusher 0x01bc 1900 0x01bf ffff 255744 reserved 0x01c0 0000 0x01c0 ffff 64k edma cc edma cc 0x01c1 0000 0x01c1 03ff 1k edma tc0 edma tc0 0x01c1 0400 0x01c1 07ff 1k edma tc1 edma tc1 0x01c1 0800 0x01c1 0bff 1k edma tc2 edma tc2 0x01c1 0c00 0x01c1 0fff 1k edma tc3 edma tc3 0x01c1 1000 0x01c1 1fff 4k reserved reserved 0x01c1 2000 0x01c1 23ff 1k video port 0x01c1 2400 0x01c1 27ff 1k reserved reserved 0x01c1 2800 0x01c1 2fff 2k vdce 0x01c1 3000 0x01c1 33ff 1k tsif0 0x01c1 3400 0x01c1 37ff 1k tsif1 0x01c1 3800 0x01c1 9fff 26k reserved reserved 0x01c1 a000 0x01c1 a7ff 2k pci control registers 0x01c1 a800 0x01c1 ffff 22k reserved reserved 0x01c2 0000 0x01c2 03ff 1k uart0 0x01c2 0400 0x01c2 07ff 1k uart1 0x01c2 0800 0x01c2 0bff 1k uart2 0x01c2 0c00 0x01c2 0fff 1k reserved reserved 0x01c2 1000 0x01c2 13ff 1k i2c 0x01c2 1400 0x01c2 17ff 1k timer0 timer0 0x01c2 1800 0x01c2 1bff 1k timer1 timer1 0x01c2 1c00 0x01c2 1fff 1k timer2 (watchdog) timer2 (watchdog) 0x01c2 2000 0x01c2 23ff 1k pwm0 0x01c2 2400 0x01c2 27ff 1k pwm1 0x01c2 2800 0x01c2 5fff 14k reserved reserved 0x01c2 6000 0x01c2 63ff 1k crgen0 0x01c2 6400 0x01c2 67ff 1k crgen1 0x01c2 6800 0x01c3 ffff 102k reserved reserved 0x01c4 0000 0x01c4 07ff 2k system module system module 0x01c4 0800 0x01c4 0bff 1k pll controller 1 pll controller 1 0x01c4 0c00 0x01c4 0fff 1k pll controller 2 pll controller 2 0x01c4 1000 0x01c4 1fff 4k power and sleep controller power and sleep controller 0x01c4 2000 0x01c4 7fff 24k reserved reserved 0x01c4 8000 0x01c4 83ff 1k arm interrupt controller reserved 0x01c4 8400 0x01c6 3fff 111k reserved reserved submit documentation feedback device overview 23
3.6 pin assignments 3.6.1 pin map (bottom view) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-4. configuration memory map summary (continued) master peripheral start end size accessibility arm/edma c64x+ address address (bytes) hpi pci vlynq 0x01c6 4000 0x01c6 5fff 8k usb2.0 registers / ram 0x01c6 6000 0x01c6 67ff 2k ata 0x01c6 6800 0x01c6 6fff 2k spi 0x01c6 7000 0x01c6 77ff 2k gpio 0x01c6 7800 0x01c6 7fff 2k hpi hpi 0x01c6 8000 0x01c7 ffff 96k reserved reserved 0x01c8 0000 0x01c8 0fff 4k emac control registers 0x01c8 1000 0x01c8 1fff 4k emac control module registers reserved 0x01c8 2000 0x01c8 3fff 8k emac control module ram 0x01c8 4000 0x01c8 47ff 2k mdio control registers 0x01c8 4800 0x01d0 0fff 498k reserved reserved 0x01d0 1000 0x01d0 13ff 1k mcasp0 registers mcasp0 registers 0x01d0 1400 0x01d0 17ff 1k mcasp0 data port mcasp0 data port 0x01d0 1800 0x01d0 1bff 1k mcasp1 registers mcasp1 registers 0x01d0 1c00 0x01d0 1fff 1k mcasp1 data port mcasp1 data port 0x01d0 2000 0x01df ffff 1016k reserved reserved 0x01e0 0000 0x01ff ffff 2m reserved reserved 0x0200 0000 0x021f ffff 2m reserved reserved 0x0220 0000 0x023f ffff 2m reserved reserved 0x0240 0000 0x0fff ffff 220m reserved reserved extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. for more information on pin muxing, see section 4.7 , multiplexed pin configurations, of this document. figure 3-2 through figure 3-7 show the bottom view of the package pin assignments in six quadrants (a, b, c, d, e, and f). 24 device overview submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 figure 3-2. pin map [section a] submit documentation feedback device overview 25 v ss v ss gp[4]/ stc_clkin vp_dout1/ btmode1 vp_dout6/ dspboot vp_dout5/ pcien vp_dout14/ ts1_pstin vp_dout9/ ts1_enao v ss ahclkr0 gp[3]/ audio_clk0 tout1u vp_dout0/ btmode0 vp_dout3/ btmode3 vp_dout7/ vadjen vp_dout15/ ts1_din aclkx0 aclkr0 amutein0 gp[2]/ audio_clk1 tout1l tinp0u vp_dout4/ cs2bw vp_dout12/ ts1_waito ahclkx0 amute0 afsr0 afsx0 tout2 tinp1l tinp0l vp_dout2/ btmode2 aclkx1 ahclkx1 axr0[3] axr0[2] gp[0] reset tout0u tout0l spi_clk axr1[0] axr0[0] axr0[1] gp[1] v ss dv dd33 dv dd33 vlynq_ clock vlynq_ scrun spi_cs1 sda scl dv dd33 cv dd vlynq_txd1 vlynq_txd2 vlynq_txd3 spi_cs0 spi_en 1 2 ac abaa y w v u t mtclk vlynq_rxd2 vlynq_rxd3 vlynq_txd0 spi_somi mtxd7 gmtclk vlynq_rxd1 vlynq_rxd0 spi_simo mtxd3 mtxd4 mtxd5 mtxd6 r p n 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ac abaa y w v u t r p n v ss v ss dv dd33 cv dd cv dd dv dd33 v ss v ss cv dd cv dd v ss v ss v ss v ss a b c d e f
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com figure 3-3. pin map [section b] 26 device overview submit documentation feedback a b c d e f vp_clkin3/ ts1_clko vp_clko3/ ts0_clko ts1_clkin ucts0/ usd0 vp_clkin0 vp_din4/ ts0_dout4/ ts1_waito vp_din0/ ts0_dout0 vp_din8/ ts0_din0 vp_dout8/ ts1_waitin vp_dout11/ ts1_dout udsr0/ ts0_psto/ gp[37] v ss urxd0/ ts1_din vp_din5/ ts0_dout5/ ts1_en_waito vp_din1/ ts0_dout1 vp_din9/ ts0_din1 vp_clko2 vp_dout10/ ts1_psto udcd0/ ts0_waitin/ gp[38] dv dd33 urts0/ uirtx0/ ts1_en_waito vp_din6/ ts0_dout6/ ts1_pstin vp_din2/ ts0_dout2 vp_din10/ ts0_din2 vp_dout13/ ts1_en_waito vp_clkin2 urin0/ gp[8]/ ts1_waitin udtr0/ ts0_enao/ gp[36] utxd0/ urctx0/ ts1_pstin vp_din7/ ts0_dout7/ ts1_din vp_din3/ ts0_dout3 vp_din11/ ts0_din3 dv dd33 cv dd 9 10 ac abaa y w v u t r p n 11 12 13 14 15 16 9 10 11 12 13 14 15 16 ac abaa y w v u t r p n dv dd33 dv dd33 dv dd33 dv dd33 dv dd33 dv dd33 dv dd33 cv dd cv dd cv dd cv dd cv dd cv dd cv dd v ss v ss v ss v ss cv dd cv dd cv dd cv dd cv dd cv dd cv dd cv dd v ss cv dd cv dd cv dd v ss v ss cv dd cv dd cv dd cv dd cv dd cv dd v ss v ss cv dd cv dd cv dd cv dd cv dd cv dd v ss v ss v ss v ss v ss v ss v ss v ss
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 figure 3-4. pin map [section c] submit documentation feedback device overview 27 vp_din12/ ts0_din4 vp_din15_ vp_vsync/ ts0_din7 ts0_clkin urts2/ uirtx2/ ts0_pstin/ gp[41] ucts2/usd2/ crg0_vcxi/ gp[42]/ ts1_psto v ss vp_din13_ field/ ts0_din5 vp_clkin1 utxd1/ urctx1/ ts0_dout7/ gp[24] v ss ddr_d[23] vp_din14_ vp_hsync/ ts0_din6 urts1/ uirtx1/ ts0_waito/ gp[25] utxd2/urctx2/ crg1_po/ gp[40]/ crg0_po dv ddr2 ddr_d[28] ddr_d[21] ddr_d[20] ucts1/usd1/ ts0_en_waito/ gp[26] urxd1/ ts0_din7/ gp[23] ddr_d[31] ddr_d[29] ddr_d[22] ddr_dqm[2] pwm0/ crg0_po/ ts1_enao 17 18 ac abaa y w v u t r p n 19 20 21 22 23 17 18 19 20 21 22 23 ac abaa y w v u t r p n a b c d e f pwm1/ ts1_dout v ss ddr_d[30] dv ddr2 v ss ddr_dqs[2] ddr_d[19] ddr_dqs[2] ddr_dqs[3] ddr_dqm[3] v ss v ss ddr_dqs[3] ddr_d[27] dv ddr2 ddr_d[24] ddr_d[18] ddr_d[16] v ss v ss dv ddr2 v ss dv ddr2 ddr_a[10] ddr_d[17] ddr_d[26] ddr_d[25] dv ddr2 ddr_dqgate2 ddr_a[1] ddr_a[3] ddr_dqgate3 ddr_a[12] ddr_ba[2] ddr_vref v ss dv ddr2 ddr_a[14] ddr_a[9] ddr_a[5] ddr_a[7] ddr_ba[0] v ss v ss v ss v ss dv dd33 dv ddr2 v ss urxd2/ crg1_vcxi/ gp[39]/ crg0_vcxi v ss v ss
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com figure 3-5. pin map [section d] 28 device overview submit documentation feedback mtxd0 mtxen mcrs mcol mrclk mrxd7 mrxd6 v ss mrxd4 mrxd3 mrxd2 mrxdv rftclk mrxd1 mrxer mdio mdclk dv dd33 1 2 l k j h g f e d c ba 3 4 5 6 7 8 1 2 3 4 5 6 7 8 lk j h g f e d c b a a b c d e f dv dd33 pci_ad0/ hd0/ em_d0 pci_ad2/ hd2/ em_d2 pci_ad4/ hd4/ em_d4 v ss dv dd33 cv dd v ss v ss pci_ad9/ hd9/ em_d9 pci_cbe0 ata_cs0 / / gp[33]/ em_a[18] pci_ad6/ hd6/ em_d6 pci_ad3/ hd3/ em_d3 pci_ad1/ hd1/ em_d1 pci_ad13/ hd13/ em_d13 pci_ad15/ hd15/ em_d15 pci_ad11/ hd11/ em_d11 pci_par/ / has em_dqm0 pci_idsel/ hddir/ em_r/w pci_ad18/ dd2/ hd18/ em_a[2] pci_trdy/ hhwil/ em_a[16]/(ale) pci_ad7/ hd7/ em_d7 pci_ad5/ hd5/ em_d5 pci_ad10/ hd10/ em_d10 pci_ad8/ hd8/ em_d8 pci_ad12/ hd12/ em_d12 pci_ad24/ dd8/ hd24/ em_a[8] pci_ad20/ dd4/ hd20/ em_a[4] pci_frame hint / / em_ba[0] pci_stop em_we / hcntl0/ pci_ad26/ dd10/hd26/ em_a[10] pci_cbe2 hds2 em_cs2 / / pci_cbe1 ata_cs1 / / gp[32]/ em_a[19] pci_ad14/ hd14/ em_d14 pci_perr hcs em_dqm1 / / pci_ad22/ dd6/ hd22/ em_a[6] pci_ad16/ dd0/ hd16/ em_a[0] pci_ad21/ dd5/ hd21/ em_a[5] pci_ad29/ dd13/hd29/ em_a[13] pci_ad17/ dd1/ hd17/ em_a[1] pci_serr hds1 em_oe / / v ss pci_devsel/ hcntl1/ em_ba[1] pci_ad25/ dd9/ hd25/ em_a[9] pci_ad23/ dd7/ hd23/ em_a[7] pci_ad31/ dd15/hd31/ em_a[15] v ss pci_ad27/ dd11/ hd27/ em_a[11] pci_cbe3 w em_cs3 / hr/ / pci_ad19/ dd3/ hd19/ em_a[3] pci_irdy hrdy / / em_a[17]/(cle) rsv2 rsv1 mtxd1 mtxd2 m m v ss v ss v ss v ss v ss v ss v ss v ss cv dd dv dd33 dv dd33 v ss mrxd5 v ss dv dd33 cv dd cv dd cv dd cv dd dv dd33 v ss mrxd0 dv dd33
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 figure 3-6. pin map [section e] submit documentation feedback device overview 29 a b c d e f v ss dv dd33 9 10 l k j h g f e d c ba 11 12 13 14 15 16 9 10 11 12 13 14 15 16 lk j h g f e d c b a rsv7 trst tdi gp[6]/ cvddadj0 tms aux_cv dd dev_cv dd dev_dv ss pci_rsv3 / gp[19]/ em_wait5/ (rdy5/ ) dior bsy5 pci_rsv1/ da0/ gp[17]/ em_a[20] pci_gnt dmack em_cs4 / / gp[12]/ pci_ad28/ dd12/hd28/ em_a[12] pci_rsv5/ iordy/ gp[21]/ em_wait3/ (rdy3/ ) bsy3 aux_dv dd18 dev_dv dd18 rsv5 tdo aux_dv ss rtck pci_rst/ da2/ gp[13]/ em_a[22] pci_ad30/ dd14/hd30/ em_a[14] pci_inta bsy2 / em_wait2/ (rdy2/ ) dev_v ss pll1v ss clkout0 tck pci_rsv2/ intrq/ gp[18]/ em_rsv0 pci_req em_cs5 / dmarq/ gp[11]/ gp[5] pll1v dd18 emu1 pll2v ss v ss dev_mxo emu0 gp[7]/ cvddadj1 pci_rsv4/ / gp[20]/ em_wait4/ (rdy4/ ) diow bsy4 pci_clk/ gp[10] pci_rsv0/ da1/ gp[16]/ em_a[21] m m v ss v ss v ss v ss v ss v ss v ss v ss cv dd v ss cv dd cv dd v ss dev_mxi/ dev_clkin v ss v ss v ss v ss v ss v ss v ss cv dd cv dd cv dd cv dd cv dd cv dd cv dd v ss cv dd cv dd cv dd cv dd cv dd cv dd cv dd cv dd v ss v ss v ss cv dd cv dd cv dd cv dd cv dd cv dd cv dd dv dd33 dv dd33 dv dd33 dv dd33 dv dd33 dv dd33 dv dd33 pll2v dd18
3.7 terminal functions 3.7.1 boot tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com figure 3-7. pin map [section f] the terminal functions tables (table 3-5 through table 3-32 ) identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description. for more detailed information on device configuration, peripheral selection, multiplexed/shared pin, and see the device configurations section of this data manual. 30 device overview submit documentation feedback ddr_a[2] ddr_clk ddr_zp ddr_we ddr_cas v ss dv ddr2 ddr_ras dv ddr2 ddr_a[11] ddr_dqgate0 ddr_cs ddr_dqgate1 ddr_a[4] ddr_a[8] ddr_d[7] ddr_a[13] ddr_d[15] ddr_a[0] dv ddr2 17 18 l k j h g f e d c ba 19 20 21 22 23 17 18 19 20 21 22 23 l kj h g f e d c b a a b c d e f dv ddr2 ddr_d[4] ddr_d[6] ddr_d[13] ddr_d[14] ddr_d[12] ddr_dqm[1] ddr_d[5] ddr_dqm[0] v ss usb_v dda3p3 ddr_dqs[0] dv ddr2 v ss ddr_d[1] ddr_d[11] usb_v dd1p8 usb_ v dda1p2ldo usb_r1 por v ss ddr_dqs[1] ddr_dqs[1] ddr_dqs[0] ddr_d[2] usb_v ssref ddr_d[8] ddr_d[10] ddr_d[0] ddr_d[3] usb_ drvvbus/ gp[22] ddr_d[9] v ss dv ddr2 rsv4 rsv3 usb_dn usb_dp v ss aux_mxo v ss aux_mxi/ aux_clkin rsv6 aux_v ss v ss ddr_odt0 v ss v ss ddr_a[6] ddr_clk ddr_zn ddr_cke ddr_ba[1] v ss m m v ss v ss dv ddr2 v ss dv ddr2 v ss v ss v ss v ss v ss
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-5. boot terminal functions signal type (1) other (2) (3) description name no. boot arm boot mode configuration bits. these pins are multiplexed between arm boot mode and the video port interface (vpif). at reset, the boot mode inputs btmode[3:0] are sampled to determine the arm boot configuration. see below the boot modes set by these inputs. for more details on the types of boot modes, see the section 4.4.1 , boot modes. after reset, these pins are video port data outputs 3 through 0 (vp_dout[3:0]). btmode[3:0] arm boot mode 0000 emulation boot (pcien = 0) 0001 reserved hpi boot (16-bit width) (if pcien = 0) vp_dout0/ ipd 0010 or ab5 i/o/z btmode0 dv dd33 pci boot without auto-initialization (if pcien = 1) hpi boot (32-bit width) (if pcien = 0) 0011 or pci boot with auto-initialization (if pcien = 1) emifa direct boot (rom/nor) (pcien = 0) [error if pcien = 0100 1; defaults to uart0] vp_dout1/ ipd 0101 reserved ac4 i/o/z btmode1 dv dd33 0110 i2c boot 0111 nand flash boot (pcien = 0) [error if pcien = 1] 1000 uart0 boot 1001 reserved vp_dout2/ ipd y8 i/o/z btmode2 dv dd33 1010 reserved 1011 reserved 1100 - 1101 reserved vp_dout3/ ipd ab6 i/o/z 1110 spi boot btmode3 dv dd33 1111 reserved device control emifa cs2 space data bus width. this pin is multiplexed between emifa control and the vpif. at reset, the input state is sampled to set the emifa data bus width for the cs2 (boot) chip select region. vp_dout4/ ipd aa7 i/o/z cs2bw dv dd33 for an 8-bit-wide emifa data bus, cs2bw = 0. for a 16-bit-wide emifa data bus, cs2bw = 1. after reset, this pin is video port data output 4 (vp_dout4). pci enable. this pin is multiplexed between pci control and the vpif. at reset, the input state is sampled to enable/disable the pci interface pin multiplexing. note: when pci boot mode is not used, for proper device operation out of reset pcien must be "0". vp_dout5/ ipd ac6 i/o/z pcien dv dd33 0 = pci pin function is disabled; emifa or hpi pin function enabled 1 = pci pin function is enabled after reset, this pin is video port data output 5 (vp_dout5).- dsp boot source bit. this pin is multiplexed between dsp boot and the vpif. at reset, the input state is sampled to set the dsp boot source dspboot. vp_dout6/ ipd the dsp is booted by the arm when dspboot = 0. ac5 i/o/z dspboot dv dd33 the dsp boots from emifa when dspboot = 1 (and arm hpi or pci boot mode is not selected). after reset, this pin is video port data output 6 (vp_dout6). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 31
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-5. boot terminal functions (continued) signal type (1) other (2) (3) description name no. voltage adjust enable (smartreflex). this pin is multiplexed between smartreflex output control enable and the vpif. at reset, the input state is sampled to determine whether the smartreflex control outputs are enbabled or disabled. vp_dout7/ ipd 0 = smartreflex outputs disabled [default]. gp[6]/cvddadj0 and ab7 i/o/z vadjen dv dd33 gp[7]/cvddadj1 pins function as gpio. 1 = smartreflex outputs enabled. gp[6]/cvddadj0 and gp[7]/cvddadj1 pins function as smartreflex control outputs to the adjustable core power supply [1.2 v or 1.05 v]. device overview 32 submit documentation feedback
3.7.2 oscillator/pll tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-6. oscillator/pll terminal functions signal type (1) other (2) description name no. oscillator, pll dev_mxi/ crystal input dev_mxi for dev oscillator (system oscillator, typically 27 mhz). if the b15 i dev_dv dd18 dev_clkin internal oscillator is bypassed, this pin is the 1.8-v external oscillator clock input. crystal output for dev oscillator. if the internal oscillator is bypassed, dev_mxo dev_mxo a15 o dev_dv dd18 should be left as a no connect. 1.8-v power supply for dev oscillator. if the internal oscillator is bypassed, dev_dv dd18 d15 s (3) dev_dv dd18 should still be connected to the 1.8-v power supply. i/o ground for dev oscillator. if the internal oscillator is bypassed, dev_dv ss dev_dv ss e14 gnd (3) should be connected to ground v ss . 1.2-v power supply for dev oscillator. if the internal oscillator is bypassed, dev_cv dd e15 s (3) dev_cv dd should be connected to the 1.2-v power supply (cv dd ). ground for dev oscillator. connect to crystal load capacitors. do not connect to dev_v ss c15 gnd (3) board ground (v ss ). if the internal oscillator is bypassed, dev_v ss should still be connected to ground v ss . crystal input for auxiliary (aux) oscillator (24/48 mhz for usb, and uart2/1/0 and aux_mxi/ mcasp1/0). if the internal oscillator is bypassed, this pin is the 1.8-v external b17 i aux_dv dd18 aux_clkin oscillator clock input. when the peripheral is not used, aux_mxi should be left as a no connect. crystal output for aux oscillator. if the internal oscillator is bypassed, aux_mxo aux_mxo a17 o aux_dv dd18 should be left as a no connect. when the peripheral is not used, aux_mxo should be left as a no connect. 1.8-v power supply for aux oscillator. if the internal oscillator is bypassed, aux_dv dd18 should still be connected to the 1.8-v power supply. when the aux_dv dd18 d16 s (3) peripheral is not used, aux_dv dd18 should be connected to the 1.8-v power supply. i/o ground for aux oscillator. if the internal oscillator is bypassed, aux_dv ss aux_dv ss c16 gnd (3) should be connected to ground (v ss ). when the peripheral is not used, aux_dv ss should be connected to ground (v ss ). 1.2-v power supply for aux oscillator. if the internal oscillator is bypassed, aux_cv dd should be connected to the 1.2-v power supply (cv dd ). when the aux_cv dd e16 s (3) peripheral is not used, aux_cv dd should be connected to the 1.2-v power supply (cv dd ). ground for aux oscillator. connect to crystal load capacitors. do not connect to board ground (v ss ). if the internal oscillator is bypassed, aux_v ss should still be aux_v ss c17 gnd (3) connected to ground (v ss ). when the peripheral is not used, aux_v ss should be connected to ground (v ss ). pll1v dd18 b14 s (3) 1.8-v power supply for plls. pll2v dd18 b16 pll1v ss c14 gnd (3) ground for plls. pll2v ss a16 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) specifies the operating i/o supply voltage for each signal (3) for more information, see the recommended operating conditions table submit documentation feedback device overview 33
3.7.3 clock generator tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-7. clock generator terminal functions signal type (1) other (2) (3) description name no. clock generator clkout0 c13 o/z dv dd33 configurable output clock. gp[3]/ ipd this pin is multiplexed between gpio and the audio clock selector. for the audio ab3 i/o/z audio_clk0 dv dd33 clock selector, this pin is the configurable audio_clk0 output. gp[2]/ ipd this pin is multiplexed between gpio and the audio clock selector. for the audio aa4 i/o/z audio_clk1 dv dd33 clock selector, this pin is the configurable audio_clk1 output. this pin is multiplexed between gpio and the tsif clock selector. for tsif, this gp[4]/ ipd ac3 i/o/z pin is the stc_clkin which can be used as an external clock source for the tsif stc_clkin dv dd33 counters or as tsif output clock. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 34 submit documentation feedback
3.7.4 reset and jtag tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-8. reset and jtag terminal functions signal type (1) other (2) (3) description name no. reset ipu reset w6 i device reset. dv dd33 ipu por d17 i power-on reset. dv dd33 jtag ipu jtag test-port mode select input. tms d12 i dv dd33 for proper device operation, do not oppose the ipu on this pin. ? tdo d13 o/z jtag test-port data output. dv dd33 ipu tdi e13 i jtag test-port data input. dv dd33 ipu tck b12 i jtag test-port clock input. dv dd33 ? rtck c12 o/z jtag test-port return clock output. dv dd33 ipd jtag test-port reset. for ieee 1149.1 jtag compatibility, see the ieee 1149.1 trst e12 i dv dd33 jtag compatibility statement portion of this data manual. ipu emu1 b13 i/o/z emulation pin 1 dv dd33 ipu emu0 a13 i/o/z emulation pin 0 dv dd33 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 35
3.7.5 asynchronous external memory interface (emifa) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-9. asynchronous external memory interface (emifa) terminal functions signal type (1) other (2) (3) description name no. emifa boot configuration emifa cs2 space data bus width. this pin is multiplexed between emifa control and the vpif. at reset, the input state is sampled to set the emifa data bus width for the cs2 (boot) chip select region. vp_dout4/ ipd aa7 i/o/z cs2bw dv dd33 for an 8-bit-wide emifa data bus, cs2bw = 0. for a 16-bit-wide emifa data bus, cs2bw = 1. after reset, this pin is video port data output 4 (vp_dout4). dsp boot source bit. this pin is multiplexed between dsp boot and the vpif. at reset, the input state is sampled to set the dsp boot source dspboot. vp_dout6/ ipd ac5 i/o/z the dsp is booted by the arm when dspboot = 0. dspboot dv dd33 the dsp boots from emifa when dspboot=1. after reset, this pin is video port data output 6 (vp_dout6). emifa functional pins: async this pin is multiplexed between pci, hpi, and emifa. pci_cbe2/ ipu in emifa mode, this pin is chip select 2 output em_cs2 (o/z). this is the chip hds2/ c4 i/o/z dv dd33 select used for emifa boot modes. asynchronous memories (i.e., nor flash) or em_cs2 nand flash. pci_cbe3/ this pin is multiplexed between pci, hpi, and emifa. ipu hr/ w a5 i/o/z in emifa mode, this pin is chip select 3 output em_cs3 (o/z). asynchronous dv dd33 em_cs3 memories (i.e., nor flash). this pin is multiplexed between pci, ata, gpio, and emifa. pci_gnt/ ipu in emifa mode, this pin is chip select 4 output em_cs4 (o/z). asynchronous dack/ d10 i/o/z dv dd33 memories (i.e., nor flash). gp[12]/ em_cs4 this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_req/ this pin is multiplexed between pci, ata, gpio, and emifa. ipu dmarq/ b9 i/o/z in emifa mode, this pin is chip select 5 output em_cs5 (o/z). dv dd33 gp[11]/ em_cs5 this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_idsel/ ipu this pin is multiplexed between pci, ata, and emifa. hddir/ e8 i/o/z dv dd33 in emifa mode, this pin is the read/write output em_r/ w (o/z). em_r/ w pci_serr/ ipu this pin is multiplexed between pci, hpi, and emifa. hds1/ b2 i/o/z dv dd33 in emifa mode, this pin is the output enable output em_oe (o/z). em_oe pci_stop/ ipu this pin is multiplexed between pci, hpi, and emifa. hcntl0/ d5 i/o/z dv dd33 in emifa mode, this pin is the write enable output em_we (o/z). em_we pci_perr/ ipu hcs/ c3 i/o/z dv dd33 em_dqm1 these pins are multiplexed between pci, hpi, and emifa. in emifa mode, these pins are em_dqm[1:0] and act as byte enables (o/z). pci_par/ ipu has/ d4 i/o/z dv dd33 em_dqm0 pci_inta/ this pin is multiplexed between pci and emifa. ipu em_wait2/ c11 i/o/z in emifa mode, this pin is wait state extension input 2 em_wait2 (i). dv dd33 (rdy2/ bsy2) when used for emifa (nand), this pin is the ready/busy 2 input (rdy2/ bsy2). pci_rsv5/iordy/ this pin is multiplexed between pci, ata, gpio, and emifa. ipu gp[21]/ em_wait3/ d11 i/o/z in emifa mode, this pin is wait state extension input 3 em_wait3 (i). dv dd33 (rdy3/ bsy3) when used for emifa (nand), this pin is the ready/busy 3 input (rdy3/ bsy3). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 36 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-9. asynchronous external memory interface (emifa) terminal functions (continued) signal type (1) other (2) (3) description name no. pci_rsv4/ diow/ this pin is multiplexed between pci, ata, gpio, and emifa. ipu gp[20]/ em_wait4/ a11 i/o/z in emifa mode, this pin is wait state extension input 4 em_wait4 (i). dv dd33 (rdy4/ bsy4) when used for emifa (nand), this pin is the ready/busy 4 input (rdy4/ bsy4). pci_rsv3/ dior/ this pin is multiplexed between pci, ata, gpio, and emifa. ipu gp[19]/ em_wait5/ e10 i/o/z for emifa, this pin is wait state extension input 5 em_wait5 (i). dv dd33 (rdy5/ bsy5) when used for emifa (nand), this pin is the ready/busy 5 input (rdy5/ bsy5). this pin is multiplexed between pci, hpi, and emifa. for emifa, this is the bank address 0 output em_ba[0] (o/z). pci_frame/ ipu when connected to a 16-bit asynchronous memory, this pin has the same hint/ d6 i/o/z dv dd33 function as emif address pin 22 (em_a[22]). em_ba[0] when connected to an 8-bit asynchronous memory, this pin is the lowest order bit of the byte address. this pin is multiplexed between pci, hpi, and emifa. for emifa, this is the bank address 1 output em_ba[1] (o/z). pci_devsel/ ipu when connected to a 16 bit asynchronous memory this pin is the lowest order bit hcntl1/ b3 i/o/z dv dd33 of the 16-bit word address. em_ba[1] when connected to an 8-bit asynchronous memory, this pin is the second bit of the address. this pin is multiplexed between pci, ata, gpio, and emifa. pci_rsv2/intrq/ ipd b10 i/o/z in emifa mode, this pin is reserved. gp[18]/ em_rsv0 dv dd33 this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_rst/ this pin is multiplexed between pci, ata, gpio, and emifa. ipd da2/ c10 i/o/z in emifa mode, this pin is address bit 22 output em_a[22] (o/z). dv dd33 gp[13]/ em_a[22] this signal is not available when ata is enabled (i.e., emif nand flash mode). this pin is multiplexed between pci, ata, gpio, and emifa. pci_rsv0/da1/ ipd a9 i/o/z in emifa mode, this pin is address bit 21 output em_a[21] (o/z). gp[16]/ em_a[21] dv dd33 this signal is not available when ata is enabled (i.e., emif nand flash mode). this pin is multiplexed between pci ata, gpio, and emifa. pci_rsv1/da0/ ipd e9 i/o/z in emifa mode, this pin is address bit 20 output em_a[20] (o/z). gp[17]/ em_a[20] dv dd33 this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_cbe1/ this pin is multiplexed between pci, ata, gpio, and emifa. ipu ata_cs1/ c2 i/o/z in emifa mode, this pin is address bit 19 output em_a[19] (o/z). dv dd33 gp[32]/ em_a[19] this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_cbe0/ this pin is multiplexed between pci, ata, gpio, and emifa. ipu ata_cs0/ f4 i/o/z in emifa mode, this pin is address bit 18 output em_a[18] (o/z). dv dd33 gp[33]/ em_a[18] this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_irdy/ this pin is multiplexed between pci, hpi, and emifa. ipu hrdy/ a3 i/o/z in emifa mode, this pin is address bit 17 output em_a[17] (o/z). dv dd33 em_a[17]/(cle) when used for emifa (nand), this pin is command latch enable output (cle). pci_trdy/ this pin is multiplexed between pci, hpi, and emifa. ipu hhwil/ e6 i/o/z for emifa, this pin is address bit 16 output em_a[16] (o/z). dv dd33 em_a[16]/(ale) when used for emifa (nand), this pin is address latch enable output (ale). pci_ad31/ this pin is multiplexed between pci, ata, hpi, and emifa. ipd dd15/ a8 i/o/z for emifa, this pin is address bit 15 output em_a[15] (o/z). dv dd33 hd31/ em_a[15] this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_ad30/ this pin is multiplexed between pci, ata, hpi, and emifa. ipd dd14/ c9 i/o/z for emifa, this pin is address bit 14 output em_a[14] (o/z). dv dd33 hd30/ em_a[14] this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_ad29/ this pin is multiplexed between pci, ata, hpi, and emifa. ipd dd13/ b8 i/o/z for emifa, this pin is address bit 13 output em_a[13] (o/z). dv dd33 hd29/ em_a[13] this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_ad28/ this pin is multiplexed between pci, ata, hpi, and emifa. ipd dd12/ d9 i/o/z for emifa, this pin is address bit 12 output em_a[12] (o/z). dv dd33 hd28/ em_a[12] this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_ad27/ this pin is multiplexed between pci, ata, hpi, and emifa. ipd dd11/ a6 i/o/z for emifa, this pin is address bit 11 output em_a[11] (o/z). dv dd33 hd27/ em_a[11] this signal is not available when ata is enabled (i.e., emif nand flash mode). submit documentation feedback device overview 37
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-9. asynchronous external memory interface (emifa) terminal functions (continued) signal type (1) other (2) (3) description name no. pci_ad26/ this pin is multiplexed between pci, ata, hpi, and emifa. ipd dd10/ c8 i/o/z for emifa, this pin is address bit 10 output em_a[10] (o/z). dv dd33 hd26/ em_a[10] this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_ad25/ this pin is multiplexed between pci, ata, hpi, and emifa. ipd dd9/ b6 i/o/z for emifa, this pin is address bit 9 output em_a[9] (o/z). dv dd33 hd25/ em_a[9] this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_ad24/ this pin is multiplexed between pci, ata, hpi, and emifa. ipd dd8/ d8 i/o/z for emifa, this pin is address bit 8 output em_a[8] (o/z). dv dd33 hd24/ em_a[8] this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_ad23/ this pin is multiplexed between pci, ata, hpi, and emifa. ipd dd7/ b5 i/o/z for emifa, this pin is address bit 7 output em_a[7] (o/z). dv dd33 hd23/ em_a[7] this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_ad22/ this pin is multiplexed between pci, ata, hpi, and emifa. ipd dd6/ c7 i/o/z for emifa, this pin is address bit 6 output em_a[6] (o/z). dv dd33 hd22/ em_a[6] this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_ad21/ this pin is multiplexed between pci, ata, hpi, and emifa. ipd dd5/ c5 i/o/z for emifa, this pin is address bit 5 output em_a[5] (o/z). dv dd33 hd21/ em_a[5] this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_ad20/ this pin is multiplexed between pci, ata, hpi, and emifa. ipd dd4/ d7 i/o/z for emifa, this pin is address bit 4 output em_a[4] (o/z). dv dd33 hd20/ em_a[4] this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_ad19/ this pin is multiplexed between pci, ata, hpi, and emifa. ipd dd3/ a4 i/o/z for emifa, this pin is address bit 3 output em_a[3] (o/z). dv dd33 hd19/ em_a[3] this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_ad18/ this pin is multiplexed between pci, ata, hpi, and emifa. ipd dd2/ e7 i/o/z for emifa, this pin is address bit 2 output em_a[2] (o/z). dv dd33 hd18/ em_a[2] this signal is not available when ata is enabled (i.e., emif nand flash mode). pci_ad17/ this pin is multiplexed between pci, ata, hpi, and emifa. ipd dd1/ b4 i/o/z for emifa, this pin is address bit 1 output em_a[1] (o/z). dv dd33 hd17/ em_a[1] this signal is not available when ata is enabled (i.e., emif nand flash mode). this pin is multiplexed between pci, ata, hpi, and emifa. for emifa, this pin is address bit 0 output em_a[0] (o/z), which is the least pci_ad16/ ipd significant bit on a 32-bit word address. dd0/ c6 i/o/z dv dd33 when connected to a 16-bit asynchronous memory, this pin is the second bit of hd16/ em_a[0] the address. for an 8-bit asynchronous memory, this pin is the third bit of the address. 38 device overview submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-9. asynchronous external memory interface (emifa) terminal functions (continued) signal type (1) other (2) (3) description name no. pci_ad15/ ipd e5 i/o/z hd15/ em_d15 dv dd33 pci_ad14/ ipd c1 i/o/z hd14 / em_d14 dv dd33 pci_ad13/ ipd e4 i/o/z hd13/ em_d13 dv dd33 pci_ad12/ ipd d3 i/o/z hd12/ em_d12 dv dd33 pci_ad11/ ipd e3 i/o/z hd11/ em_d11 dv dd33 pci_ad10/ ipd d2 i/o/z hd10/ em_d10 dv dd33 pci_ad9/ ipd f5 i/o/z hd9/ em_d9 dv dd33 these pins are multiplexed between pci, hpi, and emifa. pci_ad8/ ipd d1 i/o/z for emifa mode, these pins are the 16-bit bidirectional data bus (em_d[15:0]) hd8/ em_d8 dv dd33 [i/o/z]. pci_ad7/ ipd when emifa is configured for an 8-bit asynchronous memory, only em_d[7:0] e2 i/o/z hd7/ em_d7 dv dd33 pins are used. pci_ad6/ ipd f3 i/o/z hd6/ em_d6 dv dd33 pci_ad5/ ipd e1 i/o/z hd5/ em_d5 dv dd33 pci_ad4/ ipd g5 i/o/z hd4/ em_d4 dv dd33 pci_ad3/ ipd f2 i/o/z hd3/ em_d3 dv dd33 pci_ad2/ ipd g4 i/o/z hd2/ em_d2 dv dd33 pci_ad1/ ipd f1 i/o/z hd1/ em_d1 dv dd33 pci_ad0/ ipd g3 i/o/z hd0/ em_d0 dv dd33 emifa functional pins: nand pci_irdy/ this pin is multiplexed between pci, hpi, and emifa. ipu hrdy/ a3 i/o/z in emifa mode, this pin is address bit 17 output em_a[17] (o/z). dv dd33 em_a[17]/(cle) when used for emifa (nand), this pin is command latch enable output (cle). pci_trdy/ this pin is multiplexed between pci, hpi, and emifa. ipu hhwil/ e6 i/o/z for emifa, this pin is address bit 16 output em_a[16] (o/z). dv dd33 em_a[16]/(ale) when used for emifa (nand), this pin is address latch enable output (ale). pci_inta/ this pin is multiplexed between pci and emifa. ipu em_wait2/ c11 i/o/z in emifa mode, this pin is wait state extension input 2 em_wait2 (i). dv dd33 (rdy2/ bsy2) when used for emifa (nand), this pin is the ready/busy 2 input (rdy2/ bsy2). iordy/ this pin is multiplexed between ata, gpio, and emifa. ipu gp[21]/ em_wait3/ d11 i/o/z in emifa mode, this pin is wait state extension input 3 em_wait3 (i). dv dd33 (rdy3/ bsy3) when used for emifa (nand), this pin is the ready/busy 3 input (rdy3/ bsy3). diow/ this pin is multiplexed between ata, gpio, and emifa. ipu gp[20]/ em_wait4/ a11 i/o/z in emifa mode, this pin is wait state extension input 4 em_wait4 (i). dv dd33 (rdy4/ bsy4) when used for emifa (nand), this pin is the ready/busy 4 input (rdy4/ bsy4). dior/ this pin is multiplexed between ata, gpio, and emifa. ipu gp[19]/ em_wait5/ e10 i/o/z for emifa, this pin is wait state extension input 5 em_wait5 (i). dv dd33 (rdy5/ bsy5) when used for emifa (nand), this pin is the ready/busy 5 input (rdy5/ bsy5). pci_serr/ ipu this pin is multiplexed between pci, hpi, and emifa. hds1/ b2 i/o/z dv dd33 in emifa mode, this pin is the output enable output em_oe (o/z). em_oe submit documentation feedback device overview 39
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-9. asynchronous external memory interface (emifa) terminal functions (continued) signal type (1) other (2) (3) description name no. pci_stop/ ipu this pin is multiplexed between pci, hpi, and emifa. hcntl0/ d5 i/o/z dv dd33 in emifa mode, this pin is the write enable output em_we (o/z). em_we this pin is multiplexed between pci, hpi, and emifa. pci_cbe2/ ipu in emifa mode, this pin is chip select 2 output em_cs2 (o/z). this is the chip hds2/ c4 i/o/z dv dd33 select used for emifa boot modes. asynchronous memories (i.e., nor flash) or em_cs2 nand flash. pci_cbe3/ this pin is multiplexed between pci, hpi, and emifa. ipu hr/ w a5 i/o/z in emifa mode, this pin is chip select 3 output em_cs3 (o/z). asynchronous dv dd33 em_cs3 memories (i.e., nor flash). pci_ad15/ ipd e5 i/o/z hd15/ em_d15 dv dd33 pci_ad14/ ipd c1 i/o/z hd14 / em_d14 dv dd33 pci_ad13/ ipd e4 i/o/z hd13/ em_d13 dv dd33 pci_ad12/ ipd d3 i/o/z hd12/ em_d12 dv dd33 pci_ad11/ ipd e3 i/o/z hd11/ em_d11 dv dd33 pci_ad10/ ipd d2 i/o/z hd10/ em_d10 dv dd33 pci_ad9/ ipd f5 i/o/z hd9/ em_d9 dv dd33 these pins are multiplexed between pci, hpi, and emifa. pci_ad8/ ipd d1 i/o/z for emifa mode, these pins are the 16-bit bidirectional data bus (em_d[15:0]) hd8/ em_d8 dv dd33 [i/o/z]. pci_ad7/ ipd when emifa is configured for an 8-bit asynchronous memory, only em_d[7:0] e2 i/o/z hd7/ em_d7 dv dd33 pins are used. pci_ad6/ ipd f3 i/o/z hd6/ em_d6 dv dd33 pci_ad5/ ipd e1 i/o/z hd5/ em_d5 dv dd33 pci_ad4/ ipd g5 i/o/z hd4/ em_d4 dv dd33 pci_ad3/ ipd f2 i/o/z hd3/ em_d3 dv dd33 pci_ad2/ ipd g4 i/o/z hd2/ em_d2 dv dd33 pci_ad1/ ipd f1 i/o/z hd1/ em_d1 dv dd33 pci_ad0/ ipd g3 i/o/z hd0/ em_d0 dv dd33 device overview 40 submit documentation feedback
3.7.6 ddr2 memory controller tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-10. ddr2 memory controller terminal functions signal type (1) other (2) (3) description name no. ddr2 memory controller ddr_clk m23 o/z dv ddr2 ddr2 clock ddr_clk l23 o/z dv ddr2 ddr2 differential clock ddr_cke m20 o/z dv ddr2 ddr2 clock enable ddr_cs j20 o/z dv ddr2 ddr2 active low chip select ddr_we l20 o/z dv ddr2 ddr2 active low write enable ddr_ras k19 o/z dv ddr2 ddr2 row access signal output ddr_cas l21 o/z dv ddr2 ddr2 column access signal output ddr_dqm[3] v20 o/z dv ddr2 ddr2 data mask outputs ddr_dqm[3]: for upper byte data bus ddr_d[31:24] ddr_dqm[2] y23 o/z dv ddr2 ddr_dqm[2]: for ddr_d[23:16] ddr_dqm[1] f22 o/z dv ddr2 ddr_dqm[1]: for ddr_d[15:8] ddr_dqm[0]: for lower byte ddr_d[7:0] ddr_dqm[0] f20 o/z dv ddr2 ddr_dqs[3] u20 i/o/z dv ddr2 data strobe input/outputs for each byte of the 32-bit data bus. they are outputs to the ddr2 memory when writing and inputs when reading. they are used to ddr_dqs[2] v22 i/o/z dv ddr2 synchronize the data transfers. ddr_dqs[1] d22 i/o/z dv ddr2 ddr_dqs[3] : for upper byte ddr_d[31:24] ddr_dqs[2]: for ddr_d[23:16] ddr_dqs[1]: for ddr_d[15:8] ddr_dqs[0] d21 i/o/z dv ddr2 ddr_dqs[0]: for bottom byte ddr_d[7:0] ddr_dqs[3] v21 i/o/z dv ddr2 complimentary data strobe input/outputs for each byte of the 32-bit data bus. they are outputs to the ddr2 memory when writing and inputs when reading. they are ddr_dqs[2] w23 i/o/z dv ddr2 used to synchronize the data transfers. ddr_dqs[1] d23 i/o/z dv ddr2 ddr_dqs[3] : for upper byte ddr_d[31:24] ddr_dqs[2]: for ddr_d[23:16] ddr_dqs[1]: for ddr_d[15:8] ddr_dqs[0] e20 i/o/z dv ddr2 ddr_dqs[0]: for bottom byte ddr_d[7:0] ddr_odt0 k20 o/z dv ddr2 ddr2 on-die termination control ddr_ba[2] p19 ddr_ba[1] m21 o/z dv ddr2 bank address outputs (ba[2:0]). ddr_ba[0] n19 ddr_a[14] n23 ddr_a[13] h21 ddr_a[12] p20 ddr_a[11] k23 ddr_a[10] t23 ddr_a[9] n22 ddr_a[8] j23 ddr_a[7] n20 o/z dv ddr2 ddr2 address bus ddr_a[6] m22 ddr_a[5] n21 ddr_a[4] j22 ddr_a[3] r22 ddr_a[2] l22 ddr_a[1] r23 ddr_a[0] h23 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) specifies the operating i/o supply voltage for each signal (3) for more information, see the recommended operating conditions table submit documentation feedback device overview 41
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-10. ddr2 memory controller terminal functions (continued) signal type (1) other (2) (3) description name no. ddr_d[31] y20 ddr_d[30] w20 ddr_d[29] y21 ddr_d[28] aa21 ddr_d[27] u21 ddr_d[26] t21 ddr_d[25] r20 ddr_d[24] t20 ddr_d[23] ab22 ddr_d[22] y22 ddr_d[21] aa22 ddr_d[20] aa23 ddr_d[19] v23 ddr_d[18] u23 ddr_d[17] t22 ddr_d[16] u22 i/o/z dv ddr2 ddr2 data bus can be configured as 32 bits wide or 16 bits wide. ddr_d[15] h22 ddr_d[14] g23 ddr_d[13] g22 ddr_d[12] f23 ddr_d[11] e23 ddr_d[10] c22 ddr_d[9] b22 ddr_d[8] c23 ddr_d[7] h20 ddr_d[6] g21 ddr_d[5] f21 ddr_d[4] g20 ddr_d[3] b21 ddr_d[2] c20 ddr_d[1] d20 ddr_d[0] c21 ddr_dqgate0 j19 o/z dv ddr2 ddr2 strobe gate signal for lower-half data bus ddr_dqgate1 j21 i dv ddr2 ddr2 strobe gate signal return for lower-half data bus ddr_dqgate2 r19 o/z dv ddr2 ddr2 strobe gate signal for upper-half data bus ddr_dqgate3 r21 i dv ddr2 ddr2 strobe gate signal return for upper-half data bus ddr_vref p23 s (3) reference voltage input for the sstl_18 io buffers. impedance control for ddr2 outputs. this must be connected via a 50- w ( 0.5% ddr_zp l19 o (3) tolerance) resistor to v ss . impedance control for ddr2 outputs. this must be connected via a 50- w ( 0.5% ddr_zn m19 o (3) tolerance) resistor to dv ddr2 . device overview 42 submit documentation feedback
3.7.7 peripheral component interconnect (pci) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-11. peripheral component interconnect (pci) terminal functions signal type (1) other (2) (3) description name no. pci note: when pci boot mode is not used, for proper device operation out of reset pcien must be "0". the pci pin functions are enabled when pcien = 1 (pci mode). this can be done via an external pu on the pcien pin (ac6) or by setting the pcien bit (bit 2) in the pinmux0 register to a "1" after device reset. for more details on the pcien pin, see table 3-5 , boot terminal functions. in pci mode (pcien = 1), the internal pullups/pulldowns (ipus/ipds) are disabled on all pci pins and it is recommended to have external pullup resistors on the pci_rsv[5:0] pins. for more detailed information on external pullup/pulldown resistors, see section 4.8.1 , pullup/pulldown resistors. also in pci mode (pcien = 1), the internal pulldowns (ipds) are disabled on the gp[5:7] pins. it is recommended to have external pullup resistors on the gp[5] pin when pcien = 1 and on gp[6:7] pins when pcien = 1 and vadjen = 0. [ipu] this pin is multiplexed between pci and gpio. pci_clk/gp[10] a10 i/o/z dv dd33 in pci mode, this pin is the pci clock input pci_clk (i). pci_rst/da2/ [ipd] this pin is multiplexed between the pci, ata, gpio, and emifa. c10 i/o/z gp[13]/em_a[22] dv dd33 in pci mode, this pin is pci reset pci_rst (i). this pin is multiplexed between pci, ata, and emifa. pci_idsel/ [ipu] e8 i/o/z in pci mode, this pin is the pci initialization device select, pci_idsel hddir/em_r/ w dv dd33 (i). pci_devsel/ [ipu] this pin is multiplexed between pci, hpi, and emifa. b3 i/o/z hcntl1/em_ba[1] dv dd33 in pci mode, this pin is the pci device select, pci_devsel (i/o/z). pci_frame/ [ipu] this pin is multiplexed between pci, hpi, and emifa. d6 i/o/z hint/em_ba[0] dv dd33 in pci mode, this pin is the pci cycle frame, pci_frame (i/o/z). pci_irdy/ hrdy/ [ipu] this pin is multiplexed between pci, hpi, and emifa. a3 i/o/z em_a[17]/(cle) dv dd33 in pci mode, this pin is the pci initiator ready, pci_irdy (i/o/z). pci_ trdy/hhwil/ ipu this pin is multiplexed between pci, hpi, and emifa. e6 i/o/z em_a[16]/(ale) dv dd33 in pci mode, this pin is the pci target ready, pci_ trdy (i/o/z). pci_stop/ [ipu] this pin is multiplexed between pci, hpi, and emifa. d5 i/o/z hcntl0/ em_we dv dd33 in pci mode, this pin is the pci stop, pci_stop (i/o/z). pci_serr/ [ipu] this pin is multiplexed between pci, hpi, and emifa. b2 i/o/z hds1/ em_oe dv dd33 in pci mode, this pin is the pci system error, pci_serr (i/o/z). pci_perr/ [ipu] this pin is multiplexed between pci, hpi, and emifa. c3 i/o/z hcs/ em_dqm1 dv dd33 in pci mode, this pin is the pci parity error, pci_perr (i/o/z). pci_par/ [ipu] this pin is multiplexed between pci, hpi, and emifa. d4 i/o/z has/ em_dqm0 dv dd33 in pci mode, this pin is the pci parity, pci_par (i/o/z). pci_inta/ [ipu] this pin is multiplexed between the pci and emifa. em_wait2/ c11 i/o/z dv dd33 in pci mode, this pin is the pci interrupt a, pci_inta (o/z). (rdy2/ bsy2) pci_req/ [ipu] this pin is multiplexed between the pci, ata, gpio, and emifa. dmarq/ b9 i/o/z dv dd33 in pci mode, this pin is the pci bus request, pci_req (o/z). gp[11]/ em_cs5 pci_gnt/ [ipu] this pin is multiplexed between the pci, ata, gpio, and emifa. dmack/ d10 i/o/z dv dd33 in pci mode, this pin is pci bus grant, pci_gnt (i). gp[12]/ em_cs4 this pin is multiplexed between pci, hpi, and emifa. pci_cbe3/ [ipu] a5 i/o/z in pci mode, this pin is the pci command/byte enable 3, pci_cbe3 hr/ w/ em_cs3 dv dd33 (i/o/z). this pin is multiplexed between pci, hpi, and emifa. pci_cbe2/ [ipu] c4 i/o/z in pci mode, this pin is the pci command/byte enable 2, pci_cbe2 hds2/ em_cs2 dv dd33 (i/o/z). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 43
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-11. peripheral component interconnect (pci) terminal functions (continued) signal type (1) other (2) (3) description name no. pci_cbe1/ this pin is multiplexed between pci, ata, gpio, and emifa. [ipu] ata_cs1/ c2 i/o/z in pci mode, this pin is the pci command/byte enable 1 pci_cbe1 dv dd33 gp[32]/em_a[19] (i/o/z). pci_cbe0/ this pin is multiplexed between pci, ata, gpio, and emifa. [ipu] ata_cs0/ f4 i/o/z in pci mode, this pin is the pci command/byte enable 0 pci_cbe0 dv dd33 gp[33]/em_a[18] (i/o/z). 44 device overview submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-11. peripheral component interconnect (pci) terminal functions (continued) signal type (1) other (2) (3) description name no. pci_ad31/dd15/ [ipd] a8 i/o/z hd31/em_a[15] dv dd33 pci_ad30/dd14/ [ipd] c9 i/o/z hd30/em_a[14] dv dd33 pci_ad29/dd13/ [ipd] b8 i/o/z hd29/em_a[13] dv dd33 pci_ad28/dd12/ [ipd] d9 i/o/z hd28/em_a[12] dv dd33 pci_ad27/dd11/ [ipd] a6 i/o/z hd27/em_a[11] dv dd33 pci_ad26/dd10/ [ipd] c8 i/o/z hd26/em_a[10] dv dd33 pci_ad25/dd9/ [ipd] b6 i/o/z hd25/em_a[9] dv dd33 pci_ad24/dd8/ [ipd] d8 i/o/z these pins are multiplexed between pci, ata, hpi, and emifa. hd24/em_a[8] dv dd33 in pci mode, these pins are the pci address/data bus, pci_ad[31:16] pci_ad23/dd7/ [ipd] (i/o/z). b5 i/o/z hd23/em_a[7] dv dd33 pci_ad22/dd6/ [ipd] c7 i/o/z hd22/em_a[6] dv dd33 pci_ad21/dd5/ [ipd] c5 i/o/z hd21/em_a[5] dv dd33 pci_ad20/dd4/ [ipd] d7 i/o/z hd20/em_a[4] dv dd33 pci_ad19/dd3/ [ipd] a4 i/o/z hd19/em_a[3] dv dd33 pci_ad18/dd2/ [ipu] e7 i/o/z hd18/em_a[2] dv dd33 pci_ad17/dd1/ [ipd] b4 i/o/z hd17/em_a[1] dv dd33 pci_ad16/dd0/ [ipd] c6 i/o/z hd16/em_a[0] dv dd33 pci_ad15/ [ipd] e5 i/o/z hd15/em_d15 dv dd33 pci_ad14/ [ipd] c1 i/o/z hd14/em_d14 dv dd33 pci_ad13/ [ipd] e4 i/o/z hd13/em_d13 dv dd33 pci_ad12/ [ipd] d3 i/o/z hd12/em_d12 dv dd33 these pins are multiplexed between pci, hpi, and emifa. for pci, these pins are pci data/address bus, pci_ad [15:0] (i/o/z). pci_ad11/ [ipd] e3 i/o/z hd11/em_d11 dv dd33 pci_ad10/ [ipd] d2 i/o/z hd10/em_d10 dv dd33 pci_ad9/ [ipu] f5 i/o/z hd9/em_d9 dv dd33 pci_ad8/ [ipd] d1 i/o/z hd8/em_d8 dv dd33 submit documentation feedback device overview 45
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-11. peripheral component interconnect (pci) terminal functions (continued) signal type (1) other (2) (3) description name no. pci_ad7/ [ipd] e2 i/o/z hd7/em_d7 dv dd33 pci_ad6/ [ipd] f3 i/o/z hd6/em_d6 dv dd33 pci_ad5/ [ipd] e1 i/o/z hd5/em_d5 dv dd33 pci_ad4/ [ipd] g5 i/o/z hd4/em_d4 dv dd33 these pins are multiplexed between pci, hpi, and emifa. for pci, these pins are pci data/address bus [15:0] (i/o/z) pci_ad3/ [ipd] f2 i/o/z hd3/em_d3 dv dd33 pci_ad2/ [ipd] g4 i/o/z hd2/em_d2 dv dd33 pci_ad1/ [ipd] f1 i/o/z hd1/em_d1 dv dd33 pci_ad0/ [ipd] g3 i/o/z hd0/em_d0 dv dd33 pci_rsv0/da1/ [ipd] a9 i/o/z pci reserved for future enhancements (i) (1) gp[16]/em_a[21] dv dd33 pci_rsv1/da0/ [ipd] e9 i/o/z pci reserved for future enhancements (o/z) (1) gp[17]/em_a[20] dv dd33 pci_rsv2/intrq/ [ipd] b10 i/o/z pci reserved for future enhancements (i) (1) gp[18]/em_rsv0 dv dd33 pci_rsv3/ dior/ [ipu] gp[19]/ e10 i/o/z pci reserved for future enhancements (o/z) (1) dv dd33 em_wait5 pci_rsv4/ diow/ [ipu] gp[20]/ a11 i/o/z pci reserved for future enhancements (i/o/z) (1) dv dd33 em_wait4 pci_rsv5/iordy/ [ipu] gp[21]/ d11 i/o/z pci reserved for future enhancements (i/o/z) (1) dv dd33 em_wait3 (1) in pci mode (pcien = 1), it is recommended to have an external pullup resistor on this pin. device overview 46 submit documentation feedback
3.7.8 emac [g]mii and mdio tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-12. emac [g]mii and mdio terminal functions signal type (1) other (2) (3) description name no. emac [g]mii ipd rftclk h1 i gigabit (gmii) reference transmit clock (125 mhz) dv dd33 - gmtclk p2 o/z gmii source asynchronous transmit clock dv dd33 ipd mtclk r1 i [g]mii transmit clock input dv dd33 mtxd7 p1 mtxd6 n4 mtxd5 n3 mtxd4 n2 - [g]mii transmit data [7:0]. for 1000 gmii operation, mtxd[7:0] are used. for 10/100 o/z dv dd33 mii operation, only mtxd[3:0] are used. mtxd3 n1 mtxd2 m4 mtxd1 m1 mtxd0 l1 - mtxen l2 o/z [g]mii transmit data enable output dv dd33 ipd mcol l4 i [g]mii collision detect (sense) input dv dd33 ipd mcrs l3 i [g]mii carrier sense input dv dd33 ipu mrclk k1 i [g]mii receive clock dv dd33 mrxd7 k2 mrxd6 k3 mrxd5 k4 mrxd4 j1 ipu [g]mii receive data [7:0]. for 1000 gmii operation, mrxd[7:0] are used. for 10/100 i dv dd33 mii operation, only mrxd[3:0] are used. mrxd3 j2 mrxd2 j3 mrxd1 h2 mrxd0 g2 ipu mrxdv j4 i [g]mii receive data valid input dv dd33 ipu mrxer h3 i [g]mii receive data error input dv dd33 mdio ipu mdclk g1 o/z management data serial clock output dv dd33 ipu mdio h4 i/o/z management data io dv dd33 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 47
3.7.9 vlynq tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-13. vlynq terminal functions signal type (1) other (2) (3) description name no. vlynq ipu vlynq_clock u1 i/o/z vlynq serial clock dv dd33 ipu vlynq_scrun u2 i/o/z vlynq serial clock run request dv dd33 vlynq_txd3 t3 vlynq_txd2 t2 ? o/z vlynq transmit bus [3:0] dv dd33 vlynq_txd1 t1 vlynq_txd0 r4 vlynq_rxd3 r3 vlynq_rxd2 r2 ipd i vlynq receive bus [3:0] dv dd33 vlynq_rxd1 p3 vlynq_rxd0 p4 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 48 submit documentation feedback
3.7.10 host-port interface (hpi) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-14. hpi terminal functions signal type (1) other (2) (3) description name no. host-port interface (hpi) hpi is enabled by the pinmux0.hpien =1 ( and pcien = 0 and ataen dependent for 16-/32-bit modes). for more detailed information on the hpi pin muxing, see section 4.7.3.1 , pci, hpi, emifa, and ata pin muxing. pci_perr/ ipu this pin is multiplexed between pci, hpi, and emifa. hcs/ c3 i/o/z dv dd33 in hpi mode, this pin is the hpi active-low chip select input, hcs (i). em_dqm1 pci_stop/ ipu this pin is multiplexed between pci, hpi, and emifa. hcntl0/ d5 i/o/z dv dd33 in hpi mode, this pin is the hpi control input 0, hcntl0 (i) em_we pci_devsel/ ipu this pin is multiplexed between pci, hpi, and emifa. hcntl1/ b3 i/o/z dv dd33 in hpi mode, this pin is the hpi control input 1, hcntl1 (i). em_ba[1] this pin is multiplexed between pci, hpi, and emifa. pci_par/ has/ ipu in hpi mode, this pin is the hpi address strobe, has (i). d4 i/o/z em_dqm0 dv dd33 note: the dm6467 hpi does not support the has feature. for proper hpi operation if the pin is routed out, it must be pulled up via an external resistor. pci_serr/ ipu this pin is multiplexed between pci, hpi, and emifa. b2 i/o/z hds1/ em_oe dv dd33 in hpi mode, this pin is the hpi data strobe input 1, hds1 (i). pci_cbe2/ ipu this pin is multiplexed between pci, hpi, and emifa. c4 i/o/z hds2/ em_cs2 dv dd33 in hpi mode, this pin is the hpi data strobe input 2, hds2 (i). pci_cbe3/ ipu this pin is multiplexed between pci, hpi, and emifa. a5 i/o/z hr/ w/ em_cs3 dv dd33 in hpi mode, this pin is the hpi host read/write select input, hr/ w (i). pci_trdy/ ipu this pin is multiplexed between pci, hpi, and emifa. hhwil/ e6 i/o/z dv dd33 in hpi mode, this pin is the hpi half-word identification input control, hhwil (i). em_a[16]/(ale) pci_ad31/ dd15/ a8 hd31/em_a[15] pci_ad30/ dd14/ c9 hd30/em_a[14] pci_ad29/ dd13/ b8 hd29/em_a[13] pci_ad28/ dd12/ d9 these pins are multiplexed between pci, ata, hpi, and emifa. hd28/em_a[12] ipd i/o/z in hpi-32 mode, these pins are the hpi upper data bus, hd[31:16] (i/o/z). dv dd33 pci_ad27/ in hpi-16 mode, the hd[31:16] pins are not used by the hpi . dd11/ a6 hd27/em_a[11] pci_ad26/ dd10/ c8 hd26/ em_a[10] pci_ad25/ dd9/ b6 hd25/em_a[9] pci_ad24/ dd8/ d8 hd24/em_a[8] (1) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (2) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 49
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-14. hpi terminal functions (continued) signal type (1) other (2) (3) description name no. pci_ad23/ dd7/ b5 hd23/em_a[7] pci_ad22/ dd6/ c7 hd22/em_a[6] pci_ad21/ dd5/ c5 hd21/em_a[5] pci_ad20/ dd4/ d7 these pins are multiplexed between pci, ata, hpi, and emifa. hd20/em_a[4] ipd i/o/z in hpi-32 mode, these pins are the hpi upper data bus, hd[31:16] (i/o/z). dv dd33 pci_ad19/ in hpi-16 mode, the hd[31:16] pins are not used by the hpi . dd3/ a4 hd19/em_a[3] pci_ad18/ dd2/ e7 hd18/em_a[2] pci_ad17/ dd1/ b4 hd17/em_a[1] pci_ad16/ dd0/ c6 hd16/em_a[0] pci_ad15/ e5 hd15/em_d15 pci_ad14/ c1 hd14/em_d14 pci_ad13/ e4 hd13/em_d13 pci_ad12/ d3 these pins are multiplexed between pci, hpi, and emifa. hd12/em_d12 ipd i/o/z in hpi-16 mode, these pins are the hpi data bus, hd[15:0] (i/o/z). dv dd33 pci_ad11/ in hpi-32 mode, these pins are the hpi lower data bus, hd[15:0] (i/o/z). e3 hd11/em_d11 pci_ad10/ d2 hd10/em_d10 pci_ad9/ f5 hd9/em_d9 pci_ad8/ d1 hd8/em_d8 pci_ad7/ e2 hd7/em_d7 pci_ad6/ f3 hd6/em_d6 pci_ad5/ e1 hd5/em_d5 pci_ad4/ g5 these pins are multiplexed between pci, hpi, and emifa. hd4/em_d4 ipd i/o/z in hpi-16 mode, these pins are the hpi data bus, hd[15:0] (i/o/z). dv dd33 pci_ad3/ in hpi-32 mode, these pins are the hpi lower data bus, hd[15:0] (i/o/z). f2 hd3/em_d3 pci_ad2/ g4 hd2/em_d2 pci_ad1/ f1 hd1/em_d1 pci_ad0/ g3 hd0/em_d0 device overview 50 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-14. hpi terminal functions (continued) signal type (1) other (2) (3) description name no. pci_irdy/ ipu this pin is multiplexed between pci, hpi, and emifa. hrdy/ a3 i/o/z dv dd33 in hpi mode, this pin is the hpi host ready output from dsp to host, hrdy (o/z). em_a[17]/(cle) pci_frame/ ipu this pin is multiplexed between pci, hpi, and emifa. d6 i/o/z hint/em_ba[0] dv dd33 in hpi mode, this pin is the hpi host interrupt output, hint (o/z). submit documentation feedback device overview 51
3.7.11 usb tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-15. usb terminal functions signal type (1) other (2) (3) (4) description name no. usb 2.0 usb_dp a19 a i/o usb bidirectional data differential signal pair [positive/negative]. when the usb peripheral is not used, the usb_dp signal should be pulled up usb_dn a20 a i/o (high) and the usb_dn signal should be pulled down (low) via a 10-k w resistor. usb current reference output. when the usb peripheral is used, this pin must be connected via a 10-k w 1% resistor to usb_v ssref . usb_r1 d18 a i/o (4) when the usb peripheral is not used, this pin must be connected via a 10-k w resistor to usb_v ssref . this pin is multiplexed between usb and gpio. usb_drvvbus/ ipd when this pin is used as usb_drvvbus (pinmux0.vbusdis = 0), and the usb b18 i/o/z gp[22] dv dd33 controller is operating as a host (usbctl.usbid = 0 and session is in progress), this signal is used by the usb controler to enable the external vbus charge pump. ground for reference current. this pin must be connected via a 10-k w 1% resistor to usb_r1. usb_v ssref c18 gnd (4) when the usb peripheral is not used, the usb_v ssref signal should be connected to v ss . analog 3.3 v power supply for usb phy. usb_v dda3p3 f18 s (4) when the usb peripheral is not used, the usb_v dda3p3 signal should be connected to dv dd33 . 1.8-v i/o power supply for usb phy. usb_v dd1p8 e18 s (4) when the usb peripheral is not used, the usb_v dd1p8 signal should be connected to 1.8-v power supply. core power supply ldo output for usb phy. this pin must be connected via a 1- m f capacitor to v ss . usb_v dda1p2ldo e17 s (4) when the usb peripheral is not used, the usb_v dda1p2ldo signal should still be connected via a 1- m f capacitor to v ss . (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal (4) for more information, see the recommended operating conditions table device overview 52 submit documentation feedback
3.7.12 video-port interface (vpif) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-16. video-port interface (vpif) terminal functions signal type (1) other (2) (3) description name no. video-port interface (vpif) ? capture ipd vp_clkin0 ac13 i vpif capture channel 0 input clock (i). dv dd33 ipd vp_clkin1 ab18 i vpif capture channel 1 input clock (i). dv dd33 this pin is multiplexed between the vpif and tsif0. vp_din15_vp_vsync/ ipd ac18 i when used for the vpif, this pin is capture data bit 15 or the vertical sync ts0_din7 dv dd33 input, vp_din15_vsync (i). this pin is multiplexed between the vpif and tsif0. vp_din14_vp_hsync/ ipd aa17 i when used for the vpif, this pin is capture data bit 14 or the horizontal sync ts0_din6 dv dd33 input, vp_din14_hsync (i). this pin is multiplexed between the vpif and tsif0. vp_din13_field/ ipd ab17 i when used for the vpif, this pin is capture data bit 13 or the field indicator ts0_din5 dv dd33 input, vp_din13_field (i). vp_din12/ ac17 ts0_din4 vp_din11/ y16 ts0_din3 vp_din10/ ipd these pins are multiplexed between the vpif and tsif0. aa16 i ts0_din2 dv dd33 when used for the vpif, these pins are capture data bits, vp_din[12:8] (i). vp_din9/ ab16 ts0_din1 vp_din8/ ac16 ts0_din0 vp_din7/ ts0_dout7/ y14 ts1_din vp_din6/ ts0_dout6/ aa14 ts1_pstin ipd these pins are multiplexed between the vpif, tsif0, and tsif1. i/o/z dv dd33 when used for the vpif, these pins are capture data bits, vp_din[7:4] (i). vp_din5/ ts0_dout5/ ab14 ts1_en_waito vp_din4/ ts0_dout4/ ac14 ts1_waito vp_din3/ y15 ts0_dout3 vp_din2/ aa15 ts0_dout2 ipd these pins are multiplexed between the vpif and tsif0. i/o/z dv dd33 when used for the vpif, these pins are capture data bits, vp_din[3:0] (i). vp_din1/ ab15 ts0_dout1 vp_din0/ ac15 ts0_dout0 video-port interface (vpif) ? display ipd vp_clkin2 y10 i vpif display channel 2 source input clock (i). dv dd33 this pin is multiplexed between the vpif and tsif1. vp_clkin3/ ipd ac9 i/o/z when used for vpif, this pin is display channel 3 source clock, vp_clkin3 ts1_clko dv dd33 (i). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 53
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-16. video-port interface (vpif) terminal functions (continued) signal type (1) other (2) (3) description name no. - vp_clko2 aa9 o/z vpif display channel 2 output clock (o/z). dv dd33 this pin is multiplexed between the vpif and tsif0. vp_clko3/ - ac10 o/z when used for vpif, this pin is the display channel 3 output clock, ts0_clko dv dd33 vp_clko3 (o/z). vp_dout15/ ab8 i/o/z ts1_din vp_dout14/ ac7 i/o/z ts1_pstin vp_dout13/ y9 i/o/z ts1_en_waito vp_dout12/ aa8 i/o/z these pins are multiplexed between the vpif and tsif1. ts1_waito ipd when used for the vpif, these pins are display data bits, vp_dout[15:8] dv dd33 vp_dout11/ (o/z). ab10 o/z ts1_dout vp_dout10/ aa10 o/z ts1_psto vp_dout9/ ac8 o/z ts1_enao vp_dout8/ ab9 o/z ts1_waitin vp_dout7/ ab7 vadjen vp_dout6/ ac5 dspboot vp_dout5/ ac6 pcien vp_dout4/ aa7 these pins are multiplexed between the vpif and boot configuration. cs2bw ipd i/o/z after reset, these pins are used by the vpif as display data bits, dv dd33 vp_dout3/ vp_dout[7:0] (o/z). ab6 btmode3 vp_dout2/ y8 btmode2 vp_dout1/ ac4 btmode1 vp_dout0/ ab5 btmode0 device overview 54 submit documentation feedback
3.7.13 transport stream interface 0 (tsif0) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-17. transport stream interface 0 (tsif0) terminal functions signal type (1) other (2) (3) description name no. tsif0 parallel input (pinmux0.ptsimux = 10) ipd ts0_clkin ac19 i tsif0 receive clock input (i). dv dd33 this pin is multiplexed between uart1, tsif0, and gpio. ucts1/usd1/ ipu when tsif0 input is enabled (pinmux0.ptsimux = 1x), in synchronous ts0_en_waito/ y17 i/o/z dv dd33 mode, this pin is the data enable indicator (i) or in asynchronous mode, this gp[26] pin is the wait output (o/z), ts0_en_waito. this pin is multiplexed between uart1, tsif0, and gpio. urts1/uirtx1/ ipu when tsif0 input is enabled (pinmux0.ptsimux = 1x), in asynchronous aa18 i/o/z ts0_waito/gp[25] dv dd33 mode, this pin is the wait output, ts0_waito (o/z). this tsif pin function is not used in synchronous mode. this pin is multiplexed between uart2, tsif0, and gpio. urts2/uirtx2/ ipu ac20 i/o/z when tsif0 input is enabled (pinmux0.ptsimux = 1x), this pin is the ts0_pstin/gp[41] dv dd33 packet start input indicator, ts0_pstin (i). vp_din15_vp_vsync/ ac18 ts0_din7 vp_din14_vp_hsync/ aa17 ts0_din6 vp_din13_field/ ab17 ts0_din5 vp_din12/ ac17 these pins are multiplexed between the vpif and tsif0. ts0_din4 ipd i/o/z when tsif0 parallel input mux mode is enabled (pinmux0.ptsimux = 10), dv dd33 vp_din11/ these pins are input data bits ts0_din[7:0] (i). y16 ts0_din3 vp_din10/ aa16 ts0_din2 vp_din9/ ab16 ts0_din1 vp_din8/ ac16 ts0_din0 tsif0 serial input (pinmux0.ptsimux = 11) ipd ts0_clkin ac19 i tsif0 receive clock input (i). dv dd33 this pin is multiplexed between uart1, tsif0, and gpio. ucts1/usd1/ ipu when tsif0 input is enabled (pinmux0.ptsimux = 1x), in synchronous ts0_en_waito/ y17 i/o/z dv dd33 mode, this pin is the data enable indicator (i) or in asynchronous mode, this gp[26] pin is the wait output (o/z), ts0_en_waito. this pin is multiplexed between uart2, tsif0, and gpio. urts2/uirtx2/ ipu when tsif0 input is enabled (pinmux0.ptsimux = 1x), in ac20 i/o/z ts0_pstin/gp[41] dv dd33 synchronous/asynchronous modes, this pin is the packet start input indicator, ts0_pstin (i). this pin is multiplexed between uart1, tsif0, and gpio. urxd1/ ipd when tsif0 serial input mux mode is enabled (pinmux0.ptsimux = 11), in y18 i/o/z ts0_din7/gp[23] dv dd33 synchronous/asynchronous modes, this pin is the serial input data bit (i), ts0_din7(i). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 55
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-17. transport stream interface 0 (tsif0) terminal functions (continued) signal type (1) other (2) (3) description name no. tsif0 parallel output (pinmux0.ptsimux = 10) this pin is multiplexed between the vpif and tsif0. vp_clko3/ - ac10 o/z when tsif0 output is enabled (pinmux0.ptsomux = 1x), this pin is the ts0_clko dv dd33 transmit clock output, ts0_clko (o/z). this pin is multiplexed between uart0, tsif0, and gpio. udtr0/ ipu when tsif0 output is enabled (pinmux0.ptsomux = 1x), this pin is the y12 i/o/z ts0_enao/gp[36] dv dd33 data enable indicator, ts0_enao (o/z) in either synchronous/asynchronous modes. this pin is multiplexed between uart0, tsif0, and gpio. udsr0/ ipu when tsif0 output is enabled (pinmux0.ptsomux = 1x), this pin is the ts0_psto/ ab11 i/o/z dv dd33 packet start output indicator, ts0_psto (o/z) in either gp[37] synchronous/asynchronous modes. this pin is multiplexed between uart0, tsif0, and gpio. udcd0/ ipu when tsif0 output is enabled (pinmux0.ptsomux = 1x), in asynchronous ts0_waitin/ aa11 i/o/z dv dd33 mode, this pin is the wait input, ts0_waitin (i). gp[38] this tsif pin function is not used in synchronous mode. vp_din7/ ts0_dout7/ y14 ts1_din vp_din6/ these pins are multiplexed between the vpif, tsif0, and tsif1. ts0_dout6/ aa14 when parallel tsif0 output is enabled (pinmux0.ptsomux = 10), and ts1_pstin ipd i/o/z tsif1 vpif_din muxing is not enabled (tssi_mux 1 11), these pins are dv dd33 vp_din5/ the output data bits ts0_dout[7:4] (o/z) in either ts0_dout5/ ab14 synchronous/asynchronous modes. ts1_en_waito vp_din4/ ts0_dout4/ ac14 ts1_waito vp_din3/ y15 ts0_dout3 vp_din2/ these pins are multiplexed between the vpif and tsif0. aa15 ts0_dout2 ipd when parallel tsif0 output is enabled (pinmux0.ptsomux = 10), these i/o/z dv dd33 pins are the output data bits ts0_dout[3:0] (o/z) in either vp_din1/ ab15 synchronous/asynchronous modes. ts0_dout1 vp_din0/ ac15 ts0_dout0 tsif0 serial output (pinmux0.ptsimux = 11) this pin is multiplexed between the vpif and tsif0. vp_clko3/ - ac10 o/z when tsif0 output is enabled (pinmux0.ptsomux = 1x), this pin is the ts0_clko dv dd33 transmit clock output, ts0_clko (o/z). this pin is multiplexed between uart0, tsif0, and gpio. udtr0/ ipu when tsif0 output is enabled (pinmux0.ptsomux = 1x), this pin is the y12 i/o/z ts0_enao/gp[36] dv dd33 data enable indicator, ts0_enao (o/z) in either synchronous/asynchronous modes. this pin is multiplexed between uart0, tsif0, and gpio. udsr0/ ipu when tsif0 output is enabled (pinmux0.ptsomux = 1x), this pin is the ab11 i/o/z ts0_psto/gp[37] dv dd33 packet start output indicator, ts0_psto (o/z) in either synchronous/asynchronous modes. this pin is multiplexed between uart0, tsif0, and gpio. udcd0/ ipu when tsif0 output is enabled (pinmux0.ptsomux = 1x), in asynchronous aa11 i/o/z ts0_waitin/gp[38] dv dd33 mode, this pin is the wait input, ts0_waitin (i). this tsif pin function is not used in synchronous mode. this pin is multiplexed between uart1, tsif0, and gpio. utxd1/urctx1/ ipd when serial tsif0 output is enabled (pinmux0.ptsomux = 11), in ab19 i/o/z ts0_dout7/gp[24] dv dd33 synchronous/asynchronous modes, this pin is the serial output data bit, ts0_dout[7] (o/z). device overview 56 submit documentation feedback
3.7.14 transport stream interface 1 (tsif1) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-18. transport stream interface 1 (tsif1) terminal functions signal type (1) other (2) (3) description name no. tsif1 input ? uart0 muxing (pinmux0.tssimux = 01) ipd ts1_clkin ac11 i tsif1 receive clock input (i). dv dd33 this pin is multiplexed between uart0 and tsif1. urxd0/ ipd ab13 i when tsif1 input on uart0 muxing is enabled (pinmux0.tssimux = 01), this ts1_din dv dd33 pin is the serial data input, ts1_din (i). this pin is multiplexed between uart0 and tsif1. urts0/uirtx0/ ipu when tsif1 input on uart0 muxing is enabled (pinmux0.tssimux = 01), in aa13 i/o/z ts1_en_waito dv dd33 synchronous mode, this pin is the data enable indicator (i) or in asynchronous mode, this pin is the wait output, ts1_en_waito (o/z). this pin is multiplexed between uart0 and tsif1. utxd0/urctx0/ ipd y13 i/o/z when tsif1 input on uart0 muxing is enabled (pinumx0.tssimux = 01), this ts1_pstin dv dd33 pin is the packet start indicator, ts1_pstin (i). tsif1 input ? vpif dout muxing (pinmux0.tssimux = 10) ipd ts1_clkin ac11 i tsif1 receive clock input (i). dv dd33 this pin is multiplexed between vpif and tsif1. vp_dout15/ ipd ab8 i/o/z when tsif1 input on vpif dout muxing is enabled (pinmux0.tssimux = 10), ts1_din dv dd33 this pin is the serial data input, ts1_din (i). this pin is multiplexed between vpif and tsif1. vp_dout13/ ipd when tsif1 input on vpif dout muxing is enabled (pinmux0.tssimux = 10), in y9 i/o/z ts1_en_waito dv dd33 synchronous mode, this pin is the data enable indicator (i) or in asynchronous mode, this pin is the wait output, ts1_en_waito (o/z). this pin is multiplexed between vpif and tsif1. vp_dout14/ ipd when tsif1 input on vpif dout muxing is enabled (pinmux0.tssimux = 10), in ac7 i/o/z ts1_pstin dv dd33 synchronous/asynchronous modes, this pin is the packet start indicator, ts1_pstin (i). tsif1 input ? vpif din muxing (pinmux0.tssimux = 11) ipd ts1_clkin ac11 i tsif1 receive clock input (i). dv dd33 vp_din7/ this pin is multiplexed between vpif, tsif0, and tsif1. ipd ts0_dout7/ y14 i/o/z when tsif1 input on vpif din muxing is enabled (pinmux0.tssimux = 11), in dv dd33 ts1_din synchronous/asynchronous modes, this pin is the serial data input, ts1_din (i). this pin is multiplexed between vpif, tsif0, and tsif1. vp_din5/ ipd when tsif1 input on vpif din muxing is enabled (pinmux0.tssimux = 11), in ts0_dout5/ ab14 i/o/z dv dd33 synchronous mode, this pin is the data enable indicator (i) or in asynchronous ts1_en_waito mode, this pin is the wait output, ts1_en_waito (o/z). this pin is multiplexed between vpif, tsif0, and tsif1. vp_din6/ ipd when tsif1 input on vpif din muxing is enabled (pinmux0.tssimux = 11), in ts0_dout6/ aa14 i/o/z dv dd33 synchronous/asynchronous modes, this pin is the packet start indicator, ts1_pstin ts1_pstin (i). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 57
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-18. transport stream interface 1 (tsif1) terminal functions (continued) signal type (1) other (2) (3) description name no. tsif1 output ? vpif dout muxing (pinmux0.tssomux = 10) this pin is multiplexed between the vpif and tsif1. vp_clkin3/ ipd when tsif1 output is enabled (pinmux0.tssomux = 1x), in ac9 i/o/z ts1_clko dv dd33 synchronous/asynchronous modes, this pin is the transmit clock output, ts1_clko (o/z). this pin is multiplexed between the vpif and tsif1. vp_dout11/ ipd when tsif1 output on vpif dout muxing is enabled (pinmux0.tssomux = 10), ab10 i/o/z ts1_dout dv dd33 in synchronous/asynchronous modes, this pin is the serial data output, ts1_dout (o/z). this pin is multiplexed between the vpif and tsif1. vp_dout9/ ipd when tsif1 output on vpif dout muxing is enabled (pinmux0.tssomux = 10), ac8 i/o/z ts1_enao dv dd33 in synchronous/asynchronous modes, this pin is the data enable indicator, ts1_enao (o/z). this pin is multiplexed between the vpif and tsif1. vp_dout10/ ipd when tsif1 output on vpif dout muxing is enabled (pinmux0.tssomux = 10), aa10 i/o/z ts1_psto dv dd33 in synchronous/asynchronous modes, this pin is the packet start indicator output, ts1_psto (o/z). this pin is multiplexed between the vpif and tsif1. vp_dout8/ ipd when tsif1 output on vpif dout muxing is enabled (pinmux0.tssomux = 10), ab9 i/o/z ts1_waitin dv dd33 in asynchronous mode, this pin is the wait indicator input, ts1_waitin (i). this tsif pin function is not used in synchronous mode. tsif1 output ? uart/pwm muxing (pinmux0.tssomux = 11) this pin is multiplexed between the vpif and tsif1. vp_clkin3/ ipd when tsif1 output is enabled (pinmux0.tssomux = 1x), in ac9 i/o/z ts1_clko dv dd33 synchronous/asynchronous modes, this pin is the transmit clock output, ts1_clko (o/z). this pin is multiplexed between pwm1 and tsif1. pwm1/ - when tsif1 output on uart/pwm is enabled (pinmux0.tssomux = 11), in w18 i/o/z ts1_dout dv dd33 synchronous/asynchronous modes, this pin is the serial data output, ts1_dout (o/z). this pin is multiplexed between pwm0, crgen0, and tsif1. pwm0/ - when tsif1 output on uart/pwm is enabled (pinmux0.tssomux = 11), in crg0_po/ w17 o/z dv dd33 synchronous/asynchronous modes, this pin is the data enable indicator output, ts1_enao ts1_enao (o/z) ucts2/usd2/ this pin is multiplexed between uart2, crgen0, gpio, and tsif1. crg0_vcx1/ ipu when tsif1 output on uart/pwm is enabled (pinmux0.tssomux = 11), in ac21 i/o/z gp[42]/ dv dd33 synchronous/asynchronous modes, this pin is the packet start indicator output, ts1_psto ts1_psto (o/z). this pin is multiplexed between uart0, gpio, and tsif1. urin0/gp[8]/ ipd when tsif1 output on uart/pwm is enabled (pinmux0.tssomux = 11), in y11 i/o/z ts1_waitin dv dd33 asynchronous mode, this pin is the wait indicator input, ts1_waitin (i). this tsif pin function is not used in synchronous mode. device overview 58 submit documentation feedback
3.7.15 inter-integrated circuit (i2c) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-19. i2c terminal functions signal type (1) other (2) description name no. i2c - i2c clock output scl. for proper device operation, this pin must be pulled up via scl u5 i/o/z dv dd33 external resistor. - i2c bidirectional data signal sda. for proper device operation, this pin must be sda u4 i/o/z dv dd33 pulled up via external resistor. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 59
3.7.16 serial peripheral interface (spi) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-20. spi terminal functions signal type (1) other (2) (3) description name no. spi ipd spi_clk v1 i/o/z spi clock dv dd33 ipd spi_en t5 i/o/z spi device enable dv dd33 ipd spi_cs0 t4 i/o/z spi chip select 0 dv dd33 ipd spi_cs1 u3 i/o/z spi chip select 1 dv dd33 ipd spi_somi r5 i/o/z spi slave out, master in data pin dv dd33 ipd spi_simo p5 i/o/z spi slave in, master out data pin dv dd33 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 60 submit documentation feedback
3.7.17 multichannel audio serial port (mcasp) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-21. multichannel audio serial port (mcasp) terminal functions signal type (1) other (2) (3) description name no. mcasp0 ipd aclkr0 aa2 i/o/z mcasp0 receive bit clock dv dd33 ipd ahclkr0 ab2 i/o/z mcasp0 receive high-frequency master clock dv dd33 ipd afsr0 y3 i/o/z mcasp0 receive frame sync dv dd33 ipd aclkx0 aa1 i/o/z mcasp0 transmit bit clock dv dd33 ipd ahclkx0 y1 i/o/z mcasp0 transmit high-frequency master clock dv dd33 ipd afsx0 y4 i/o/z mcasp0 transmit frame sync dv dd33 axr0[3] w3 axr0[2] w4 ipd i/o/z mcasp0 transmit/receive data pins [3:0] dv dd33 axr0[1] v4 axr0[0] v3 ipd amute0 y2 i/o/z mcasp0 mute output dv dd33 ipd amutein0 aa3 i mcasp0 mute input dv dd33 mcasp1 ipd aclkx1 w1 i/o/z mcasp1 transmit bit clock dv dd33 ipd ahclkx1 w2 i/o/z mcasp1 transmit high-frequency master clock dv dd33 ipd axr1[0] v2 i/o/z mcasp1 transmit data pin [0] dv dd33 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 61
3.7.18 clock recovery generator (crgen) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-22. clock recovery generator (crgen) terminal functions signal type (1) other (2) (3) description name no. crgen1 only mode (pinmux0.crgmux = 001) urxd2/ this pin is multiplexed between uart2, crgen1, gpio, and crgen0. crg1_vcxi/ ipd ab20 i/o/z when crgen1 is enabled (pinmux0.crgmux = 001), this pin is crgen1 input gp[39]/ dv dd33 clock from external vcxo, crg1_vcxi (i). crg0_vcxi utxd2/ urctx2/ this pin is multiplexed between uart2, crgen1, gpio, and crgen0. crg1_po/ ipd aa19 i/o/z when crgen1 is enabled (pinmux0.crgmux = 001), this pin is crgen1 gp[40]/ dv dd33 pulse width modulation output, crg1_po (o/z). crg0_po crgen0 only (uart2/pwm0 mux) mode (pinmux0.crgmux = 100) ucts2/ usd2/ this pin is multiplexed between uart2, crgen0, gpio, and tsif1. crg0_vcxi/ ipu ac21 i/o/z when crgen0 on uart2/pwm muxing is enabled (pinmux0.crgmux = 10x), gp[42]/ dv dd33 this pin is crgen0 input clock from external vcxo, crg0_vcxi (i). ts1_psto pwm0/ this pin is multiplexed between pwm0, crgen0, and tsif1. ? crg0_po/ w17 o/z when crgen0 on uart2/pwm muxing is enabled (pinmux0.crgmux = 10x), dv dd33 ts1_enao this pin is crgen0 pulse width modulation output, crg0_po (o/z). crgen0 and crgen1 mode (pinmux0.crgmux = 101) urxd2/ this pin is multiplexed between uart2, crgen1, gpio, and crgen0. crg1_vcxi/ ipd ab20 i/o/z when crgen1 is enabled (pinmux0.crgmux = x01), this pin is crgen1 input gp[39]/ dv dd33 clock from external vcxo, crg1_vcxi (i). crg0_vcxi utxd2/ urctx2/ this pin is multiplexed between uart2, crgen1, gpio, and crgen0. crg1_po/ ipd aa19 i/o/z when crgen1 is enabled (pinmux0.crgmux = x01), this pin is crgen1 gp[40]/ dv dd33 pulse width modulation output, crg1_po (o/z). crg0_po ucts2/ usd2/ this pin is multiplexed between uart2, crgen0, gpio, and tsif1. crg0_vcxi/ ipu ac21 i/o/z when crgen0 on uart2/pwm muxing is enabled (pinmux0.crgmux = 10x), gp[42]/ dv dd33 this pin is crgen0 input clock from external vcxo, crg0_vcxi (i). ts1_psto pwm0/ this pin is multiplexed between pwm0, crgen0, and tsif1. ? crg0_po/ w17 o/z when crgen0 on uart2/pwm muxing is enabled (pinmux0.crgmux = 10x), dv dd33 ts1_enao this pin is crgen0 pulse width modulation output, crg0_po (o/z). crgen0 only (uart2 mux) mode (pinmux0.crgmux = 110) urxd2/ this pin is multiplexed between uart2, crgen1, gpio, and crgen0. crg1_vcxi/ ipd ab20 i/o/z when crgen0 on uart2 muxing is enabled (pinmux0.crgmux = 110), this gp[39]/ dv dd33 pin is crgen0 input clock from external vcxo, crg0_vcxi (i). crg0_vcxi utxd2/ urctx2/ this pin is multiplexed between uart2, crgen1, gpio, and crgen0. crg1_po/ ipd aa19 i/o/z when crgen0 on uart2 muxing is enabled (pinmux0.crgmux = 110), this gp[40]/ dv dd33 pin is crgen0 pulse width modulation output, crg0_po (o/z). crg0_po (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 62 submit documentation feedback
3.7.19 uart0 tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-23. uart0 terminal functions signal type (1) other (2) (3) description name no. actual uart0 pin functions are determined by the pinmux0 and pinmux1 register bit settings. for more details, see section 4.7.3 , pin multiplexing. uart0 with modem control (pinmux1.uart0ctl = 00) this pin is multiplexed between uart0 and tsif1. urxd0/ ipd when uart0 uart functional muxing is selected (pinmux1.uart0ctl = 0x) ab13 i ts1_din dv dd33 and tsif1 input on uart0 muxing is not enabled (pinmux0.tssimux 1 01), this pin is uart0 receive data, urxd0 (i). this pin is multiplexed between uart0 and tsif1. utxd0/ ipd when uart0 uart functional muxing is selected (pinmux1.uart0ctl = 0x) urctx0/ y13 i/o/z dv dd33 and tsif1 input on uart0 muxing is not enabled (pinmux0.tssimux 1 01), this ts1_pstin pin is uart0 transmit data, utxd0 (o/z). this pin is multiplexed between uart0 and tsif1. urts0/ ipu when uart0 uart functional muxing is selected (pinmux1.uart0ctl = 0x) uirtx0/ aa13 i/o/z dv dd33 and tsif1 input on uart0 muxing is not enabled (pinmux0.tssimux 1 01), this ts1_en_waito pin is the uart0 request-to-send signal, urts0 (o/z). this pin is multiplexed between uart0 and tsif1. ipu when uart0 uart functional muxing is selected (pinmux1.uart0ctl = 0x) ucts0/ usd0 ac12 i/o/z dv dd33 and tsif1 input on uart0 muxing is not enabled (pinmux0.tssimux 1 01), this pin is the uart0 clear-to-send signal, ucts0 (i). this pin is multiplexed between uart0, tsif0, and gpio. udtr0/ ipu when uart0 uart with modem functional muxing is selected ts0_enao/ y12 i/o/z dv dd33 (pinmux1.uart0ctl = 00) and tsif0 output muxing is not enabled gp[36] (pinmux0.ptsomux 1 1x), this pin is uart0 data-terminal-ready, udtr0 (o/z). this pin is multiplexed between uart0, tsif0, and gpio. udsr0/ ipu when uart0 uart with modem functional muxing is selected ts0_psto/ ab11 i/o/z dv dd33 (pinmux1.uart0ctl = 00) and tsif0 output muxing is not enabled gp[37] (pinmux0.ptsomux 1 1x), this pin is uart0 data-set-ready, udsr0 (i). this pin is multiplexed between uart0, tsif0, and gpio. udcd0/ ipu when uart0 uart with modem functional muxing is selected ts0_waitin/ aa11 i/o/z dv dd33 (pinmux1.uart0ctl = 00) and tsif0 output muxing is not enabled gp[38] (pinmux0.ptsomux 1 1x), this pin is uart0 data-carrier-detect, udcd0 (i). this pin is multiplexed between uart0, gpio, and tsif1. when uart0 uart with modem functional muxing is selected urin0/gp[8]/ ipd y11 i/o/z (pinmux1.uart0ctl = 00) and tsif1 output on uart/pwm muxing is not ts1_waitin dv dd33 enabled (pinmux0.tssomux 1 11), this pin is the uart0 ring indicator, urin0 (i). uart0 without modem control (pinmux1.uart0ctl = 01) this pin is multiplexed between uart0 and tsif1. urxd0/ ipd when uart0 uart functional muxing is selected (pinmux1.uart0ctl = 0x) ab13 i ts1_din dv dd33 and tsif1 input on uart0 muxing is not enabled (pinmux0.tssimux 1 01), this pin is uart0 receive data, urxd0 (i). this pin is multiplexed between uart0 and tsif1. utxd0/ ipd when uart0 uart functional muxing is selected (pinmux1.uart0ctl = 0x) urctx0/ y13 i/o/z dv dd33 and tsif1 input on uart0 muxing is not enabled (pinmux0.tssimux 1 01), this ts1_pstin pin is uart0 transmit data, utxd0 (o/z). this pin is multiplexed between uart0 and tsif1. urts0/ ipu when uart0 uart functional muxing is selected (pinmux1.uart0ctl = 0x) uirtx0/ aa13 i/o/z dv dd33 and tsif1 input on uart0 muxing is not enabled (pinmux0.tssimux 1 01), this ts1_en_waito pin is uart0 request-to-send signal, urts0 (o/z). when uart0 uart functional muxing is selected (pinmux1.uart0ctl = 0x) ucts0/ ipu ac12 i/o/z and tsif1 input on uart0 muxing is not enabled (pinmux0.tssimux 1 01), this usd0 dv dd33 pin is uart0 clear-to-send signal, ucts0 (i). (1) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (2) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 63
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-23. uart0 terminal functions (continued) signal type (1) other (2) (3) description name no. uart0 irda/cir function (pinmux1.uart0ctl = 1x) this pin is multiplexed between uart0 and tsif1. urxd0/ ipd ab13 i when tsif1 input on uart0 muxing is not enabled (pinmux0.tssimux 1 01), ts1_din dv dd33 this pin is uart0 irda/cir receive data, urxd0 (i). this pin is multiplexed between uart0 and tsif1. utxd0/ ipd when uart0 irda/cir functional muxing is selected (pinmux1.uart0ctl = 1x) urctx0/ y13 i/o/z dv dd33 and tsif1 input on uart0 muxing is not enabled (pinmux0.tssimux 1 01), this ts1_pstin pin is uart0 cir transmit data, urctx0 (o/z). this pin is multiplexed between uart0 and tsif1. urts0/ ipu when uart0 irda/cir functional muxing is selected (pinmux1.uart0ctl = 1x) uirtx0/ aa13 i/o/z dv dd33 and tsif1 input on uart0 muxing is not enabled (pinmux0.tssimux 1 01), this ts1_en_waito pin is uart0 irda transmit data, uirtx0 (o/z). when uart0 irda/cir functional muxing is selected (pinmux1.uart0ctl = 1x) ucts0/ ipu ac12 i/o/z and tsif1 input on uart0 muxing is not enabled (pinmux0.tssimux 1 01), this usd0 dv dd33 pin is uart0 irda transceiver control, usd0 (o/z). device overview 64 submit documentation feedback
3.7.20 uart1 tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-24. uart1 terminal functions signal type (1) other (2) (3) description name no. uart1 with flow control (pinmux1.uart1ctl = 00) actual uart1 pin functions are determined by the pinmux0 and pinmux1 register bit settings. for more details, see section 4.7.3 , pin multiplexing. this pin is multiplexed between uart1, tsif0, and gpio. urxd1/ ipd when uart1 uart functional muxing is selected (pinmux1.uart1ctl = 0x) ts0_din7/ y18 i/o/z dv dd33 and tsif0 serial input is not enabled (pinmux0.ptsimux 1 11), this pin is gp[23] uart1 receive data, urxd1 (i). utxd1/ this pin is multiplexed between uart1, tsif0, and gpio. urctx1/ ipd when uart1 uart functional muxing is selected (pinmux1.uart1ctl = 0x) ab19 i/o/z ts0_dout7/ dv dd33 and tsif0 serial output is not enabled (pinmux0.ptsimux 1 11), this pin is gp[24] uart1 transmit data, utxd1 (o/z). this pin is multiplexed between uart1, tsif0, and gpio. urts1/uirtx1/ ipu when uart1 uart with flow control muxing is selected (pinmux1.uart1ctl = ts0_waito/ aa18 i/o/z dv dd33 00) and tsif0 input is not enabled (pinmux0.ptsimux 1 0x), this pin is uart1 gp[25] request-to-send, urts1 (o/z). this pin is multiplexed between uart1, tsif0, and gpio. ucts1/usd1 ipu when uart1 uart with flow control muxing is selected (pinmux1.uart1ctl = ts0_en_waito/ y17 i/o/z dv dd33 00) and tsif0 input is not enabled (pinmux0.ptsimux 1 0x), this pin is uart1 gp[26] clear-to-send, ucts1 (i). uart1 without flow control (pinmux1.uart1ctl = 01) this pin is multiplexed between uart1, tsif0, and gpio. urxd1/ ipd when uart1 uart functional muxing is selected (pinmux1.uart1ctl = 0x) ts0_din7/ y18 i/o/z dv dd33 and tsif0 serial input is not enabled (pinmux0.ptsimux 1 11), this pin is gp[23] uart1 receive data, urxd1 (i). utxd1/ this pin is multiplexed between uart1, tsif0, and gpio. urctx1/ ipd when uart1 uart functional muxing is selected (pinmux1.uart1ctl = 0x) ab19 i/o/z ts0_dout7/ dv dd33 and tsif0 serial output is not enabled (pinmux0.ptsimux 1 11), this pin is gp[24] uart1 transmit data, utxd1 (o/z). uart1 irda/cir function (pinmux1.uart1ctl = 10) this pin is multiplexed between uart1, tsif0, and gpio. urxd1/ ipd when uart1 irda/cir functional muxing is selected (pinmux1.uart1ctl = 10) ts0_din7/ y18 i/o/z dv dd33 and tsif0 serial input is not enabled (pinmux0.ptsimux 1 11), this pin is gp[23] uart1 receive data, urxd1 (i). this pin is multiplexed between uart1, tsif0, and gpio. utxd1/ urctx1/ ipd when uart1 irda/cir functional muxing is selected (pinmux1.uart1ctl = 10) ts0_dout7/ ab19 i/o/z dv dd33 and tsif0 serial output is not enabled (pinmux0.ptsomux 1 11), this pin is gp[24] uart1 cir transmit data, urctx1 (o/z). this pin is multiplexed between uart1, tsif0, and gpio. urts1/ uirtx1/ ipu when uart1 irda/cir functional muxing is selected (pinmux1.uart1ctl = 10) ts0_waito/ aa18 i/o/z dv dd33 and tsif0 input is not enabled (pinmux0.ptsimux = 0x), this pin is uart1 irda gp[25] transmit data, uirtx1 (o/z). this pin is multiplexed between uart1, tsif0, and gpio. ucts1/ usd1/ ipu when uart1 irda/cir functional muxing is selected (pinmux1.uart1ctl = 10) ts0_en_waito/ y17 i/o/z dv dd33 and tsif0 input is not enabled (pinmux0.ptsimux = 0x), this pin is uart1 irda gp[26] tranceiver control, usd1 (o/z). (1) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (2) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 65
3.7.21 uart2 tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-25. uart2 terminal functions signal type (1) other (2) (3) description name no. uart2 with flow control (pinmux1.uart2ctl = 00) actual uart2 pin functions are determined by the pinmux0 and pinmux1 register bit settings. for more details, see section 4.7.3 , pin multiplexing. urxd2/ this pin is multiplexed between uart2, crgen1, gpio, and crgen0. crg1_vcxi/ ipd when uart2 uart functional muxing is selected (pinmux1.uart2ctl = 0x) ab20 i/o/z gp[39]/ dv dd33 and crgen0/1 are not enabled (pinmux0.crgmux 1 x01, 110), this pin is crg0_vcxi uart2 receive data, urxd2 (i). utxd2/ this pin is multiplexed between uart2, crgen1, gpio, and crgen0. urctx2/ ipd when uart2 uart functional muxing is selected (pinmux1.uart2ctl = 0x) crg1_po/ aa19 i/o/z dv dd33 and crgen0/1 are not enabled (pinmux0.crgmux 1 x01, 110), this pin is gp[40]/ uart2 transmit data, utxd2 (o/z). crg0_po this pin is multiplexed between uart2, tsif0, and gpio. urts2/uirtx2/ ipu when uart2 uart with flow control muxing is selected (pinmux1.uart2ctl = ts0_pstin/ ac20 i/o/z dv dd33 00) and tsif0 input is not enabled (pinmux0.ptsimux = 0x), this pin is uart2 gp[41] request-to-send, urts2 (o/z). ucts2/usd2/ this pin is multiplexed between uart2, crgen0, gpio, and tsif1. crg0_vcxi/ ipu when uart2 uart with flow control muxing is selected (pinmux1.uart2ctl = ac21 i/o/z gp[42]/ dv dd33 00) and tsif1 output is not enabled (pinmux0.ptsomux = 0x), this pin is ts1_psto uart2 clear-to-send, ucts2 (i). uart2 without flow control (pinmux1.uart2ctl = 01) urxd2/ this pin is multiplexed between uart2, crgen1, gpio, and crgen0. crg1_vcxi/ ipd when uart2 uart functional muxing is selected (pinmux1.uart2ctl = 0x) ab20 i/o/z gp[39]/ dv dd33 and crgen0/1 are not enabled (pinmux0.crgmux 1 x01, 110), this pin is crg0_vcxi uart2 receive data, urxd2 (i). utxd2/ this pin is multiplexed between uart2, crgen1, gpio, and crgen0. urctx2/ ipd when uart2 uart functional muxing is selected (pinmux1.uart2ctl = 0x) crg1_po/ aa19 i/o/z dv dd33 and crgen0/1 are not enabled (pinmux0.crgmux 1 x01, 110), this pin is gp[40]/ uart2 transmit data, utxd2 (o/z). crg0_po uart2 irda/cir function (pinmux1.uart2ctl = 10) urxd2/ this pin is multiplexed between uart2, crgen1, gpio, and crgen0. crg1_vcxi/ ipd when uart2 irda/cir functional muxing is selected (pinmux1.uart2ctl = 10) ab20 i/o/z gp[39]/ dv dd33 and crgen0/1 are not enabled (pinmux0.crgmux 1 x01, 110), this pin is crg0_vcxi uart2 receive data, urxd2 (i). utxd2/ urctx2/ this pin is multiplexed between uart2, crgen1, gpio, and crgen0. crg1_po/ ipd when uart2 irda/cir functional muxing is selected (pinmux1.uart2ctl = 10) aa19 i/o/z gp[40]/ dv dd33 and crgen0/1 are not enabled (pinmux0.crgmux 1 x01, 110), this pin is the crg0_po uart2 cir transmit data, urctx2 (o/z). this pin is multiplexed between uart2, tsif0, and gpio. urts2/ uirtx2/ ipu when uart2 irda/cir functional muxing is selected (pinmux1.uart2ctl = 10) ts0_pstin/ ac20 i/o/z dv dd33 and tsif0 input is not enabled (pinmux0.ptsimux = 0x), this pin is uart2 irda gp[41] transmit data, uirtx2 (o/z). ucts2/ usd2/ this pin is multiplexed between uart2, crgen0, gpio, and tsif1. crg0_vcxi/ ipu when uart2 irda/cir functional muxing is selected (pinmux1.uart2ctl = 10) ac21 i/o/z gp[42]/ dv dd33 and crgen0 on tsif0 output is not enabled (pinmux0.tssomux = 0x), this ts1_psto pin is uart2 irda tranceiver control, usd2 (o/z). (1) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (2) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (3) specifies the operating i/o supply voltage for each signal device overview 66 submit documentation feedback
3.7.22 pulse-width modulation (pwm) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-26. pwm terminal functions signal type (1) other (2) description name no. pwm0 this pin is multiplexed between pwm0, crgen0, and tsif1. pwm0/ ? when not overridden by crgen or tsif1 output muxing (pinmux0.crgmux 1 crg0_po/ w17 o/z dv dd33 10x and pinmux0.tssomux 1 11), this pin is the pulse width modulation 0 output, ts1_enao pwm0 (o/z). pwm1 this pin is multiplexed between pwm1 and tsif1. pwm1/ ? w18 o/z when not overridden by tsif1 output muxing (pinmux0.tssomux 1 11), this pin ts1_dout dv dd33 is the pulse width modulation 1 output, pwm1 (o/z). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 67
3.7.23 timers (timer 0, timer 1, and timer 2) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-27. timer 0, timer 1, and timer 2 terminal functions signal type (1) other (2) (3) description name no. timer 0 ipd timer0 lower input. this pin is the timer0 input for 64-mode operation. for 32-bit tinp0l y7 i/o/z dv dd33 timer operation, this pin is the input for the timer0 lower 32-bit counter. ipd timer0 upper input. for 32-bit timer operation, this pin is the input for the timer0 tinp0u aa6 i/o/z dv dd33 upper 32-bit counter. not used for timer0 64-mode operation. ipd timer0 lower output. this pin is the timer0 output for 64-mode operation. for 32-bit tout0l w8 i/o/z dv dd33 timer operation, this pin is the output for the timer0 lower 32-bit counter. ipd timer0 upper output. for 32-bit timer operation, this pin is the output for the timer0 tout0u w7 i/o/z dv dd33 upper 32-bit counter. not used for timer0 64-mode operation. timer 1 ipd timer1 lower input. this pin is the timer1 input for 64-mode operation. for 32-bit tinp1l y6 i/o/z dv dd33 timer operation, this pin is the input for the timer1 lower 32-bit counter. ipd timer1 lower output. this pin is the timer1 output for 64-mode operation. for 32-bit tout1l aa5 i/o/z dv dd33 timer operation, this pin is the output for the timer1 lower 32-bit counter. ipd timer1 upper output. for 32-bit timer operation, this pin is the output for the timer1 tout1u ab4 i/o/z dv dd33 upper 32-bit counter. not used for timer1 64-mode operation. watchdog timer (timer 2) ipd tout2 y5 i/o/z watchdog timer output. dv dd33 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 68 submit documentation feedback
3.7.24 ata tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-28. ata terminal functions signal type (1) other (2) (3) description name no. ata ata is enabled by the pinmux0.ataen =1 ( and pcien = 0). for more detailed information on the ata pin muxing, see section 4.7.3.1 , pci, hpi, emifa, and ata pin muxing. pci_cbe0/ ipu this pin is multiplexed between pci, ata, gpio, and emifa. ata_cs0/ f4 i/o/z dv dd33 when ata is enabled, this pin is ata chip select 0 output, ata_cs0 (o/z). gp[33]/em_a[18] pci_cbe1/ ipu this pin is multiplexed between pci, ata, gpio, and emifa. ata_cs1/ c2 i/o/z dv dd33 when ata is enabled, this pin is ata chip select 1 output, ata_cs1 (o/z). gp[32]/em_a[19] pci_rsv4/ diow/ ipu this pin is multiplexed between pci, ata, gpio, and emifa. a11 i/o/z gp[20]/em_wait4 dv dd33 when ata is enabled, this pin is the ata write strobe output, diow (o/z). pci_rsv3/ dior/ ipu this pin is multiplexed between pci, ata, gpio, and emifa. e10 i/o/z gp[19]/em_wait5 dv dd33 when ata is enabled, this pin is the ata read strobe output, dior (o/z). pci_rsv5/ iordy/ ipu this pin is multiplexed between pci, ata, gpio, and emifa. d11 i/o/z gp[21]/em_wait3 dv dd33 when ata is enabled, this pin is ata i/o ready, iordy (i). pci_rst/ ipd this pin is multiplexed between pci, ata, gpio, and emifa. da2/ c10 i/o/z dv dd33 when ata is enabled, this pin is ata address bit 2, da2 (o/z). gp[13]/em_a[22] pci_rsv0/ da1/ ipd this pin is multiplexed between pci, ata, gpio, and emifa. a9 i/o/z gp[16]/em_a[21] dv dd33 when ata is enabled, this pin is ata address bit 1, da1 (o/z). pci_rsv1/ da0/ ipd this pin is multiplexed between pci, ata, gpio, and emifa. e9 i/o/z gp[17]/em_a[20] dv dd33 when ata is enabled, this pin is ata address bit 0, da0 (o/z). pci_rsv2/ intrq/ ipd this pin is multiplexed between pci, ata, gpio, and emifa. b10 i/o/z gp[18]/em_rsv0 dv dd33 when ata is enabled, this pin is the ata interrupt request input, intrq (i). pci_req/ ipu this pin is multiplexed between pci, ata, gpio, and emifa. dmarq/ b9 i/o/z dv dd33 when ata is enabled, this pin is the ata dma request input, dmarq (i). gp[11]/ em_cs5 pci_gnt/ this pin is multiplexed between pci, ata, gpio, and emifa. ipu dmack/ d10 i/o/z when ata is enabled, this pin is the ata dma acknowledge output, dmack dv dd33 gp[12]/ em_cs4 (o/z). pci_idsel/ this pin is multiplexed between pci, ata, and emifa. ipu hddir/ e8 i/o/z when ata is enabled, this pin is the data direction indicator for external buffer dv dd33 em_r/ w control, hddir (o/z). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 69
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-28. ata terminal functions (continued) signal type (1) other (2) (3) description name no. pci_ad31/ dd15/ a8 hd31/ em_a[15] pci_ad30/ dd14/ c9 hd30/em_a[14] pci_ad29/ dd13/ b8 hd29/em_a[13] pci_ad28/ dd12/ d9 hd28/em_a[12] pci_ad27/ dd11/ a6 hd27/em_a[11] pci_ad26/ dd10/ c8 hd26/em_a[10] pci_ad25/ dd9/ b6 hd25/em_a[9] pci_ad24/ dd8/ d8 these pins are multiplexed between pci, ata, hpi, and emifa. hd24/em_a[8] ipd i/o/z when ata is enabled, these pins are the ata 16-bit bidirectional data bus, dv dd33 pci_ad23/ dd[15:0] (i/o/z). dd7/ b5 hd23/em_a[7] pci_ad22/ dd6/ c7 hd22/em_a[6] pci_ad21/ dd5/ c5 hd21/em_a[5] pci_ad20/ dd4/ d7 hd20/em_a[4] pci_ad19/ dd3/ a4 hd19/em_a[3] pci_ad18/ dd2/ e7 hd18/em_a[2] pci_ad17/ dd1/ b4 hd17/em_a[1] pci_ad16/ dd0/ c6 hd16/em_a[0] device overview 70 submit documentation feedback
3.7.25 general purpose input/output (gpio) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-29. general purpose input/output (gpio) terminal functions signal type (1) other (2) (3) description name no. gpio the dm6467 device does not support gp[47:43], gp[35:34], gp[31:27], gp[15:14], and gp[9] signals (not pinned out). gp[7:0] pins have dedicated arm926 and dsp interrupts. when pci is used, gp[19:16] pins are reserved. ipd gp[0] w5 i/o/z gp[0] (i/o/z). this pin is general-purpose input/output 0. dv dd33 ipd gp[1] v5 i/o/z gp[1] (i/o/z). this pin is general-purpose input/output 1. dv dd33 gp[2]/ ipd this pin is multiplexed between gpio and the audio clock selector. aa4 i/o/z audio_clk1 dv dd33 when audio clock 1 is disabled (pinmux0.audck1 = 0), this pin is gp[2] (i/o/z). gp[3]/ ipd this pin is multiplexed between gpio and the audio clock selector. ab3 i/o/z audio_clk0 dv dd33 when audio clock 0 is disabled (pinmux0.audck0 = 0), this pin is gp[3] (i/o/z). this pin is multiplexed between gpio and the tsif clock selector. gp[4]/ ipd ac3 i/o/z when the stc source clock input is disabled (pinmux0.stcck = 0), this pin is stc_clkin dv dd33 gp[4] (i/o/z). ipd gp[5] b11 i/o/z this pin is gp[5] (i/o/z). dv dd33 this pin is multiplexed between gpio and smartreflex (voltage adjust) control gp[6]/ ipd outputs. e11 i/o/z cvddadj0 dv dd33 when the core voltage adjust function is disabled (vp_dout7/vadjen = 0 at reset), this pin is gp[6] (i/o/z). this pin is multiplexed between gpio and smartreflex (voltage adjust) control gp[7]/ ipd outputs. a12 i/o/z cvddadj1 dv dd33 when the core voltage adjust function is disabled (vp_dout7/vadjen = 0 at reset), this pin is gp[7] (i/o/z). this pin is multiplexed between uart0, gpio, and tsif1. urin0/ gp[8]/ ipd when uart0 uart with modem functional muxing is not selected y11 i/o/z ts1_waitin dv dd33 (pinmux1.uart0ctl = 00) and tsif1 output on uart/pwm muxing is not enabled (pinmux0.tssomux 1 11), this pin is gp[8] (i/o/z). gp[9] n/a ? ? gp[9] is not pinned out on this device. ipu this pin is multiplexed between pci and gpio. pci_clk/ gp[10] a10 i/o/z dv dd33 when pci is disabled (pinmux0.pcien = 0), this pin is gp[10] (i/o/z). pci_req/ this pin is multiplexed between pci, ata, gpio, and emifa. ipu dmarq/ b9 i/o/z when 32-bit hpi mode is enabled (pinmux0.pcien = 0, pinmux0.hpien = 1, dv dd33 gp[11]/ em_cs5 pinmux0.ataen = 0), this pin is gp[11] (i/o/z). pci_gnt/ this pin is multiplexed between pci, ata, gpio, and emifa. ipu dmack/ d10 i/o/z when 32-bit hpi mode is enabled (pinmux0.pcien = 0, pinmux0.hpien = 1, dv dd33 gp[12]/ em_cs4 pinmux0.ataen = 0), this pin is gp[12] (i/o/z). pci_rst/ this pin is multiplexed between pci, ata, gpio, and emifa. ipd da2/ c10 i/o/z when 32-bit hpi mode is enabled (pinmux0.pcien = 0, pinmux0.hpien = 1, dv dd33 gp[13]/em_a[22] pinmux0.ataen = 0), this pin is gp[13] (i/o/z). gp[14:15] n/a ? ? gp[14:15] are not pinned out on this device. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 71
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-29. general purpose input/output (gpio) terminal functions (continued) signal type (1) other (2) (3) description name no. pci_rsv0/da1/ ipd gp[16]/ a9 i/o/z dv dd33 em_a[21] pci_rsv1/da0/ ipd e9 i/o/z gp[17]/em_a[20] dv dd33 these pins are multiplexed between pci, ata, gpio, and emifa. when 32-bit hpi mode is enabled (pinmux0.pcien = 0, pinmux0.hpien = 1, pci_rsv2/ pinmux0.ataen = 0), these pins are gp[16:19] (i/0/z). when pci mode is enabled intrq/ ipd b10 i/o/z (pinmux0.pcien = 1), these pins are reserved. gp[18]/ dv dd33 em_rsv0 pci_rsv3/ dior/ ipu gp[19]/ e10 i/o/z dv dd33 em_wait5 pci_rsv4/ diow/ ipu a11 i/o/z gp[20]/ dv dd33 these pins are multiplexed between pci, ata, gpio, and emifa. em_wait4 when 32-bit hpi mode is enabled (pinmux0.pcien = 0, pinmux0.hpien = 1, pci_rsv5/ pinmux0.ataen = 0), these pins are gp[20:21] (i/0/z). iordy/ ipu d11 i/o/z gp[21]/ dv dd33 em_wait3 usb_drvvbus/ ipd this pin is multiplexed between usb and gpio. b18 i/o/z gp[22] dv dd33 when not used for usb (pinmux0.vbusdis = 1), this pin is gp[22] (i/o/z). urxd1/ this pin is multiplexed between uart1, tsif0, and gpio. ipd ts0_din7/ y18 i/o/z when uart1 gpio muxing is selected (pinmux1.uart1ctl = 11) and tsif0 dv dd33 gp[23] serial input is not enabled (pinmux0.ptsimux 1 11), this pin is gp[23] (i/o/z). utxd1/ this pin is multiplexed between uart1, tsif0, and gpio. urctx1/ ipd ab19 i/o/z when uart1 gpio muxing is selected (pinmux1. uart1ctl = 11) and tsif0 ts0_dout7/ dv dd33 serial input is not enabled (pinmux0.ptsimux 1 11), this pin is gp[24] (i/o/z). gp[24] urts1/ uirtx1/ ipd aa18 i/o/z ts0_waito/ dv dd33 these pins are multiplexed between uart1, tsif0, and gpio. gp[25] when uart1 gpio muxing is selected (pinmux1.uart1ctl = 11) and tsif0 input is not enabled (pinmux0.ptsimux = 0x), these pins are gp[25:26] (i/o/z). ucts1/usd1/ ipu ts0_en_waito/ y17 i/o/z dv dd33 gp[26] gp[27:31] n/a ? ? gp[27:31] are not pinned out on this device. pci_cbe1/ ata_cs1/ ipu c2 i/o/z gp[32]/ dv dd33 these pins are multiplexed between pci, ata, gpio, and emifa. em_a[19] when 32-bit hpi mode is enabled (pinmux0.pcien = 0, pinmux0.hpien = 1, pci_cbe0/ pinmux0.ataen = 0), these pins are gp[32:33] (i/o/z). ata_cs0/ ipu f4 i/o/z gp[33]/ dv dd33 em_a[18] gp[34:35] n/a ? ? gp[34:35] are not pinned out on this device. udtr0/ ipu ts0_enao/ y12 i/o/z dv dd33 gp[36] these pins are multiplexed between uart0, tsif0, and gpio. udsr0/ ipu when uart0 uart with modem functional muxing is not selected ts0_psto/ ab11 i/o/z dv dd33 (pinmux1.uart0ctl 1 00) and tsif0 output muxing is not enabled gp[37] (pinmux0.ptsomux 1 1x), these pins are gp[36:38] (i/o/z). udcd0/ ipu ts0_waitin/ aa11 i/o/z dv dd33 gp[38] device overview 72 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-29. general purpose input/output (gpio) terminal functions (continued) signal type (1) other (2) (3) description name no. urxd2/ crg1_vcxi/ ipd ab20 i/o/z gp[39]/ dv dd33 these pins are multiplexed between uart2, crgen1, gpio, and crgen0. crg0_vcxi when uart2 uart gpio muxing is selected (pinmux1.uart2ctl = 11) and crgen0/1 are not enabled (pinmux0.crgmux 1 x01, 110), these pins are utxd2/urctx2/ gp[39:40] (i/o/z). crg1_po/ ipd aa19 i/o/z gp[40]/ dv dd33 crg0_po this pin is multiplexed between uart2, tsif0, and gpio. urts2/uirtx2/ ipu when uart2 uart without flow control or gpio muxing is selected ts0_pstin/ ac20 i/o/z dv dd33 (pinmux1.uart2ctl = x1) and tsif0 input is not enabled gp[41] (pinmux0.ptsimux = 0x), this pin is gp[41] (i/o/z). this pin is multiplexed between uart2, crgen0, gpio, and tsif1. ucts2/usd2/ when uart2 uart without flow control or gpio muxing is selected crg0_vcxi/ ipu ac21 i/o/z (pinmux1.uart2ctl = x1) and crgen0 on uart2/pwm muxing is not enabled gp[42]/ dv dd33 (pinmux0.crgmux 1 10x) and tsif1 output is not enabled ts1_psto (pinmux0.tssomux = 0x), this pin is gp[42] (i/o/z). gp[43:47] n/a ? ? gp[43:47] are not pinned out on this device. submit documentation feedback device overview 73
3.7.26 reserved tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-30. reserved terminal functions signal type (1) other description name no. reserved rsv1 a1 reserved. for proper device operation, this pin must be tied directly to v ss . rsv2 a2 reserved. for proper device operation, this pin must be tied directly to v ss . rsv3 a22 reserved. for proper device operation, this pin must be tied directly to v ss . rsv4 a23 reserved. (leave unconnected, do not connect to power or ground.) rsv5 d14 reserved. (leave unconnected, do not connect to power or ground.) rsv6 f17 reserved. for proper device operation, this pin must be tied directly to cv dd . rsv7 g16 reserved. for proper device operation, this pin must be tied directly to cv dd . (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal device overview 74 submit documentation feedback
3.7.27 supply tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-31. supply terminal functions signal type (1) other description name no. supply voltage pins b7 f8 f9 f10 f11 f12 f13 f14 f15 f16 g7 h6 j6 k6 k7 3.3-v i/o supply voltage dv dd33 m3 s (see the power-supply decoupling section of this data manual) r7 t7 u7 v7 v8 v17 w9 w10 w11 w12 w13 w14 w15 w16 aa12 b20 e21 g17 g19 h17 1.8-v ddr2 i/o supply voltage dv ddr2 s (see the power-supply decoupling section of this data manual) j17 k17 k21 p21 r17 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal submit documentation feedback device overview 75
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-31. supply terminal functions (continued) signal type (1) other description name no. r18 t18 t19 1.8-v ddr2 i/o supply voltage dv ddr2 s (see the power-supply decoupling section of this data manual) u19 w21 aa20 g8 g9 g10 g11 g12 g13 g14 g15 h7 h8 h9 h14 h15 h16 j7 j8 1.20-v core supply voltage (-594, -594a, -729 devices) j9 (see the power-supply decoupling section of this data manual) j10 smartreflex: when selected (vp_dout7/vadjen = 1 at reset), the gp[7]/cvddadj1 and gp[6]/cvddadj0 pins function as smartreflex control j11 outputs to the adjustable core power supply. for more detailed information on cv dd j13 s smartreflex, see the section 7.3.6 , smartreflex (voltage scaling). j14 1.2-v core supply voltage (-594v, -594av only) [gp[7]/cvddadj1 and j15 gp[6]/cvddadj0 = 00] 1.05-v core supply voltage (-594v, -594av only) [gp[7]/cvddadj1 and j16 gp[6]/cvddadj0 = 11] k8 k9 k10 k11 k13 k14 k15 k16 p7 p8 p9 p10 p11 p13 p14 p15 device overview 76 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-31. supply terminal functions (continued) signal type (1) other description name no. r8 r9 r10 r11 r13 r14 r15 t8 t9 t10 1.20-v core supply voltage (-594, -594a, -729 devices) t11 (see the power-supply decoupling section of this data manual) t13 smartreflex: when selected (vp_dout7/vadjen = 1 at reset), the t14 gp[7]/cvddadj1 and gp[6]/cvddadj0 pins function as smartreflex control t15 outputs to the adjustable core power supply. for more detailed information on cv dd s smartreflex, see the section 7.3.6 , smartreflex (voltage scaling). u8 1.2-v core supply voltage (-594v, -594av only) [gp[7]/cvddadj1 and u9 gp[6]/cvddadj0 = 00] u10 1.05-v core supply voltage (-594v, -594av only) [gp[7]/cvddadj1 and u14 gp[6]/cvddadj0 = 11] u15 u16 v9 v10 v11 v12 v13 v14 v15 v16 submit documentation feedback device overview 77
3.7.28 ground tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-32. ground terminal functions signal type (1) other description name no. ground pins a7 a14 a18 a21 b1 b19 b23 c19 d19 e19 e22 f6 f7 f19 g6 g18 h5 h10 v ss gnd ground pins h11 h12 h13 h18 h19 j5 j12 j18 k5 k12 k18 k22 l5 l6 l7 l8 l9 l10 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal 78 device overview submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 3-32. ground terminal functions (continued) signal type (1) other description name no. l11 l12 l13 l14 l15 l16 l17 l18 m2 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 m16 m17 m18 v ss gnd ground pins n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 n16 n17 n18 p6 p12 p16 p17 p18 p22 r6 r12 r16 submit documentation feedback device overview 79
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 3-32. ground terminal functions (continued) signal type (1) other description name no. t6 t12 t16 t17 u6 u11 u12 u13 u17 u18 v6 v18 v ss gnd ground pins v19 w19 w22 y19 ab1 ab12 ab21 ab23 ac1 ac2 ac22 ac23 device overview 80 submit documentation feedback
3.8 device support 3.8.1 development support 3.8.2 device and development-support tool nomenclature tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 ti offers an extensive line of development tools for the tms320dm646x dmsoc platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. the tool's support documentation is electronically available within the code composer studio? integrated development environment (ide). the following products support development of tms320dm646x soc-based applications: software development tools: code composer studio? integrated development environment (ide): including editor c/c++/assembly code generation, and debug plus additional development tools scalable, real-time foundation software (dsp/bios?), which provides the basic run-time target software needed to support any soc application. hardware development tools: extended development system (xds?) emulator for a complete listing of development-support tools for the tms320dm644x dmsoc platform, visit the texas instruments web site on the worldwide web at http://www.ti.com uniform resource locator (url). for information on pricing and availability, contact the nearest ti field sales office or authorized distributor. to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all dsp devices and support tools. each dsp commercial family member has one of three prefixes: tmx, tmp, or tms (e.g.,tmx320dm6467zut). texas instruments recommends two of three possible prefix designators for its support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (tmx/tmdx) through fully qualified production devices/tools (tms/tmds). device development evolutionary flow: tmx experimental device that is not necessarily representative of the final device's electrical specifications. tmp final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification. tms fully-qualified production device. support tool development evolutionary flow: tmdx development-support product that has not yet completed texas instruments internal qualification testing. tmds fully qualified development-support product. tmx and tmp devices and tmdx development-support tools are shipped against the following disclaimer: "developmental product is intended for internal evaluation purposes." tms devices and tmds development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti's standard warranty applies. submit documentation feedback device overview 81
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com predictions show that prototype devices (tmx or tmp) have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. ti device nomenclature also includes a suffix with the device family name. this suffix indicates the package type (for example, zut), the temperature range (for example, "blank" is the commercial temperature range), and the device speed range in megahertz (for example, "blank" is the default [594-mhz dsp, 297-mhz arm9]). figure 3-8 provides a legend for reading the complete device name for any tms320dm646x dmsoc platform member. figure 3-8. device nomenclature 82 device overview submit documentation feedback prefix tms 320 dm6467 zut tmx = experimental devicetms = qualified device device family 320 = tms320? dsp family package type (a) zut = 529-pin plastic bga, with pb-free soldered balls [green] c64x+? dsp: dm6467 device a. bga = ball grid array device speed range ( ) blank= 594-mhz dsp, 297-mhz arm9 [default] 7 = 729-mhz dsp, 364.5-mhz arm9 temperature range a a silicon revision: blank = revision 1.0 a = revision 1.1 c = revision 3.0 v blank= a = -4 0 c to 85 c, commercial temperature 0 c to 105 c, extended temperature [-594 mhz only] d = -40 c to 85 c, industrial temperature [-729 mhz only] voltage scale adjustment blank= v = smartreflex[-594 mhz only] smartreflex not supported tmxblank = revision 1.1 tms c = revision 3.0
3.9 documentation support 3.9.1 related documentation from texas instruments tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the following documents describe the tms320dm646x digital media system-on-chip (dmsoc). copies of these documents are available on the internet at www.ti.com . tip: enter the literature number in the search box provided at www.ti.com. the current documentation that describes the dm646x dmsoc, related peripherals, and other technical collateral, is available in the c6000 dsp product folder at: www.ti.com/c6000 . spruep8 tms320dm646x dmsoc dsp subsystem reference guide. describes the digital signal processor (dsp) subsystem in the tms320dm646x digital media system-on-chip (dmsoc). spruep9 tms320dm646x dmsoc arm subsystem reference guide. describes the arm subsystem in the tms320dm646x digital media system-on-chip (dmsoc). the arm subsystem is designed to give the arm926ej-s (arm9) master control of the device. in general, the arm is responsible for configuration and control of the device; including the dsp subsystem and a majority of the peripherals and external memories. sprueq0 tms320dm646x dmsoc peripherals overview reference guide. provides an overview and briefly describes the peripherals available on the tms320dm646x digital media system-on-chip (dmsoc). spraa84 tms320c64x to tms320c64x+ cpu migration guide. describes migrating from the texas instruments tms320c64x digital signal processor (dsp) to the tms320c64x+ dsp. the objective of this document is to indicate differences between the two cores. functionality in the devices that is identical is not included. spru732 tms320c64x/c64x+ dsp cpu and instruction set reference guide. describes the cpu architecture, pipeline, instruction set, and interrupts for the tms320c64x and tms320c64x+ digital signal processors (dsps) of the tms320c6000 dsp family. the c64x/c64x+ dsp generation comprises fixed-point devices in the c6000 dsp platform. the c64x+ dsp is an enhancement of the c64x dsp with added functionality and an expanded instruction set. spru871 tms320c64x+ dsp megamodule reference guide. describes the tms320c64x+ digital signal processor (dsp) megamodule. included is a discussion on the internal direct memory access (idma) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache. spraav0 understanding ti's pcb routing rule-based ddr timing specification application report this application report describes the way the ddr high-speed timing requirements are now going to be communicated to system designers. the system designer uses this information to evaluate whether timing specifications are met and can be expected to operate reliably. spraaz2 enabling smartreflex on the tms320dm6467 application report this application report describes the basic concepts of smartreflex? technology implemented in the dm6467 device. the goal for implementing this technology and the expected benefits are detailed, and a reference design of the smartreflex feature is introduced. submit documentation feedback device overview 83
4 device configurations 4.1 system module registers tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the system module includes status and control registers for configuration of the device.brief descriptions of the various registers are shown in table 4-1 . system module registers required for device configurations are discussed in the following sections. table 4-1. system module register memory map hex address range register acronym description 0x01c4 0000 pinmux0 pin multiplexing control 0 (see section 4.7.2.1 , pinmux0 register). 0x01c4 0004 pinmux1 pin multiplexing control 1 (see section 4.7.2.2 , pinmux1 register). 0x01c4 0008 dspbootaddr dsp boot address. decoded by bootloader software for host boots. (see section 4.4.2.1 , dspbootaddr register.) 0x01c4 000c suspsrc emulator suspend source (see section 4.7.3.13 , emulation control). 0x01c4 0010 bootstat boot status (see section 4.4.2.2 , bootstat register). 0x01c4 0014 bootcfg device boot configuration (see section 4.4.2.3 , bootcfg register). 0x01c4 0018 smtreflex smartreflex status (see figure 7-7 , smtreflex status register). [voltage scale adjustment (v) parts only] 0x01c4 001c - 0x01c4 0020 ? reserved 0x01c4 0024 armboot arm926 boot control (see section 4.4.2.4 , armboot register). 0x01c4 0028 jtagid device id number [see section 7.29.1 , jtag id (jtagid) register description(s)]. 0x01c4 002c ? reserved 0x01c4 0030 hpictl hpi control (see section 4.6.2.1 , hpictl register). 0x01c4 0034 usbctl usb control (see section 4.6.2.2 , usbctl register). 0x01c4 0038 vidclkctl video clock control (see section 4.3.2.1 , video clock control). 0x01c4 003c mstpri0 bus master priority control 0 (see section 4.6.1 , switch central resource (scr) bus priorities). 0x01c4 0040 mstpri1 bus master priority control 1 (see section 4.6.1 , switch central resource (scr) bus priorities). 0x01c4 0044 mstpri2 bus master priority control 2 (see section 4.6.1 , switch central resource (scr) bus priorities). 0x01c4 0048 vdd3p3v_pwdn v dd 3.3-v i/o powerdown control (see section 4.2 , power considerations). 0x01c4 004c ? reserved 0x01c4 0050 tsifctl tsif control register (see section 4.3.2.2 , tsif control). 0x01c4 0054 pwmctl pwm control (see section 4.6.2.3 , pwm (trigger source) control register). 0x01c4 0058 edmatccfg edma tc configuration (see section 4.6.2.4 , edmatccfg register). 0x01c4 005c clkctl oscillator and output clock control (see section 4.3.3 , clock and oscillator control). 0x01c4 0060 dspint arm to dsp interrupt status (see section 4.7.3.12 , arm/dsp communications interrupts). 0x01c4 0064 dspintset arm to dsp interrupt set (see section 4.7.3.12 , arm/dsp communications interrupts). 0x01c4 0068 dspintclr arm to dsp interrupt clear (see section 4.7.3.12 , arm/dsp communications interrupts). 0x01c4 006c vsclkdis video and tsif clock disable (see section 4.3.2.3 , video and tsif clock disable). 0x01c4 0070 armint dsp to arm interrupt status (see section 4.7.3.12 , arm/dsp communications interrupts). 0x01c4 0074 armintset dsp to arm interrupt set (see section 4.7.3.12 , arm/dsp communications interrupts). device configurations 84 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 4-1. system module register memory map (continued) hex address range register acronym description 0x01c4 0078 armintclr dsp to arm interrupt clear (see section 4.7.3.12 , arm/dsp communications interrupts). 0x01c4 007c armwait arm memory wait state control (see section 4.4.2.5 , armwait register). 0x01c4 0080 - 0x01c4 03ff ? reserved submit documentation feedback device configurations 85
4.2 power considerations tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the dm6467 provides several means of managing power consumption. as described in the section 7.3.4 , dm6467 power and clock domains, the dm6467 has one single power domain?the ?always on? power domain. within this power domain, the dm6467 utilizes local clock gating via the power and sleep controller (psc) to achieve power savings. for more details on the psc, see section 7.3.5 , power and sleep controller (psc) and the tms320dm646x dmsoc arm subsystem reference guide (literature number spruep9 ). some of the dm6467 peripherals support additional power saving features. for more details on power saving features supported, see the peripheral-specific reference guides [listed/linked in the tms320dm646x dmsoc peripherals overview reference guide (literature number sprueq0 ). most dm6467 3.3-v i/os can be powered-down to reduce power consumption. the vdd3p3v_pwdn register in the system module (see figure 4-1 ) is used to selectively power down unused 3.3-v i/o pins. note: to save power, all other i/o buffers are powered down by default. before using these pins, the user must program the vdd3p3v_pwdn register to power up the corresponding i/o buffers. for a list of multiplexed pins on the device and the pin mux group each pin belongs to, see section 4.7.3 , pin multiplexing details. note: the vdd3p3v_pwdn register only controls the power to the i/o buffers. the power and sleep controller (psc) determines the clock/power state of the peripheral. 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved usbv clkout rsv spi vlynq reserved gmii mii mcasp1 mcasp0 pcihpi1 pcihpi0 r-000 r/w-1 r/w-0 r-0 r/w-1 r/w-1 r-00 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gpio wdtim tim23 tim01 pwm1 pwm0 ur2fc ur2dat ur1fc ur1dat ur0mdm ur0df vpif3 vpif2 vpif1 vpif0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 r/w-1 r/w-1 legend: r/w = read/write; r = read only; - n = value after reset figure 4-1. vdd3p3v_pwdn register [0x01c4 0048] device configurations 86 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 4-2. vdd3p3v_pwdn register bit descriptions bit name description 31:29 reserved reserved. read returns "0". usb_drvvbus powerdown control. 0 = i/o cells powered up. 28 usbv 1 = i/o cells powered down. this bit controls the usb_drvvbus/gp[22] pin. clkout0 powerdown control. 27 clkout this bit controls the clkout0 pin. 26 rsv reserved. read returns "0". spi powerdown control. 25 spi this bit controls the six spi interface pins: spi_clk, spi_en, spi_cs0, spi_cs1, spi_somi, and spi_simo. vlynq powerdown control. 24 vlynq this bit controls the ten vlynq interface pins: vlynq_clock, vlynq_scrun, vlynq_txd[3:0], and vlynq_rxd[3:0]. 23:22 reserved reserved. read returns "0". gmii powerdown control. 21 gmii this bit controls the ten pins used by gmii (gigabit) only: rftclk, gmtclk, mtxd[7:4], and mrxd[7:4]. mii powerdown control. 20 mii this bit controls the 17 pins used by (g)mii (10/100/1000) and mdio interfaces: mtclk, mtxd[3:0], mtxen, mcol, mcrs, mrclk, mrxd[3:0], mrxdv, mrxer, mdclk, and mdio. mcasp1 powerdown control. 19 mcasp1 this bit controls the three mcasp1 pins: aclkx1, ahclkx1, and axr1[0]. mcasp0 powerdown control. 18 mcasp0 this bit controls the 12 mcasp0 pins: aclkr0, ahclkr0, afsr0, aclkx0, ahclkx0, afsx0, axr0[3:0], amute0, and amutein0. pci/hpi/emifa/ata powerdown control. this bit controls the 28 pins used by the ata or pci`, hpi, or emifa. these pins include: pci_rst/da2/gp[13]/em_a[22], pci_idsel/hddir/em_r/ w, pci_req/dmarq/gp[11]/ em_cs5, pci_gnt/ dmack/gp[12]/ em_cs4, 17 pcihpi1 pci_cbe1/ ata_cs1/gp[32]/em_a[19], pci_cbe0/ ata_cs0/gp[33]/em_a[18], diow/gp[20]/em_wait4/(rdy4/ bsy4), iordy/gp[21]/em_wait3/(rdy3/ bsy3), dior/gp[19]/em_wait5/(rdy5/ bsy5), da1/gp[16]/em_a[21], da0/gp[17]/em_a[20], intrq/gp[18]/rsv, pci_ad[31:16]/dd[15:0]/hd[31:16]/em_a[15:0] defaults to powered up for nor boot. pci/hpi/emifa powerdown control. this bit controls the 28 pins used by pci, hpi, or emifa but not shared with ata. these pins include: pci_clk/gp[10], pci_devsel/hcntl1/em_ba[1], pci_frame/ hint/em_ba[0], pci_irdy/ hrdy/em_a[17]/(cle), pci_trdy/hhwil/em_a[16]/(ale), 16 pcihpi0 pci_stop/hcntl0/ em_we, pci_serr/ hds1/ em_oe, pci_perr/ hcs/ em_dqm1, pci_par/ has/ em_dqm0, pci_inta/em_wait2/(rdy2/ bsy2), pci_cbe3/hr/ w/ em_cs3, pci_cbe2/ hds2/ em_cs2, pci_ad[15:0]/hd[15:0]/em_d[15:0] defaults to powered up for nor boot. gpio powerdown control. 15 gpio this bit controls the eight gp[7:0] pins. defaults to powered up. wd timer powerdown control. 14 wdtim this bit controls the wd timer pin tout2. timer1 powerdown control. 13 tim23 this bit controls the three timer1 pins tinp1l, tout1l, and tout1u. timer0 powerdown control. 12 tim01 this bit controls the four timer0 pins tinp0l, tinp0u, tout0l, and tout0u. pwm1 powerdown control. 11 pwm1 this bit controls the pwm1/ts1_dout pin. pwm0 powerdown control. 10 pwm0 this bit controls the pwm0/crg0_po/ts1_enao pin. uart2 flow control powerdown control. 9 ur2fc this bit controls the urts2/uirtx2/ts0_pstin/gp[41] and ucts2/usd2/crg0_vcxi/gp[42]/ts1_psto pins. submit documentation feedback device configurations 87
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 4-2. vdd3p3v_pwdn register bit descriptions (continued) bit name description uart2 data powerdown control. 8 ur2dat this bit controls the urxd2/crg1_vcxi/gp[39]/crg0_vcxi and utxd2/urctx2/crg1_po/gp[40]/crg0_po pins. uart1 flow control powerdown control. 7 ur1fc this bit controls the urts1/uirtx1/ts0_waito/gp[25] and ucts1/usd1/ts0_en_waito/gp[26] pins. uart1 data powerdown control. 6 ur1dat this bit controls the urxd1/ts0_din7/gp[23] and utxd1/urctx1/ts0_dout7/gp[24] pins. uart0 modem control powerdown control. 5 ur0mdm this bit controls the udtr0/ts0_enao/gp[36], udsr0/ts0_psto/gp[37], udcd0/ts0_waitin/gp[38], and urin0/gp[8]/ts1_waitin pins. uart0 data and flow control powerdown control. 4 ur0df this bit controls the urxd0/ts1_din, utxd0/urctx0/ts1_pstin, urts0/uirtx0/ts1_en_waito, and ucts0/usd0 pins. vpif msb output powerdown control. 3 vpif3 this bit controls the vp_dout[15:8]/ts1_xx, vp_clkin3/ts1_clko, and vp_clko3/ts0_clko pins. vpif lsb output powerdown control. 2 vpif2 this bit controls the vp_dout[7:0], vp_clkin2, and vp_clko2 pins. (vp_dout[7:0] are boot configuration inputs.) vpif msb input powerdown control. 1 vpif1 this bit controls the vp_din[15:8]/ts0_din[7:0] and vp_clkin1 pins. vpif lsb input powerdown control. 0 vpif0 this bit controls the vp_din[3:0]/ts0_dout[3:0], vp_din[7:4]/ts0_dout[7:4]/ts1_xx, and vp_clkin0 pins. device configurations 88 submit documentation feedback
4.3 clock considerations 4.3.1 clock configurations after device reset 4.3.1.1 device clock frequency 4.3.1.2 module clock state tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 global device and local peripheral clocks are controlled by the pll controllers (pllc1 and pllc2) and the power and sleep controller (psc). in addition, the system module video clock control (vidclkctl), tsif control (tsifctl), and clock and oscillator control (clkctl) registers configure the clock sources to the vpif, tsif, crgen peripherals, and the auxiliary oscillator. the selected video, tsif, and crgen module input clocks are disabled using the system module video source clock disable (vsclkdis) register. note: to ensure glitch-free operation, the clock should be disabled before changing the clock source frequency or muxing via the vidclkctl and tsifctl. after device reset, the user is responsible for programming the pll controllers (pllc1 and pllc2) and the power and sleep controller (psc) to bring the device up to the desired clock frequency and the desired peripheral clock state (clock gating or not). for additional power savings, some of the dm6467 peripherals support clock gating within the peripheral boundary. for more details on clock gating and power saving features supported by a specific peripheral, see the peripheral-specific reference/user's guides [listed/linked in the tms320dm646x dmsoc peripherals overview reference guide (literature number sprueq0 )]. the dm6467 defaults to pll bypass mode. if the rom bootloader is selected (btmode[3:0] 1 0100), the bootloader code programs pllc1 and pllc2. section 4.4.1 , boot modes discusses the different boot modes in more detail. the user must adhere to the various clock requirements when programming the pllc1 and pllc2: pll multiplier and frequency ranges. for more details on pll multiplier and frequency ranges, see section 7.5.1 , pll1 and pll2. the clock and reset state for each of the modules is controlled by the power and sleep controller (psc). table 4-3 shows the default state of each module after a device-level global reset. the dm6467 device has four different module states?enable, disable, syncreset, or swrstdisable. for more information on the definitions of the module states, the psc, and psc programming, see section 7.3.5 , power and sleep controller (psc) and the tms320dm646x dmsoc arm subsystem reference guide (literature number spruep9 ). submit documentation feedback device configurations 89
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 4-3. dm6467 default module states default module state lpsc # module name [psc register mdstatn.state] 0 arm enable dsp c64x+ if dspboot = 0 then, enable and module local reset is asserted (mdstatn.lrst = 0). 1 if dspboot = 1 then, enable and module local reset is deasserted (mdstatn.lrst = 1). 2 hdvicp0 swrstdisable 3 hdvicp1 swrstdisable 4 edmacc swrstdisable 5 edmatc0 swrstdisable 6 edmatc1 swrstdisable 7 edmatc2 swrstdisable 8 edmatc3 swrstdisable 9 usb2.0 swrstdisable 10 ata swrstdisable 11 vlynq swrstdisable 12 hpi swrstdisable 13 pci swrstdisable 14 emac/mdio swrstdisable 15 vdce swrstdisable 16 ? 17 video port (1) swrstdisable 18 tsif0 swrstdisable 19 tsif1 swrstdisable 20 ddr2 memory contoller swrstdisable if btmode[3:0] 1 0100 and dspboot = 0 then, swrstdisable 21 emifa if btmode[3:0] = 0100 or dspboot = 1 then, enable 22 mcasp0 swrstdisable 23 mcasp1 swrstdisable 24 crgen0 swrstdisable 25 crgen1 swrstdisable 26 uart0 swrstdisable 27 uart1 swrstdisable 28 uart2 swrstdisable 29 pwm0 swrstdisable 30 pwm1 swrstdisable 31 i2c swrstdisable 32 spi swrstdisable 33 gpio swrstdisable 34 timer0 swrstdisable 35 timer1 swrstdisable 36 ? 44 reserved reserved 45 arm intc enable (1) the video port module has a total of five clock inputs that can be controlled by the lpsc. one lpsc can support only a maximum of four clocks; therefore, two lpscs are assigned to the video port. both video port lpscs should be controlled together and should be set to the same state. device configurations 90 submit documentation feedback
4.3.2 clock control 4.3.2.1 video clock control register tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 this section describes the following registers: the vpif (video)/tsif clock control and clock disable registers and the clock and oscillator control register. the video clock control (vidclkctl) register allows the user to select/control the clock muxing for the video channels' (i.e., channels 1, 2, and 3) output clock source. 31 16 reserved r-0000 0000 0000 0000 15 14 12 11 10 8 7 5 4 3 0 rsv vch3clk rsv vch2clk reserved vch1clk reserved r-0 r/w-111 r-0 r/w-110 r-000 r/w-1 r-0000 legend: r/w = read/write; r = read only; - n = value after reset figure 4-2. vidclkctl register [0x01c4 0038] table 4-4. vidclkctl register bit descriptions bit name description 31:15 reserved reserved. read returns "0". video channel 3 clock source. this field selects the clock source for the channel 3 output source clock. 000 = crg0_vcxi (external pin) 001 = crg1_vcxi (external pin) 010 = sysclk8 (pllc1) 14:12 vch3clk 011 = auxclk (pllc1) 100 = vp_clkin0 (external pin) 101 = stc_clkin (external pin) 110 = vp_clkin2 (external pin) 111 = vp_clkin3 (external pin) 11 rsv reserved. read returns "0". video channel 2 clock source. this field selects the clock source for the channel 2 output source clock. 000 = crg0_vcxi (external pin) 001 = crg1_vcxi (external pin) 010 = sysclk8 (pllc1) 10:8 vch2clk 011 = auxclk (pllc1) 100 = vp_clkin0 (external pin) 101 = stc_clkin (external pin) 110 = vp_clkin2 (external pin) 111 = reserved 7:5 reserved reserved. read returns "0". video channel 1 clock source. this bit selects the clock source for the channel 1 input clock. 4 vch1clk 0 = vp_clkin0 (external pin) 1 = vp_clkin1 (external pin) 3:0 reserved reserved. read returns "0". submit documentation feedback device configurations 91
4.3.2.2 tsif control tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the tsif control (tsifctl) registers allows the user to select/control the clock muxing for the counter and serial output of tsif1 andthe counter and parallel/serial output for tsif0. 31 16 reserved r-0000 0000 0000 0000 15 14 12 11 8 7 6 4 3 2 0 rsv tsif1_cntclk tsso_clk rsv tsif0_cntclk rsv tspo_clk r-0 r/w-000 r/w-0000 r-0 r/w-000 r-0 r/w-000 legend: r/w = read/write; r = read only; - n = value after reset figure 4-3. tsifctl register [0x01c4 0050] table 4-5. tsifctl register bit descriptions bit name description 31:15 reserved reserved. read returns "0". tsif1 counter clock source. this field selects the clock source for the tsif1 module's counter. 000 = crg1_vcxi (external pin) 001 = stc_clkin (external pin) 010 = auxclk (pllc1 output ? 27 mhz) 14:12 tsif1_cntclk 011 = crg0_vcxi (external pin) 100 = vp_clkin2 (external pin) 101 = vp_clkin3 (external pin) 110 = reserved 111 = reserved tsif1 serial output clock source. this field selects the clock source for the tsif1 output source clock. 0000 = crg1_vcxi (external pin) 0001 = stc_clkin (external pin) 0010 = sysclk6 (pllc1) 0011 = sysclkbp (pllc1) 11:8 tsso_clk 0100 = vp_clkin0 (external pin) 0101 = ts1_clkin (external pin) 0110 = vp_clkin2 (external pin) 0111 = reserved 1000 = crg0_vcxi 1001 = reserved 1xx1 = reserved 7 rsv reserved. read returns "0". tsif0 counter clock source. this field selects the clock source for the tsif0 module's counter. 000 = crg0_vcxi (external pin) 001 = stc_clkin (external pin) 010 = auxclk (pllc1 output ? 27 mhz) 6:4 tsif0_cntclk 011 = crg1_vcxi (external pin) 100 = vp_clkin0 (external pin) 101 = vp_clkin1 (external pin) 110 = reserved 111 = reserved 3 rsv reserved. read returns "0". 92 device configurations submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 4-5. tsifctl register bit descriptions (continued) bit name description tsif0 parallel/serial output clock source. this field selects the clock source for the tsif0 output source clock. 000 = crg0_vcxi (external pin) 001 = stc_clkin (external pin) 010 = sysclk5 (pllc1) 2:0 tspo_clk 011 = sysclkbp (pllc1) 100 = vp_clkin0 (external pin) 101 = vp_clkin1 (external pin) 110 = ts0_clkin (external pin) 111 = crg1_vcxi (external pin) submit documentation feedback device configurations 93
4.3.2.3 video and tsif clock disable tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the video source clock disable (vsclkdis) register allows the user to disable the selected video (vpif), tsif, and crgen module input clocks. note: to ensure glitch-free operation, the clock should be disabled before changing the clock source frequency or muxing via the vidclkctl and tsifctl. 31 16 reserved r-0000 0000 0000 0000 15 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved vid3 vid2 vid1 vid0 tsifcnt1 tsifcnt0 tsiftx1 tsiftx0 tsifrx1 tsifrx0 crg1 crg0 r-0000 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 legend: r/w = read/write; r = read only; - n = value after reset figure 4-4. vsclkdis register [0x01c4 006c] table 4-6. vsclkdis register bit descriptions bit name description 31:12 reserved reserved. read returns "0". vpif channel 3 clock disable. 11 vid3 0 = clock enabled. 1 = clock disabled. vpif channel 2 clock disable. 10 vid2 0 = clock enabled. 1 = clock disabled. vpif channel 1 clock disable. 9 vid1 0 = clock enabled. 1 = clock disabled. vpif channel 0 clock disable. 8 vid0 0 = clock enabled. 1 = clock disabled. tsif1 counter clock disable. 7 tsifcnt1 0 = clock enabled. 1 = clock disabled. tsif0 counter clock disable. 6 tsifcnt0 0 = clock enabled. 1 = clock disabled. tsif1 transmit clock disable. 5 tsiftx1 0 = clock enabled. 1 = clock disabled. tsif0 transmit clock disable. 4 tsiftx0 0 = clock enabled. 1 = clock disabled. tsif1 receive clock disable. 3 tsifrx1 0 = clock enabled. 1 = clock disabled. tsif0 receive clock disable. 2 tsifrx0 0 = clock enabled. 1 = clock disabled. crgen1 clock disable. 1 crg1 0 = clock enabled. 1 = clock disabled. crgen0 clock disable. 0 crg0 0 = clock enabled. 1 = clock disabled. device configurations 94 submit documentation feedback
4.3.3 clock and oscillator control tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the clock and oscillator control (clkctl) register allows the user to disable the osc pwrdwn and pwr disable 31 26 25 24 23 20 19 16 reserved oscpwrdn oscdis reserved clkout r-0000 00 r/w-0 r/w-1 r-0000 r/w-1000 15 12 11 8 7 4 3 0 reserved aud_clk1 reserved aud_clk0 r-0000 r/w-0000 r-0000 r/w-0000 legend: r/w = read/write; r = read only; - n = value after reset figure 4-5. clkctl register [0x01c4 005c] table 4-7. clkctl register bit descriptions bit name description 31:26 reserved reserved. read returns "0". 25 oscpwrdn auxiliary oscillator powerdown. this bit controls the internal bias resistor conection. 0 = internal bias resistor connected (normal operation) 1 = internal bias resistor disconnected (external bias resistor required or clock input used) 24 oscdis auxiliary oscillator disable. this bit disables the oscillator. 0 = oscillator enabled (normal operation). 1 = oscillator disabled (clock input used or no auxiliary clock required). 23:20 reserved reserved. read returns "0". 19:16 clkout clkout0 source. this field selects the clock source for the clkout0 output. 0000 = disabled 0001 = pll1 auxclk 0010 = reserved 0011 = sysclk3 (1) 0100 = sysclk4 0101 = sysclk5 0110 = sysclk6 0111 = reserved 1000 = sysclk8 1001 = sysclk9 1010 = aux_mxi 1011 = reserved 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved 15:12 reserved reserved. read returns "0". (1) the maximum frequency allowed for the clkout0 pin is 148.5 mhz. for the -729 mhz device, in pll mode, do not configure the clkout bits to sysclk3 (0011) because the clkout0 source will exceed the maximum frequency limit allowed for clkout0 pin. for more details on the clkout0 timings, see table 7-15 , switching characteristics over recommended operating conditions for clkout0. submit documentation feedback device configurations 95
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 4-7. clkctl register bit descriptions (continued) bit name description 11:8 aud_clk1 audio_clk1 source. this field selects the clock source for the audio_clk1 output. 0000 = disabled 0001 = pll1 auxclk 0010 = crg0_vcxi 0011 = crg1_vcxi 0100 = vp_clkin0 0101 = vp_clkin1 0110 = vp_clkin2 0111 = vp_clkin3 1000 = aux_mxi 1001 = stc_clkin 1010 = reserved 1011 = reserved 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved 7:4 reserved reserved. read returns "0". 3:0 aud_clk0 audio_clk0 source. this field selects the clock source for the audio_clk0 output. 0000 = disabled 0001 = pll1 auxclk 0010 = crg0_vcxi 0011 = crg1_vcxi 0100 = vp_clkin0 0101 = vp_clkin1 0110 = vp_clkin2 0111 = vp_clkin3 1000 = aux_mxi 1001 = stc_clkin 1010 = reserved 1011 = reserved 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved 96 device configurations submit documentation feedback
4.4 boot sequence 4.4.1 boot modes 4.4.2 boot mode registers 4.4.2.1 dspbootaddr register tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the boot sequence is a process by which the device's memory is loaded with program and data sections, and by which some of the device's internal registers are programmed with predetermined values. the boot sequence is started automatically after each device-level global reset. for more details on device-level global resets, see section 7.7 , reset. there are several methods by which the memory and register initialization can take place. each of these methods is referred to as a boot mode. the boot mode to be used is selected at reset. for more information on the bootmode selections, see section 4.4.1 , boot modes. the device is booted through multiple means?primary bootloaders within internal rom or emifa, and secondary user bootloaders from peripherals or external memories. boot modes, pin configurations, and register configurations required for booting the device, are described in the following subsections. the dm6467 boot modes are determined by these device boot and configuration pins. for information on how these pins are sampled at device reset, see section 7.7.1.2 , latching boot and configuration pins. btmode[3:0] pcien cs2bw dspboot vp_dout7/vadjen the tms320dm646x dmsoc arm can boot either from asynchronous emif/nor flash or from arm rom, as determined by the device boot and configuration pins at reset (btmode[3:0] and pcien). the pcien pin configuration is used to select the default configuration of the emifa/pci/hpi pins at reset. this allows the dm646x dmsoc to be pci-compliant at reset. when pcien = 1, the pci module controls the multiplexed pins with the appropriate pullup/pulldown configuration. for all other bootmodes (non-pci bootmodes), the pcien must be cleared to "0". for a more detailed description of the rom boot modes supported by the dm646x dmsoc, see using the tms320dm646x bootloader application report (literature number spraas0 ). the dspbootaddr, bootcmplt, bootcmd, and bootcfg registers are used to control boot and device configurations. the dspbootaddr register contains the upper 22 bits of the dsp reset vector. 31 10 9 0 bootaddr[21:0] reserved r/w-0100 0010 0010 0000 0000 00 r-00 0000 0000 legend: r/w = read/write; r = read only; - n = value after reset figure 4-6. dspbootaddr register table 4-8. dspbootaddr register bit descriptions bit name description 31:10 bootaddr[21:0] upper 22 bits of the c64x+ dsp boot address. 9:0 reserved reserved submit documentation feedback device configurations 97
4.4.2.2 bootstat register tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the boot status (bootstat) register indicates the status of the device boot process (e.g., boot error, boot complete, or watchdog timer reset). 31 30 20 19 16 wdrst reserved booterr r/w-0 r-000 0000 0000 r-0000 15 1 0 reserved bc r-0000 0000 0000 000 r/w-0 legend: r/w = read/write; r = read only; - n = value after reset figure 4-7. bootstat register table 4-9. bootstat register bit descriptions bit name description watchdog timer reset. 0 = device reset was not a result of a watchdog timer timeout. 1 = device reset was a result of a watchdog timer timeout. 31 wdrst this is a "sticky" bit that can be used to debug wd timeout conditions. the bit is set when a wd timeout occurs (tout2). this bit is reset (to "0") by a por reset only; otherwise it retains its value. it is not cleared by a warm reset or soft reset. the bit may be cleared by writing a "1". 30:20 reserved reserved. read returns "0". boot error. 0000 = no boot error [ default]. 19:16 booterr others = bootloader detected boot error. the exact meaning of the various error codes will be determined by the bootloader software. 15:1 reserved reserved. read returns "0". boot complete. 0 = host has not completed the boot sequence [ default]. 1 = host has completed the boot sequence. 0 bc this bit may be optionally set by a host boot device (such as pci or hpi) to indicate that it has finished loading code. the arm926 can poll this bit to determine whether to continue the boot process. device configurations 98 submit documentation feedback
4.4.2.3 bootcfg register tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the boot configuration (bootcfg) register is a read-only register that indicates the value of the device bootmode and configuration pins latched at the end of reset. during a hard reset ( por or reset pin active [low]), the values of the cfg pins (i.e., btmode[3:0], cs2bw, pcien, dspboot) are propagated through the bootcfg register to the boot controller. when reset or por is de-asserted, the value of the pins is latched. the bootcfg value does not change as a result of a soft reset, instead the value latched at the end of the previous global reset is retained. 31 18 17 16 reserved dsp_bt pcien r-0000 0000 0000 00 r-l r-l 15 13 12 11 9 8 7 4 3 0 reserved vadjen reserved cs2_bw reserved bootmode r-000 r-l r-000 r-l r-0000 r-llll legend: r = read only; l = latched pin value; - n = value after reset figure 4-8. bootcfg register submit documentation feedback device configurations 99
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 4-10. bootcfg register bit descriptions bit name description 31:18 reserved reserved. read returns "0". dsp boot. latched from dspboot input at the rising edge of reset or por. 0 = arm boots c64x+. 1 = c64x+ self-boots. 17 dsp_bt this bit will cause the dsp to be released from reset automatically. the c64x+ will boot from emifa (default dspbootaddr address 0x4220 0000). if bootmode = 0010 or 0011, or pcien = 1, then the c64x+ self-boot will fail since emifa will be disabled. pci enable. latched from pcien input at the rising edge of reset or por. 0 = pci disabled. 16 pcien 1 = pci enabled. pcien = 1 disables the internal pullup and pulldown resistors on the pci pins and configures the pin muxing for pci. 15:13 reserved reserved. read returns "0". votlage adjust enable (smartreflex). latched from vadjen input at the rising edge of reset or por. this pin determines whether gp[6]/cvddadj0 and gp[7]/cvddadj1 function as gpio pins or as 12 vadjen smartreflex control output pins. 0 = smartreflex outputs disabled. gp[6]/cvddadj0 and gp[7]/cvddadj1 pins function as gpio. 1 = smartreflex outputs enabled. gp[6]/cvddadj0 and gp[7]/cvddadj1 pins function as smartreflex control outputs. 11:9 reserved reserved. read returns "0". emifa em_cs2 default bus width. latched from cs2bw input at the rising edge of reset or por. 0 = default to 8-bit operation. 8 cs2_bw 1 = default to 16-bit operation. this bit determines the default bus width of the emifa em_cs2 memory space. this ensures that boot from emifa (arm or dsp) will correctly read the attached memory. 7:4 reserved reserved. read returns "0". boot mode configuration bits. bit values latched from btmode[3:0] at the rising edge of reset or por. 0000 = emulation boot. 0001 = reserved. 0010 = hpi-16 (if pcien = 0). pci without autoinitialization (if pcien = 1). 0011 = hpi-32 (if pcien = 0). pci with autoinitialization (if pcien = 1). 0100 = emifa direct boot (rom/nor) (if pcien = 0; error if pcien = 1 defaults to uart0). 0101 = reserved. 3:0 bootmode 0110 = i2c boot. 0111 = nand flash boot (if pcien = 0; error if pcien = 1 defaults to uart0). 1000 = uart0 boot. 1001 = reserved. 1010 = reserved. 1011 = reserved. 1100 = reserved. 1101 = reserved. 1110 = spi boot. 1111 = reserved. device configurations 100 submit documentation feedback
4.4.2.4 armboot register 4.4.2.5 armwait register tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the arm boot configuration (armboot) register is used to control the arm926 boot. the armboot value does not change as a result of a soft reset, instead the last value written is retained. when rom boot is selected (btmode[3:0] 1 0100), a jump to the internal tcm rom (0x0000 8000) is forced into the first fetched instruction word. the embedded rom boot loader (rbl) code can then perform certain configuration steps, read the bootcfg register to determine the desired boot method, and branch to an appropriate secondary loader utility. if emifa boot is selected (btmode[3:0] = 0100), a jump to the highest branch address (0x0200 0000) is forced into the first fetched instruction word. this must be modified to address 0x4200 0000 in order to map to the emifa. the arm will then continue executing from external memory using the default emifa timings until modified by software. note: that either nor flash or rom must be connected to the first emifa chip select space (em_cs2). the emifa does not support direct execution from nand flash. 31 5 4 3 1 0 reserved addrmod reserved tramboot r-0000 0000 0000 0000 0000 0000 000 r/w-c r-000 r/w-0 legend: r/w = read/write; r = read only; c = clear; - n = value after reset figure 4-9. armboot register table 4-11. armboot register bit descriptions bit name description 31:5 reserved reserved. read returns "0". iahb address modification. 0 = no address modification. 1 = address bit 30 is tied high to modify iahb fetch address to point to emifa. the default value for this bit is determined by the bootmode configuration bits (btmode[3:0]). if btmode[3:0] = 0100 [emifa direct boot (rom/nor)] , then addrmod defaults to "1" so that 4 addrmod instruction fetches from the arm will point to emifa cs2 memory space. for all other btmode[3:0] values, addrmod defaults to "0" because arm will boot from its tcm (rom or ram). the addrmod value is ignored when tramboot is set (1) [address modification is disabled]. after branching into the emifa cs2 space, software should clear this bit as part of the reset routine so that subsequent iahb access addresses are not modified. 3:1 reserved reserved. read returns "0". arm tcm ram boot. 0 = use btmode[3:0] selected boot mode 1 = boot from itcm ram 0 tramboot this is a "sticky" bit that can be used to force the arm926 to boot from itcm ram. on por reset, this bit will be initialized to "0" because tcm ram is not initialized; otherwise, the bit retains the value. after initializing itcm ram, software can set this bit so that subsequent warm reset ( reset) or soft reset will boot from the itcm. the arm wait state control (armwait) register is used to control arm926 accesses to its tcm ram. at normal arm operating frequency, a wait state must be inserted when accessing tcm ram. when the device is operated at low speeds, performance may be increased by removing the wait state. note: tcm rom will always operate with a wait state enabled. 31 1 0 reserved ramwait r-0000 0000 0000 0000 0000 0000 0000 000 r/w-1 legend: r/w = read/write; r = read only; - n = value after reset figure 4-10. armwait register submit documentation feedback device configurations 101
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 4-12. armwait register bit descriptions bit name description 31:1 reserved reserved. read returns "0". arm tcm ram wait state configuration. 0 ramwait 0 = tcm ram wait state disabled. 1 = tcm ram wait state enabled. device configurations 102 submit documentation feedback
4.5 configurations at reset 4.5.1 device and peripheral configurations at device reset tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 some device configurations are determined at reset. the following subsections give more details. table 3-5 , boot terminal functions lists the device boot and configuration pins that are latched at device reset for configuring basic device settings for proper device operation. table 4-13 , summarizes the device boot and configuration pins, and the device functions that they affect. table 4-13. default functions affected by device boot and configuration pins device boot and boot selected pin mux control global setting peripheral setting configuration pins bootmode[3:0] boot mode pinmux0/pinmux1 i/o pin power: psc/peripherals: registers: based on based on based on bootmode[3:0], the bootmode[3:0], the bootmode[3:0], the bootloader code programs bootloader code programs bootloader code programs vdd3p3v_pwdn register the psc to put pinmux0 and pinmux1 to power up the i/o pins boot-related peripheral(s) registers to select the required for boot. in the enable state, and appropriate pin functions programs the peripheral(s) required for boot. for boot operation. cs2bw emifa direct boot mode pinmux0.hpien = 0 ? the default width of the pinmux0.pcien = 0 first emifa chip select pinmuix0.ataen = 0 space (cs2) is determined by the cs2bw value. if cs2bw = 0, the space defaults to 8-bits wide. if cs2bw = 1, it defaults to 16-bits wide. this allows the arm to make full use of the width of the attached memory device when booting from emifa. pcien (1) host boot: pinmux0.pcien: ? psc/peripheral pcien selects the type of sets this field to control (applicable to host boot host boot the pci pin muxing in . only): (hpi boot or pci boot) (1) (2) based on the host boot type (pci or hpi), the bootloader code programs the psc to put the corresponding peripheral in the enable state, and programs the peripheral for boot operation. (1) software can modify all pinmux0 and pinmux1 bit fields from their defaults. (2) in addition to pin mux control, pcien also affects the internal pullup/down resistors of the pci capable pins. when pcien = 0, internal pullup/down resistors on the pci capable pins are enabled. when pcien = 1, internal pullup/down resistors on the pci capable pins are disabled to be compliant to the pci local bus specification revision 2.3. submit documentation feedback device configurations 103
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 4-13. default functions affected by device boot and configuration pins (continued) device boot and boot selected pin mux control global setting peripheral setting configuration pins dspboot bit = 0, dsp is booted by ? ? note: that either nor the arm flash or rom must be bit =1, dsp boots self connected to the first from emifa emifa chip select space (cs2). the emifa does not support direct execution from nand flash. code within the emifa memory should execute a branch to the actual emifa address and then disable the instruction address modification logic (by clearing the addrmod bit in the armboot register of the system module). vadjen ? at reset, the input state is ? ? sampled to determine whether the smartreflex control outputs are enbabled or disabled. 0 = smartreflex outputs disabled. gp[6]/cvddadj0 and gp[7]/cvddadj1 pins function as gpio. 1 = smartreflex outputs enabled. gp[6]/cvddadj0 and gp[7]/cvddadj1 pins function as smartreflex control outputs. cvddadj0 ? once the smartreflex ? cvddadj1 control outputs are enabled (vadjen = 1 at reset), these pins control the adjustable core power supply to output the cv dd voltage for the device: 00 = 1.2 v (-594v, -594av devcies only) 11 = 1.05 v (-594v, -594av devcies only) all other settings reserved. for proper device operation, external pullup/pulldown resistors may be required on these device boot and configuration pins. for discussion situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. note: all dm6467 device configuration inputs (bootmode[3:0], cs2bw, pcien, and dspboot) are multiplexed with other functional pins. these pins function as device boot and configuration pins only during device reset. the user must take care of any potential data contention in the system. to help avoid system data contention, the dm6467 puts these configuration pins into a high-impedance state (hi-z) when device reset (reset or por) is asserted, and continues to hold them in a high-impedance state until the internal global reset is removed; at which point, the default peripheral (vpif) will now control these pins. device configurations 104 submit documentation feedback
4.5.2 emifa cs2 bus width (cs2bw) 4.5.3 pci enable (pcien) 4.5.4 dspboot tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 all of the device boot and configuration pin settings are captured in the corresponding bit fields in the bootcfg register (see section 4.4.2.3 ). the following subsections provide more details on the device configurations determined at device reset: cs2bw, pcien, and dspboot. the default width of the first emifa chip select space (cs2) is determined by the cs2bw value. if cs2bw = 0, the space defaults to 8-bits wide. if cs2bw = 1, it defaults to 16-bits wide. this allows the arm to make full use of the width of the attached memory device when booting from emifa. note: cs2bw only selects the default bus width. the emifa bus width may be changed at any time via software by accessing the appropriate emifa control register. the default width affects only the first chip select space (cs2). all other chip select spaces default to 8-bits wide and must be modified using the appropriate emifa control register if 16-bit operation is desired. the pcien configuration pin determines if the pci peripheral is used on this device. if pcien = 1 indicating the pci is used, then the pci multiplexed pins default to pci functions, and the pins? corresponding internal pullup/pulldown resistors are disabled. if pcien = 0 indicating the pci is not used, then the pci muxed pins default to non-pci functions (e.g., emifa or hpi pin functions), and the pins? corresponding internal pullup/pulldown resistors are enabled. the pcien setting is captured and stored in the bootcfg.pcien bit field, and also in the pinmux0.pcien bit field. the dspboot input determines dsp operation at reset. for most applications, the arm is the master device and controls the reset and boot of the dsp. under this scenario (dspboot = 0), the dsp will remain disabled (held in reset) after reset. the arm is responsible for releasing dsp from reset. before releasing dsp from reset, the arm must transfer a valid dsp boot image to program memory accessible by the dsp (dsp memory, emifa or ddr2), and configure the dsp boot address in dspbootaddr register (in system module) from which the dsp will begin execution. when dspboot = 1, the dsp will boot itself. under this scenario, dsp will be released from reset without arm intervention. the dsp boot address is set to an emifa address 0x4220 0000h. dsp will begin execution with instruction (l1p) cache enabled. note: the dspboot operation is overridden when arm hpi or pci boot is selected (btmode[3:0] = 001x). this is because arm hpi/pci boot selection will force the hpien or pcien bit in pinmux0 to ?1?. this enables uhpi/pci functions on the emifa control and data pins and prevents the dsp from using emifa. dspboot is treated as "0" internally when btmode[3:0] = 001x, regardless of the value at the configuration pin (the actual pin value should still be latched in the bootcfg register of the system module). submit documentation feedback device configurations 105
4.6 configurations after reset 4.6.1 switch central resource (scr) bus priorities tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the following sections provide details on configuring the device after reset. multiplexed pin are configured both at and after reset. section 4.5.1 , device and peripheral configurations at device reset, discusses multiplexed pin control at reset. for more details on multiplexed pins control after reset, see section 4.7 , multiplexed pin configurations. prioritization within the switched central resource (scr) is programmable for each master. the register bit fields and default priority levels for dm6467 bus masters are shown in table 4-14 , dm6467 default bus master priorities. the priority levels should be tuned to obtain the best system performance for a particular application. lower values indicate higher priority. for most masters, their priority values are programmed at the system level by configuring the mstpri0, mstpri1, and mstpri2 registers. details on the mstpri0/1/2 registers are shown in figure 4-11 , figure 4-12 , and figure 4-13 . table 4-14. dm6467 default bus master priorities priority bit field bus master default priority level vp0p vpif capture 1 (mstpri2 register) vp1p vpif display 1 (mstpri2 register) tsif0p tsif0 1 (mstpri2 register) tsif1p tsif1 1 (mstpri2 register) edmatc0p edmatc0 2 (mstpri2 register) edmatc1p edmatc1 2 (mstpri2 register) edmatc2p edmatc2 2 (mstpri2 register) edmatc3p edmatc3 2 (mstpri2 register) hdvicp0p hdvicp0 (cfg) (1) 3 (mstpri0 register) hdvicp1p hdvicp1 (cfg) (1) 3 (mstpri0 register) arminstp arm926 (inst) 4 (mstpri0 register) armdatap arm926 (data) 4 (mstpri0 register) dspdmap c64x+ dsp (dma) 4 (mstpri0 register) dspcfgp c64x+ dsp (cfg) (1) 4 (mstpri0 register) vdcep vdce 4 (mstpri1 register) emacp emac 5 (mstpri1 register) usbp usb2.0 5 (mstpri1 register) atap ata 5 (mstpri1 register) vlynqp vlynq 5 (mstpri1 register) pcip pci 6 (mstpri1 register) hpip hpi 6 (mstpri1 register) (1) the c64x+ dsp (cfg), hdvicp0 (cfg), and hdvicp1 (cfg) priority values are not actually used by the dmsoc infrastructure ? which gives equal weight round-robin priority to accesses from these three masters. therefore, the priority settings for these three masters in the mstpri0 register have no effect. 106 device configurations submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 31 23 22 20 19 18 16 reserved rsv hdvicp1p (1) hdvicp0p (1) r-0000 0000 0 r/w-011 r-0 r/w-011 15 14 12 11 8 7 6 4 3 2 0 rsv dspdmap rsv dspcfgp (1) rsv armdatap rsv arminstp r-0 r/w-100 r-0 r/w-100 r-0 r/w-100 r-0 r/w-100 legend: r/w = read/write; r = read only; - n = value after reset figure 4-11. mstpri0 register [0x01c4 003c] (1) the dspcfgp, hdvicp0p, and hdvicp1p priority values are not actually used by the infrastructure, which gives equal weight round-robin priority to accesses from this master; therefore, the settings have no effect. table 4-15. mstpri0 register bit descriptions bit name description 31:23 reserved reserved. read returns "0". 22:20 hdvicp1p (1) hdvicp1 master port priority in system infrastructure. read returns "011". writes have no effect. 19 rsv reserved. read returns "0". 18:16 hdvicp0p (1) hdvicp0 master port priority in system infrastructure. read returns "011". writes have no effect. 15 rsv reserved. read returns "0". 14:12 dspdmap dspdma master port priority in system infrastructure. 000 = priority 0 ( highest) 100 = priority 4 [ default] 001 = priority 1 101 = priority 5 010 = priority 2 110 = priority 6 011 = priority 3 111 = priority 7 ( lowest) 11 rsv reserved. read returns "0". 10:8 dspcfgp (1) dspcfg master port priority in system infrastructure. read returns "100". writes have no effect. 7 rsv reserved. read returns "0". 6:4 armdatap arm data master port priority in system infrastructure. 000 = priority 0 ( highest) 100 = priority 4 [ default] 001 = priority 1 101 = priority 5 010 = priority 2 110 = priority 6 011 = priority 3 111 = priority 7 ( lowest) 3 rsv reserved. read returns "0". 2:0 arminstp arm inst master port priority in system infrastructure. 000 = priority 0 ( highest) 100 = priority 4 [ default] 001 = priority 1 101 = priority 5 010 = priority 2 110 = priority 6 011 = priority 3 111 = priority 7 ( lowest) (1) the priorities for these masters are fixed at their default values. writing alternate values to these fields has no effect.. submit documentation feedback device configurations 107
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com 31 30 28 27 26 24 23 22 20 19 18 16 rsv vdcep rsv pcip rsv hpip rsv vlynqp r-0 r/w-100 r-0 r/w-110 r-0 r/w-110 r-0 r/w-101 15 14 12 11 10 8 7 3 2 0 rsv atap rsv usbp reserved emacp r-0 r/w-101 r-0 r/w-101 r-0000 0 r/w-101 legend: r/w = read/write; r = read only; - n = value after reset figure 4-12. mstpri1 register [0x01c4 0040] table 4-16. mstpri1 register bit descriptions bit name description 31 rsv reserved. read returns "0". 30:28 vdcep vdce master port priority in system infrastructure. 000 = priority 0 ( highest) 100 = priority 4 [ default] 001 = priority 1 101 = priority 5 010 = priority 2 110 = priority 6 011 = priority 3 111 = priority 7 ( lowest) 27 rsv reserved. read returns "0". 26:24 pcip pci master port priority in system infrastructure. 000 = priority 0 ( highest) 100 = priority 4 001 = priority 1 101 = priority 5 010 = priority 2 110 = priority 6 [ default] 011 = priority 3 111 = priority 7 ( lowest) 23 rsv reserved. read returns "0". hpi master port priority in system infrastructure. same priority 0?7 selection as above. 22:20 hpip "110" = priority 6 [ default]. 19 rsv reserved. read returns "0". vlynq master port priority in system infrastructure. same priority 0?7 selection as above. 18:16 vlynqp "110" = priority 6 [ default]. 15 rsv reserved. read returns "0". ata master port priority in system infrastructure. same priority 0?7 selection as above. 14:12 atap "101" = priority 5 [ default]. 11 rsv reserved. read returns "0". usb master port priority in system infrastructure. same priority 0?7 selection as above. 10:8 usbp "101" = priority 5 [ default]. 7:3 reserved reserved. read returns "0". emac master port priority in system infrastructure. same priority 0?7 selection as above. 2:0 emacp "101" = priority 5 [ default]. device configurations 108 submit documentation feedback
4.6.2 peripheral selection after device reset tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 31 30 28 27 26 24 23 22 20 19 18 16 rsv tsif1p rsv tsif0p rsv vp1p rsv vp0p r-0 r/w-001 r-0 r/w-001 r-0 r/w-001 r-0 r/w-001 15 14 12 11 10 8 7 6 4 3 2 0 rsv edmatc3p rsv edmatc2p rsv edmatc1p rsv edmatc0p r-0 r/w-010 r-0 r/w-010 r-0 r/w-010 r-0 r/w-010 legend: r/w = read/write; r = read only; - n = value after reset figure 4-13. mstpri2 register table 4-17. mstpri2 register bit descriptions bit name description 31 rsv reserved. read returns "0". 30:28 tsif1p tsif1 master port priority in system infrastructure. 000 = priority 0 ( highest) 100 = priority 4 001 = priority 1 [ default] 101 = priority 5 010 = priority 2 110 = priority 6 011 = priority 3 111 = priority 7 ( lowest) 27 rsv reserved. read returns "0". 26:24 tsif0p tsif0 master port priority in system infrastructure. 000 = priority 0 ( highest) 100 = priority 4 001 = priority 1 [ default] 101 = priority 5 010 = priority 2 110 = priority 6 011 = priority 3 111 = priority 7 ( lowest) 23 rsv reserved. read returns "0". vpif display master port priority in system infrastructure. same priority 0?7 selection as above. 22:20 vp1p "001" = priority 1 [ default]. 19 rsv reserved. read returns "0". vpif capture master port priority in system infrastructure. same priority 0?7 selection as above. 18:16 vp0p "001" = priority 1 [ default]. 15 rsv reserved. read returns "0". edmatc3 master port priority in system infrastructure. same priority 0?7 selection as above. 14:12 edmatc3p "010" = priority 2 [ default]. 11 rsv reserved. read returns "0". edmatc2 master port priority in system infrastructure. same priority 0?7 selection as above. 10:8 edmatc2p "010" = priority 2 [ default]. 7 rsv reserved. read returns "0". edmatc1 master port priority in system infrastructure. same priority 0?7 selection as above. 6:4 edmatc1p "010" = priority 2 [ default]. 3 rsv reserved. read returns "0". edmatc0 master port priority in system infrastructure. same priority 0?7 selection as above. 2:0 edmatc0p "010" = priority 2 [ default]. after device reset, most peripheral configurations are done within the peripheral?s registers. this section discusses some additional peripheral controls in the system module. for information on multiplexed pin controls that determine what peripheral pins are brought out to the pins, see section 4.7 , multiplexed pin configurations. submit documentation feedback device configurations 109
4.6.2.1 hpictl register 4.6.2.2 usbctl register tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the hpi control register (hpictl) [0x01c4 0030] controls write access to hpi control and address registers and determines the host time-out value. hpictl is not reset by a soft reset so that the hpi width will remain correctly configured. figure 4-14 and table 4-18 describe in detail the hpictl register. 31 18 17 16 reserved reserved r-0000 0000 0000 00 r/w-00 15 14 10 9 8 7 0 width reserved ctlmode addmode timout r/w-0 r-000 00 r/w-0 r/w-0 r/w-1000 0000 legend: r/w = read/write; r = read only; - n = value after reset figure 4-14. hpictl register [0x01c4 0030] table 4-18. hpictl register bit descriptions bit name description 31:18 reserved reserved. read-only, writes have no effect. 17:16 reserved reserved. for proper device operation, the user should only write "0" to these bits (default). hpi data width. 0 = half-width (16-bit) data bus 15 width 1 = full-width (32-bit) data bus this bit value must be determined before releasing the uhpi from reset to ensure correct uhpi operation. 14:10 reserved reserved. read-only, writes have no effect. hpic register write access. 9 ctlmode 0 = host 1 = dmsoc (if addmode = 1) hpia register write access. 8 addmode 0 = host 1 = dmsoc host burst write timeout value. when the hpi time-out counter reaches the value programmed here, the hpi write fifo content is 7:0 timout flushed. for more details on the time-out counter and its use in write bursting, see the tms320dm646x dmsoc host port interface (hpi) user's guide (literature number sprues1). the usb interface control register (usbctl) [0x01c4 0034] is described in figure 4-15 and table 4-19 . 31 19 18 17 16 reserved datapol vbusval usbid r-0000 0000 0000 0 r/w-1 r/w-0 r/w-0 15 9 8 7 5 4 3 1 0 phy phy phy reserved reserved reserved clkgd pllon pdwn r-0000 000 r-0 r-000 r/w-0 r-000 r/w-1 legend: r/w = read/write; r = read only; - n = value after reset figure 4-15. usbctl register [0x01c4 0034] 110 device configurations submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 4-19. usbctl register bit descriptions bit name description 31:19 reserved reserved. read returns "0". usb data polarity. 18 datapol 0 = inverted data. 1 = normal data polarity [default]. vbus sense control. 17 vbusval 0 = disabled [default]. 1 = session starts. usb mode. 16 usbid 0 = host [default]. 1 = peripheral. 15:9 reserved reserved. read returns "0". usb phy power and clock good. 8 phyclkgd 0 = phy power is not ramped or pll is not locked [default]. 1 = phy power is good and pll is locked. 7:5 reserved reserved. read returns "0". usb phy pll suspend override. 4 phypllon 0 = normal pll operation [default]. 1 = override pll suspend state. 3:1 reserved reserved. read returns "0". usb phy power-down control. 0 phypdwn 0 = phy powered on. 1 = phy power off [default]. submit documentation feedback device configurations 111
4.6.2.3 pwmctl (trigger source) control register tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the pwm control register (pwmctl) [0x01c4 0054] chip-level connections of both pwm0 and pwm1. figure 4-16 and table 4-20 describe in detail the pwmctl register. 31 16 reserved r-0000 0000 0000 0000 15 8 7 4 3 0 reserved pwm11trg pwm0trg r-0000 0000 r/w-1111 r/w-1111 legend: r/w = read/write; r = read only; - n = value after reset figure 4-16. pwmctl register [0x01c4 0054] table 4-20. pwmctl register bit descriptions bit name description 31:8 reserved reserved. read-only, writes have no effect. 7:4 pwm1trg pwm1 trigger source 0000 = gp[0] 1000 = vpif vertical interrupt 0 0001 = gp[1] 1001 = vpif vertical interrupt 1 0010 = gp[2] 1010 = vpif vertical interrupt 2 0011 = gp[3] 1011 = vpif vertical interrupt 3 0100 = gp[4] 1100 = reserved 0101 = gp[5] 1101 = reserved 0110 = gp[6] 1110 = reserved 0111 = gp[7] 1111 = reserved pwm0 trigger source 3:0 pwm0trg same selection as above. device configurations 112 submit documentation feedback
4.6.2.4 edmatccfg register tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the edma transfer controller default burst size configuration register (edmatccfg) [0x01c4 0058] configures the default burst size (dbs) for edma tc0, edma tc1, edma tc2, and edma tc3. figure 4-17 and table 4-21 describe in detail the edmatccfg register. for more information on the correct usage of dbs, see the tms320dm646x dmsoc enhanced direct memory access (edma) controller user's guide (literature number sprueq5 ). 31 16 reserved r-0000 0000 0000 0000 15 8 7 6 5 4 3 2 1 0 reserved tc3dbs tc2dbs tc1dbs tc0dbs r-0000 0000 r/w-01 r/w-01 r/w-01 r/w-01 legend: r/w = read/write; r = read only; - n = value after reset figure 4-17. edma transfer controller default burst size configuration register (edmatccfg) [0x01c4 0058] table 4-21. edmatccfg register bit descriptions bit name description 31:8 reserved reserved. read-only, writes have no effect. edma tc3 default burst size. 00 = 16 byte 01 = 32 byte [default] 7:6 tc3dbs 10 = 64 byte 11 = reserved tc3 fifo size is 256 bytes, regardless of default burst size setting. edma tc2 default burst size. 00 = 16 byte 01 = 32 byte [default] 5:4 tc2dbs 10 = 64 byte 11 = reserved tc2 fifo size is 256 bytes, regardless of default burst size setting. edma tc1 default burst size. 00 = 16 byte 01 = 32 byte [default] 3:2 tc1dbs 10 = 64 byte 11 = reserved tc1 fifo size is 256 bytes, regardless of default burst size setting. edma tc0 default burst size. 00 = 16 byte 01 = 32 byte [default] 1:0 tc0dbs 10 = 64 byte 11 = reserved tc0 fifo size is 256 bytes, regardless of default burst size setting. submit documentation feedback device configurations 113
4.7 multiplexed pin configurations 4.7.1 pin muxing selection at reset 4.7.2 pin muxing selection after reset 4.7.2.1 pinmux0 register description tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com dm6467 makes extensive use of pin multiplexing to accommodate a large number of peripheral function in the smallest possible package, providing the ultimate flexibility for end applications. the pin multiplex registers pinmux0 and pinmux1 in the system module are responsiblie for controlling all pin multiplexing functions on the dm6467. the default setting of some of the pinmux0 and pinmux1 bit fields are configured by configuration pins latched at reset (see section 4.5.1 , device and peripheral configurations at device reset). after reset, software may program the pinmux0 and pinmux1 registers to switch pin functionalities. the following peripherals have multiplexed pins: vpif, tsif0, tsif1, crgen0, crgen1, emifa, pci, hpi, ata, pwm0, pwm1, uart0, uart1, uart2, audio clock selector, the usb usb_drvvbus pin, and gpio. this section summarizes pin mux selection at reset. the configuration pins cs2bw, pcien, and vadjen, latched at device reset, determine the default pin muxing. for more details on the default pin muxing at reset, see section 4.5 , configurations at reset. the pinmux0 and pinmux1 registers in the system module allow software to select the pin functions. some pin functions require a combination of pinmux0/pinmux1 bit fields. for more details on the combination of the pinmux bit fields that control each muxed pin, see section 4.7.3 , pin multiplexing details. this section only provides an overview of the pinmux0 and pinmux1 registers. for more detailed discussion on how to program each pin mux block, see section 4.7.3 , pin multiplexing details. the pin multiplexing 0 register controls the pin function in the emifa/ata/hpi/pci, tsif0, tsif1, crgen, block. the pinmux0 register format is shown in figure 4-18 and the bit field descriptions are given in table 4-22 . some muxed pins are controlled by more than one pinmux bit field. for the combination of the pinmux bit fields that control each muxed pin, see section 4.7.3 , pin multiplexing details. for more information on the block pin muxing and pin-by-pin muxing control, see specific block muxing section (for example, for crgen pin mux control, see section 4.7.3.7 , crgen signal muxing). 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 vbusdis stcck audck1 audck0 rsv crgmux tssomux tssimux tspomux tspimux r/w-0 r/w-0 r/w-0 r/w-0 r-0 r/w-000 r/w-00 r/w-00 r/w-00 r/w-00 15 6 5 4 3 2 1 0 reserved rsv reserved pcien hpien ataen r-0000 0000 00 r/w-0 r-0 r/w-l r/w-0 r/w-0 legend: r/w = read/write; r = read only; - n = value after reset figure 4-18. pinmux0 register [0x01c4 0000] device configurations 114 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 4-22. pinmux0 register bit descriptions bit name description this bit disables usb_drvvbus output. 31 vbusdis 0 = usb_drvvbus function selected. 1 = gp[22] function selected. this bit enables stc source clock input. 30 stcck 0 = gp[4] function selected. 1 = stc_clkin function selected. this bit enables audio_clk1 output. 29 audck1 0 = gp[2] function selected. 1 = audio_clk1 function selected. this bit enables audio_clk0 output. 28 audck0 0 = gp[3] function selected. 1 = audio_clk0 function selected. 27 rsv reserved. read returns "0". crgen pin mux control (see section 4.7.3.7 , crgen signal muxing). 000 = no crgen signals enabled. 001 = crgen1 selection enabled (muxed with uart2 data). 010 = reserved (no crgen signals enabled). 26:24 crgmux 011 = reserved (no crgen signals enabled). 100 = crgen0 selection enabled (muxed with ucts2 and pwm0). 101 = crgen0 and crgen1 selection enabled. 110 = crgen0 selection enabled (muxed with uart2 data). 111 = reserved (no crgen signals enabled). tsif1 serial output pin mux control (see (1) , tsso signal muxing). 0x = no ts1 output signals enabled. 23:22 tssomux 10 = ts1 output selection enabled (muxed on vp_dout pins). 11 = ts1 output selection enabled (muxed on urin0, ucts2, pwm0, and pwm1 pins). tsif1 serial input pin mux control (see section 4.7.3.5 , tsif1 input signal muxing). 00 = no ts1 input signals enabled. 21:20 tssimux 01 = ts1 input selection enabled (muxed on uart0 pins). 10 = ts1 input selection enabled (muxed on vp_dout pins). 11 = ts1 input selection enabled (muxed on vp_din pins). tsif0 parallel/serial output pin mux control (see section 4.7.3.4 , tsif0 output signal muxing). 0x = no ts0 output signals enabled. 19:18 tspomux 10 = ts0 parallel output muxing enabled (muxed with vp_din pins). 11 = ts0 serial output muxing enabled (muxed ts0_dout7 with utxd1). tsif0 parallel/serial input pin mux control (see section 4.7.3.3 , tsif0 input signal muxing). 0x = no ts0 signals enabled. 17:16 tspimux 10 = ts0 parallel input muxing enabled (muxed with vp_din pins). 11 = ts0 serial input muxing enabled (muxed ts0_din7 with urxd1). 15:6 reserved reserved. read returns "0". reserved. read returns "0". note: for proper device operation, when writing to this bit, only a "0" 5 reserved should be written. 4:3 reserved reserved. read returns "0". pci function enable (see section 4.7.3.1 , pci, hpi, emifa and ata pin muxing). 2 pcien default value is determined by pcien boot configuration pin. 1 hpien hpi function enable (see section 4.7.3.1 , pci, hpi, emifa and ata pin muxing). 0 ataen ata function enable (see section 4.7.3.1 , pci, hpi, emifa and ata pin muxing). (1) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 4.8.1 , pullup/pulldown resistors. submit documentation feedback device configurations 115
4.7.2.2 pinmux1 register description tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the pin multiplexing 1 register controls the pin function in the uart0, uart1, and uart2 blocks. the pinmux1 register format is shown in figure 4-19 and the bit field descriptions are given in table 4-23 . some muxed pins are controlled by more than one pinmux bit field. for the combination of the pinmux bit fields that control each muxed pin, see section 4.7.3 , pin multiplexing details. for the pin-by-pin muxing control of the uart0, uart1, and uart2 blocks, see section 4.7.3.8 , uart0 pin muxing; section 4.7.3.9 , uart1 pin muxing; and section 4.7.3.10 , uart2 pin muxing. 31 16 reserved r-0000 0000 0000 0000 15 6 5 4 3 2 1 0 reserved uart2ctl uart1ctl uart0ctl r-0000 0000 00 r/w-00 r/w-00 r/w-00 legend: r/w = read/write; r = read only; - n = value after reset figure 4-19. pinmux1 register table 4-23. pinmux1 register bit descriptions bit name description 31:6 reserved reserved. read returns "0". uart2 pin configuration (see section 4.7.3.10 , uart2 pin muxing). 00 = uart function with flow control. 01 = uart function without flow control. 5:4 uart2ctl 10 = irda/cir function. 11 = gpio function. (individual pin functions may be overridden by tspimux, crgen0, and crgen1 values.) uart1 pin configuration (see section 4.7.3.9 , uart1 pin muxing). 00 = uart function with flow control. 01 = uart function without flow control. 3:2 uart1ctl 10 = irda/cir function. 11 = gpio function. (individual pin functions may be overridden by tspimux and tspomux values.) uart0 pin configuration (see section 4.7.3.8 , uart0 pin muxing). 00 = uart function with modem control. 1:0 uart0ctl 01 = uart function without modem control. 1x = irda/cir function. (individual pin functions may be overridden by tspomux value.) device configurations 116 submit documentation feedback
4.7.3 pin multiplexing details 4.7.3.1 pci, hpi, emifa, and ata pin muxing tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 this section discusses how to program each pin mux register to select the desired peripheral functions and pin muxing. see the individual pin mux sections for pin muxing details for a specific muxed pin. for details on pinmux0 and pinmux1 registers, see section 4.7.2 , pin muxing selection after reset. the pci, hpi, emifa, and ata signal muxing is determined by the value of the pcien, hpien, and ataen bit fields in the pinmux0 register. for more details on the actual pin functions, see table 4-24 and table 4-25 . table 4-24. pcien, hpien, and ataen encoding pcien hpien ataen pin functions 0 0 0 emifa 0 0 1 emifa (nand) and ata 0 1 0 hpi (32-bit) 0 1 1 hpi (16-bit) and ata 1 x x pci (1) (1) in pci mode (pcien = 1), the internal pullups/pulldowns (ipus/ipds) are disabled on all pci pins and it is recommended to have external pullup resistors on the pci_rsv[5:0] pins. see table 4-25 for the actual pci pin functions and any associated footnotes. table 4-25. pci, hpi, emifa, and ata pin muxing pin functions (with pcien, hpien, ataen values) 1xx (1) 010 011 000 001 pci_clk gp[10] gp[10] gp[10] gp[10] pci_idsel ? hddir em_r/ w hddir pci_devsel hcntl1 hcntl1 em_ba[1] em_ba[1] pci_frame hint hint em_ba[0] em_ba[0] pci_irdy hrdy hrdy em_a[17] em_a[17]/(cle) pci_trdy hhwil hhwil em_a[16] em_a[16]/(ale) pci_stop hcntl0 hcntl0 em_we em_we pci_serr hds1 hds1 em_oe em_oe pci_perr hcs hcs em_dqm1 em_dqm1 pci_par has has em_dqm0 em_dqm0 pci_inta ? ? em_wait2 em_wait2/(rdy2/ bsy2) pci_req gp[11] dmarq em_cs5 dmarq pci_gnt gp[12] dack em_cs4 dack pci_cbe3 hr/ w hr/ w em_cs3 em_cs3 pci_cbe2 hds2 hds2 em_cs2 em_cs2 pci_cbe1 gp[32] ata_cs1 em_a[19] ata_cs1 pci_cbe0 gp[33] ata_cs0 em_a[18] ata_cs0 pci_ad31 hd31 dd15 em_a[15] dd15 pci_ad30 hd30 dd14 em_a[14] dd14 pci_ad29 hd29 dd13 em_a[13] dd13 pci_ad28 hd28 dd12 em_a[12] dd12 pci_ad27 hd27 dd11 em_a[11] dd11 pci_ad26 hd26 dd10 em_a[10] dd10 (1) in pci mode (pcien = 1), the internal pullups/pulldowns (ipus/ipds) are disabled on all pci pins and it is recommended to have external pullup resistors on the pci_rsv[5:0] pins. for more detailed information on external pullup/pulldown resistors, see section 4.8.1 , pullup/pulldown resistors. submit documentation feedback device configurations 117
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 4-25. pci, hpi, emifa, and ata pin muxing (continued) pin functions (with pcien, hpien, ataen values) 1xx (1) 010 011 000 001 pci_ad25 hd25 dd9 em_a[9] dd9 pci_ad24 hd24 dd8 em_a[8] dd8 pci_ad23 hd23 dd7 em_a[7] dd7 pci_ad22 hd22 dd6 em_a[6] dd6 pci_ad21 hd21 dd5 em_a[5] dd5 pci_ad20 hd20 dd4 em_a[4] dd4 pci_ad19 hd19 dd3 em_a[3] dd3 pci_ad18 hd18 dd2 em_a[2] dd2 pci_ad17 hd17 dd1 em_a[1] dd1 pci_ad16 hd16 dd0 em_a[0] dd0 pci_ad15 hd15 hd15 em_d15 em_d15 pci_ad14 hd14 hd14 em_d14 em_d14 pci_ad13 hd13 hd13 em_d13 em_d13 pci_ad12 hd12 hd12 em_d12 em_d12 pci_ad11 hd11 hd11 em_d11 em_d11 pci_ad10 hd10 hd10 em_d10 em_d10 pci_ad9 hd9 hd9 em_d9 em_d9 pci_ad8 hd8 hd8 em_d8 em_d8 pci_ad7 hd7 hd7 em_d7 em_d7 pci_ad6 hd6 hd6 em_d6 em_d6 pci_ad5 hd5 hd5 em_d5 em_d5 pci_ad4 hd4 hd4 em_d4 em_d4 pci_ad3 hd3 hd3 em_d3 em_d3 pci_ad2 hd2 hd2 em_d2 em_d2 pci_ad1 hd1 hd1 em_d1 em_d1 pci_ad0 hd0 hd0 em_d0 em_d0 pci_rst gp[13] da2 em_a[22] da2 pci_rsv0 (1) gp[16] da1 em_a[21] da1 pci_rsv1 (1) gp[17] da0 em_a[20] da0 pci_rsv2 (1) gp[18] intrq em_rsv0 intrq pci_rsv3 (1) gp[19] dior em_wait5/(rdy5/ bsy5) dior pci_rsv4 (1) gp[20] diow em_wait4/(rdy4/ bsy4) diow pci_rsv5 (1) gp[21] iordy em_wait3/(rdy3/ bsy3) iordy device configurations 118 submit documentation feedback
4.7.3.2 pwm signal muxing tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the two pwm outputs will be configured as pwm pin functions by default. the pwm functions may be overridden by the settings of various pinmux0 bit fields as shown in table 4-26 and table 4-27 . table 4-26. pwm0 pin muxing pin function crgmux 1 10x crgmux = 10x tssomux = 11 tssomux 1 11 tssomux 1 11 pwm0 crg0_po ts1_enao table 4-27. pwm1 pin muxing pin function tssomux 1 11 tssomux = 11 pwm1 ts1_dout submit documentation feedback device configurations 119
4.7.3.3 tsif0 input signal muxing (serial/parallel) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the tsif 0 (ts0) input signals have muxing options for both parallel or serial operation as configured by the tpsimux bits as shown in table 4-28 . table 4-28. tsif0 input pin muxing tspimux = 0x tspimux = 10 tspimux = 11 (no tsif0 signals enabled) (parallel) (serial) ts0_clkin ts0_clkin ts0_clkin vp_din15_vsync ts0_din7 vp_din15_vsync vp_din14_hsync ts0_din6 vp_din14_hsync vp_din13_field ts0_din5 vp_din13_field vp_din12 ts0_din4 vp_din12 vp_din11 ts0_din3 vp_din11 vp_din10 ts0_din2 vp_din10 vp_din9 ts0_din1 vp_din9 vp_din8 ts0_din0 vp_din8 urxd1 (1) urxd1 (1) ts0_din7 utxd1 (1) utxd1 (1) (see table 4-22 ?tspomux bit field) (also see table 4-35 ) urts1 (1) ts0_waito ts0_waito ucts1 (1) ts0_en_waito ts0_en_waito urts2 (2) ts0_pstin ts0_pstin (1) function is determined by uart1ctl bit field value in the pinmux0 register. (2) function is determined by uart2ctl bit field value in the pinmux0 register. 120 device configurations submit documentation feedback
4.7.3.4 tsif0 output signal muxing (serial/parallel) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the tsif 0 (ts0) output signals have muxing options for both parallel or serial operation as configured by the tpsomux bits as shown in table 4-29 . table 4-29. tsif0 output pin muxing tspomux = 0x tspomux = 10 tspomux = 11 (parallel) (serial) uart0ctl = 00 uart0ctl 1 00 vp_clko3 vp_clko3 ts0_clko ts0_clko vp_din7 (1) vp_din7 (1) ts0_dout7 (1) vp_din7 (1) vp_din6 (1) vp_din6 (1) ts0_dout6 (1) vp_din6 (1) vp_din5 (1) vp_din5 (1) ts0_dout5 (1) vp_din5 (1) vp_din4 (1) vp_din4 (1) ts0_dout4 (1) vp_din4 (1) vp_din3 (1) vp_din3 (1) ts0_dout3 (1) vp_din3 (1) vp_din2 (1) vp_din2 (1) ts0_dout2 (1) vp_din2 (1) vp_din1 (1) vp_din1 (1) ts0_dout1 (1) vp_din1 (1) vp_din0 (1) vp_din0 (1) ts0_dout0 (1) vp_din0 (1) udtr0 gp[36] ts0_enao ts0_enao udsr0 gp[37] ts0_psto ts0_psto udcd0 gp[38] ts0_waitin ts0_waitin urin0 gp[8] gp[8] gp[8] urxd1 (2) urxd1 (2) urxd1 (2) (see table 4-22 ?tspimux bit field) (also see table 4-35 ) utxd1 (2) utxd1 (2) utxd1 (2) ts0_dout7 (1) function will be overridden by tsif1 signals if tssimux = 11 (pinmux0 register). (2) function is determined by uart1ctl bit field value in the pinmux1 register. submit documentation feedback device configurations 121
4.7.3.5 tsif1 input signal muxing (serial only) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the tsif 1 (ts1) input signals have three muxing options as configured by the tssimux bits as shown in table 4-30 . when tssimux = 11, the tssi data and control pins are muxed onto the vp_din[7:4] regardless of the value of tspomux. table 4-30. tsif1 serial input pin muxing tssimux = 00 tssimux = 01 tssimux = 10 tssimux = 11 ts1_clkin ts1_clkin ts1_clkin ts1_clkin vp_din7/ts0_dout7 (1) vp_din7/ts0_dout7 (1) vp_din7/ts0_dout7 (1) ts1_din vp_din6/ts0_dout6 (1) vp_din6/ts0_dout6 (1) vp_din6/ts0_dout6 (1) ts1_pstin vp_din5/ts0_dout5 (1) vp_din5/ts0_dout5 (1) vp_din5/ts0_dout5 (1) ts1_en_waito vp_din4/ts0_dout4 (1) vp_din4/ts0_dout4 (1) vp_din4/ts0_dout4 (1) ts1_waito vp_din3/ts0_dout3 (1) vp_din3/ts0_dout3 (1) vp_din3/ts0_dout3 (1) hi-z vp_din2/ts0_dout2 (1) vp_din2/ts0_dout2 (1) vp_din2/ts0_dout2 (1) hi-z vp_din1/ts0_dout1 (1) vp_din1/ts0_dout1 (1) vp_din1/ts0_dout1 (1) hi-z vp_din0/ts0_dout0 (1) vp_din0/ts0_dout0 (1) vp_din0/ts0_dout0 (1) hi-z vp_dout15 vp_dout15 ts1_din vp_dout15 vp_dout14 vp_dout14 ts1_pstin vp_dout14 vp_dout13 vp_dout13 ts1_en_waito vp_dout13 vp_dout12 vp_dout12 ts1_waito vp_dout12 urxd0 (2) ts1_din urxd0 (2) urxd0 (2) utxd0 (2) ts1_pstin utxd0 (2) utxd0 (2) urts0 (2) ts1_en_waito urts0 (2) urts0 (2) ucts0 (2) usd0 ucts0 (2) ucts0 (2) (1) function will be determined by tspomux bit field value in the pinmux0 register. (2) function is determined by uart0ctl bit field value in the pinmux1 register 122 device configurations submit documentation feedback
4.7.3.6 tsif1 output signal muxing (serial only) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the tsif 1 (ts1) output signals are muxed with either the vp_dout signals or uart0, uart2, and pwm signals as selected by tssomux (pinmux0 register). the ts1 output pin muxing is shown in table 4-31 . table 4-31. tsif1 serial output pin muxing pin function tssomux = 0x tssomux = 10 tssomux = 11 vp_clkin3 ts1_clko ts1_clko vp_dout11 ts1_dout vp_dout11 vp_dout10 ts1_psto vp_dout10 vp_dout9 ts1_enao vp_dout9 vp_dout8 ts1_waitin vp_dout8 urin0/gp[8] (1) urin0/gp[8] (1) ts1_waitin ucts2/gp[42]/crg0_vcxi (2) ucts2/gp[42]/crg0_vcxi (2) ts1_psto pwm0/crg0_po (3) pwm0/crg0_po (3) ts1_enao pwm1 pwm1 ts1_dout (1) function will be determined by uart0ctl bit field value in the pinmux1 register. (2) function will be determined by uart2ctl and crgmux bit field values in the pinmux1 and pinmux0 registers, respectively. (3) function will be determined by crgmux bit field value in the pinmux0 register. submit documentation feedback device configurations 123
4.7.3.7 crgen signal muxing tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the two crgen modules share pins with uart2 and pwm0. the crgen function is selected using the crgmux bit field in the pinmux0 register (see table 4-32 ). table 4-32. crg pin muxing pin function crgmux = 001 crgmux = 100 crgmux = 101 crgmux = 110 crgmux = other pwm0 (1) crg0_po (1) crg0_po (1) pwm0 (1) pwm0 (1) ucts2 (2) (3) crg0_vcxi (3) crg0_vcxi (3) ucts2 (2) (3) ucts2 (2) (3) crg1_vcxi urxd2 (2) crg1_vcxi crg0_vcxi urxd2 (2) crg1_po utxd2 (2) crg1_po crg0_po utxd2 (2) (1) function will be overridden by ts1_enao pin if tssomux = 11 (pinmux0 register). (2) function is determined by uart2ctl bit field value in the pinmux1 register. (3) function will be overridden by ts1_psto if tssomux = 11 (pinmux0 register). 124 device configurations submit documentation feedback
4.7.3.8 uart0 pin muxing tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the uart0 module can operate as either a uart or irda/cir interface. the uart0 pin muxing is controlled by the uart0ctl bit field in the pinmux1 register and the tspomux, tssimux, and tssomux bit fields in the pinmux0 register. muxing options are shown in table 4-33 and table 4-34 . when uart operation is selected, uart0ctl must be set to either ?00? for uart with modem signals or ?01? for uart without modem signals. when irda/cir operation is selected, uart0ctl must be set to ?1x? to use the irda/cir signals and the modem signal become gpios. a tspomux setting of ?1x? overrides the modem control mux settings. uart0 can still be used as a uart without modem control or in irda/cir mode based on the uart0ctl bit field value. a tssimux setting of ?01? overrides the uart data and flow control settings and prevents uart0 from being used. the uart0 modem control pins may be used as either tsif 0 output or gpio pins based on the tspomux and uart0ctl settings. a tssomux setting of ?11? overrides the rin function with the ts1_waitin function. table 4-33. uart0 pin muxing?part 1 pin functions utxd0/ urts0/ tssimux[1] tssimux[0] uart0ctl[1] uart0ctl[0] urxd0/ ucts0/ urctx0/ uirtx0/ ts1_din usd0 ts1_pstin ts1_en_waito 0 0 0 0 urxd0 utxd0 urts0 ucts0 0 0 0 1 urxd0 utxd0 urts0 ucts0 0 0 1 0 urxd0 urctx0 uirtx0 usd0 0 0 1 1 urxd0 urctx0 uirtx0 usd0 0 1 0 0 ts1_din ts1_pstin ts1_en_waito ? 0 1 0 1 ts1_din ts1_pstin ts1_en_waito ? 0 1 1 0 ts1_din ts1_pstin ts1_en_waito ? 0 1 1 1 ts1_din ts1_pstin ts1_en_waito ? 1 x 0 0 urxd0 utxd0 urts0 ucts0 1 x 0 1 urxd0 utxd0 urts0 ucts0 1 x 1 0 urxd0 urctx0 uirtx0 usd0 1 x 1 1 urxd0 urctx0 uirtx0 usd0 submit documentation feedback device configurations 125
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 4-34. uart0 pin muxing?part 2 pin functions udtr0/ udsr0/ udcd0/ urin0/ tssomux[1] tssomux[0] tspomux[1] tspomux[0] uart0ctl[1] uart0ctl[0] ts0_enao/ ts0_psto/ ts0_waitin/ gp[8]/ gp[36] gp[37] gp[38] ts1_waitin 0 x 0 x 0 0 udtr0 udsr0 udcd0 urin0 0 x 0 x 0 1 gp[36] gp[37] gp[38] gp[8] 0 x 0 x 1 0 gp[36] gp[37] gp[38] gp[8] 0 x 0 x 1 1 gp[36] gp[37] gp[38] gp[8] 0 x 1 x 0 0 ts0_enao ts0_psto ts0_waitin gp[8] 0 x 1 x 0 1 ts0_enao ts0_psto ts0_waitin gp[8] 0 x 1 x 1 0 ts0_enao ts0_psto ts0_waitin gp[8] 0 x 1 x 1 1 ts0_enao ts0_psto ts0_waitin gp[8] 1 0 0 x 0 0 udtr0 udsr0 udcd0 urin0 1 0 0 x 0 1 gp[36] gp[37] gp[38] gp[8] 1 0 0 x 1 0 gp[36] gp[37] gp[38] gp[8] 1 0 0 x 1 1 gp[36] gp[37] gp[38] gp[8] 1 0 1 x 0 0 ts0_enao ts0_psto ts0_waitin gp[8] 1 0 1 x 0 1 ts0_enao ts0_psto ts0_waitin gp[8] 1 0 1 x 1 0 ts0_enao ts0_psto ts0_waitin gp[8] 1 0 1 x 1 1 ts0_enao ts0_psto ts0_waitin gp[8] 1 1 0 x 0 0 udtr0 udsr0 udcd0 ts1_waitin 1 1 0 x 0 1 gp[36] gp[37] gp[38] ts1_waitin 1 1 0 x 1 0 gp[36] gp[37] gp[38] ts1_waitin 1 1 0 x 1 1 gp[36] gp[37] gp[38] ts1_waitin 1 1 1 x 0 0 ts0_enao ts0_psto ts0_waitin ts1_waitin 1 1 1 x 0 1 ts0_enao ts0_psto ts0_waitin ts1_waitin 1 1 1 x 1 0 ts0_enao ts0_psto ts0_waitin ts1_waitin 1 1 1 x 1 1 ts0_enao ts0_psto ts0_waitin ts1_waitin device configurations 126 submit documentation feedback
4.7.3.9 uart1 pin muxing tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the uart1 module can operate as either a uart or irda/cir interface. the uart1 pin muxing options are shown in table 4-35 . when uart operation is selected, uart1ctl must be set to either ?00? for uart with flow control or ?01? for uart without flow control signals. when irda/cir operation is selected, uart1ctl must be set to ?10? to use the irda/cir signals. if uart1 is unused, then setting uart1ctl = 11 muxes gpio function onto all the pins. the uart1 pin functions may be overridden based on the settings of tspimux and tspomux table 4-35. uart1 pin muxing pin functions utxd1/ urts1/ ucts1/ urxd1/ tspimux[1] tspimux[0] tspomux[1] tspomux[0] uart1ctl[1] uart1ctl[0] urctx1/ uirtx1/ usd1/ ts0_din7/ ts0_dout7/ ts0_waito/ ts0_en_waito/ gp[23] gp[24] gp[25] gp[26] 0 x 0 x 0 0 urxd1 utxd1 urts1 ucts1 0 x 0 x 0 1 urxd1 utxd1 gp[25] gp[26] 0 x 0 x 1 0 urxd1 urctx1 uirtx1 usd1 0 x 0 x 1 1 gp[23] gp[24] gp[25] gp[26] 0 x 1 0 0 0 urxd1 utxd1 urts1 ucts1 0 x 1 0 0 1 urxd1 utxd1 gp[25] gp[26] 0 x 1 0 1 0 urxd1 urctx1 uirtx1 usd1 0 x 1 0 1 1 gp[23] gp[24] gp[25] gp[26] 0 x 1 1 0 0 urxd1 ts0_dout7 urts1 ucts1 0 x 1 1 0 1 urxd1 ts0_dout7 gp[25] gp[26] 0 x 1 1 1 0 urxd1 ts0_dout7 uirtx1 usd1 0 x 1 1 1 1 gp[23] ts0_dout7 gp[25] gp[26] 1 0 0 x 0 x urxd1 utxd1 ts0_waito ts0_en_waito 1 0 0 x 1 0 urxd1 urctx1 ts0_waito ts0_en_waito 1 0 0 x 1 1 gp[23] gp[24] ts0_waito ts0_en_waito 1 0 1 0 0 x urxd1 utxd1 ts0_waito ts0_en_waito 1 0 1 0 1 0 urxd1 urctx1 ts0_waito ts0_en_waito 1 0 1 0 1 1 gp[23] gp[24] ts0_waito ts0_en_waito 1 0 1 1 0 x urxd1 ts0_dout7 ts0_waito ts0_en_waito 1 0 1 1 1 0 urxd1 ts0_dout7 ts0_waito ts0_en_waito 1 0 1 1 1 1 gp[23] ts0_dout7 ts0_waito ts0_en_waito 1 1 0 x 0 x ts0_din7 utxd1 ts0_waito ts0_en_waito 1 1 0 x 1 0 ts0_din7 urctx1 ts0_waito ts0_en_waito 1 1 0 x 1 1 ts0_din7 gp[24] ts0_waito ts0_en_waito 1 1 1 0 0 x ts0_din7 utxd1 ts0_waito ts0_en_waito 1 1 1 0 1 0 ts0_din7 urctx1 ts0_waito ts0_en_waito 1 1 1 0 1 1 ts0_din7 gp[24] ts0_waito ts0_en_waito 1 1 1 1 x x ts0_din7 ts0_dout7 ts0_waito ts0_en_waito submit documentation feedback device configurations 127
4.7.3.10 uart2 pin muxing tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the uart2 module can operate as either a uart or irda/cir interface. the uart2 pin muxing options are shown in table 4-36 through table 4-38 . when uart operation is selected, uart2ctl must be set to either ?00? for uart with flow control or ?01? for uart without flow control signals. when irda/cir operation is selected, uart2ctl must be set to ?10? to use the irda/cir signals. if uart2 is unused, then setting uart2ctl = 11 muxes gpio function onto all the pins. the uart2 pin functions may be overridden based on the settings of tspimux, crgmux, and tssomux. table 4-36. uart2 data pin muxing pin functions utxd2/ urxd2/ urctx2/ crgmux[2] crgmux[1] crgmux[0] uart2ctl[1] uart2ctl[0] crg1_vcxi/ crg1_po/ gp[39]/ gp[40]/ crg0_vcxi crg0_po 0 0 0 0 0 urxd2 utxd2 0 0 0 0 1 urxd2 utxd2 0 0 0 1 0 urxd2 urctx2 0 0 0 1 1 gp[39] gp[40] 0 0 1 0 0 crg1_vcxi crg1_po 0 0 1 0 1 crg1_vcxi crg1_po 0 0 1 1 0 crg1_vcxi crg1_po 0 0 1 1 1 crg1_vcxi crg1_po 0 1 0 0 0 urxd2 utxd2 0 1 0 0 1 urxd2 utxd2 0 1 0 1 0 urxd2 urctx2 0 1 0 1 1 gp[39] gp[40] 0 1 1 0 0 urxd2 utxd2 0 1 1 0 1 urxd2 utxd2 0 1 1 1 0 urxd2 urctx2 0 1 1 1 1 gp[39] gp[40] 1 0 0 0 0 urxd2 utxd2 1 0 0 0 1 urxd2 utxd2 1 0 0 1 0 urxd2 urctx2 1 0 0 1 1 gp[39] gp[40] 1 0 1 0 0 crg1_vcxi crg1_po 1 0 1 0 1 crg1_vcxi crg1_po 1 0 1 1 0 crg1_vcxi crg1_po 1 0 1 1 1 crg1_vcxi crg1_po 1 1 0 0 0 crg0_vcxi crg0_po 1 1 0 0 1 crg0_vcxi crg0_po 1 1 0 1 0 crg0_vcxi crg0_po 1 1 0 1 1 crg0_vcxi crg0_po 1 1 1 0 0 urxd2 utxd2 1 1 1 0 1 urxd2 utxd2 1 1 1 1 0 urxd2 urctx2 1 1 1 1 1 gp[39] gp[40] device configurations 128 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 4-37. uart2 ready-to-send ( urts2) pin muxing pin function urts2/ tspimux[1] tspimux[0] uart2ctl[1] uart2ctl[0] uirtx2/ ts0_pstin/ gp[41] 0 x 0 0 urts2 0 x 0 1 gp[41] 0 x 1 0 uirtx2 0 x 1 1 gp[41] 1 x x x ts0_pstin table 4-38. uart2 clear-to-send ( ucts2) pin muxing pin pin tssomux 1 11 tssomux = 11 function function ucts2/ ucts2/ usd2/ usd2/ crgmux[2] crgmux[1] crgmux[0] uart2ctl[1] uart2ctl[0] crg0_vcxi/ crgmux[2] crgmux[1] crgmux[0] uart2ctl[1] uart2ctl[0] crg0_vcxi/ gp[42]/ gp[42]/ ts1_psto ts1_psto 0 0 0 0 0 ucts2 0 0 0 0 0 ts1_psto 0 0 0 0 1 gp[42] 0 0 0 0 1 ts1_psto 0 0 0 1 0 usd2 0 0 0 1 0 ts1_psto 0 0 0 1 1 gp[42] 0 0 0 1 1 ts1_psto 0 0 1 0 0 ucts2 0 0 1 0 0 ts1_psto 0 0 1 0 1 gp[42] 0 0 1 0 1 ts1_psto 0 0 1 1 0 usd2 0 0 1 1 0 ts1_psto 0 0 1 1 1 gp[42] 0 0 1 1 1 ts1_psto 0 1 0 0 0 ucts2 0 1 0 0 0 ts1_psto 0 1 0 0 1 gp[42] 0 1 0 0 1 ts1_psto 0 1 0 1 0 usd2 0 1 0 1 0 ts1_psto 0 1 0 1 1 gp[42] 0 1 0 1 1 ts1_psto 0 1 1 0 0 ucts2 0 1 1 0 0 ts1_psto 0 1 1 0 1 gp[42] 0 1 1 0 1 ts1_psto 0 1 1 1 0 usd2 0 1 1 1 0 ts1_psto 0 1 1 1 1 gp[42] 0 1 1 1 1 ts1_psto 1 0 0 0 0 crg0_vcxi 1 0 0 0 0 ts1_psto 1 0 0 0 1 crg0_vcxi 1 0 0 0 1 ts1_psto 1 0 0 1 0 crg0_vcxi 1 0 0 1 0 ts1_psto 1 0 0 1 1 crg0_vcxi 1 0 0 1 1 ts1_psto 1 0 1 0 0 crg0_vcxi 1 0 1 0 0 ts1_psto 1 0 1 0 1 crg0_vcxi 1 0 1 0 1 ts1_psto 1 0 1 1 0 crg0_vcxi 1 0 1 1 0 ts1_psto 1 0 1 1 1 crg0_vcxi 1 0 1 1 1 ts1_psto 1 1 0 0 0 ucts2 1 1 0 0 0 ts1_psto 1 1 0 0 1 gp[42] 1 1 0 0 1 ts1_psto 1 1 0 1 0 usd2 1 1 0 1 0 ts1_psto 1 1 0 1 1 gp[42] 1 1 0 1 1 ts1_psto 1 1 1 0 0 ucts2 1 1 1 0 0 ts1_psto 1 1 1 0 1 gp[42] 1 1 1 0 1 ts1_psto 1 1 1 1 0 usd2 1 1 1 1 0 ts1_psto 1 1 1 1 1 gp[42] 1 1 1 1 1 ts1_psto submit documentation feedback device configurations 129
4.7.3.11 smartreflex and gpio pin muxing tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the smartreflex and gpio signal muxing is determined by the value of the vadjen pin (ab7) at reset. for more details on the actual pin functions, see table 4-39 . for more detailed information on smartreflex, see section 7.3.6 , smartreflex (voltage scaling). table 4-39. smartreflex and gpio pin muxing pin function vadjen = 0 vadjen = 1 smartreflex disabled. smartreflexcontrol outputs enabled gp[7] and gp[6] cvddadj[1:0] 00 = device operates at 1.2 v core power supply only (-594v, -594av devcies only) 11 = device can operate at 1.05 v core power supply (-594v, -594av devcies only) all other settings reserved. the value of these pins is also stored in the smartreflex status register (smtreflex) [see figure 7-7 ]. device configurations 130 submit documentation feedback
4.7.3.12 arm/dsp communications interrupts tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the system module includes registers for generating interrupts between the arm and dsp. the dspint register shows the status of the arm-to-dsp interrupts. the dspint register format is shown in figure 4-20 . table 4-40 describes the register bit fields. the arm may generate an interrupt to the dsp by setting one of the four intdsp[3:0] bits or by setting the intnmi bit in the dspintset pseudo-register (see figure 4-21 ). the interrupt set bit then self-clears and the corresponding intdsp[3:0] or intnmi bit in the dspint status register (see figure 4-20 ) is automatically set to indicate that the interrupt was generated. after servicing the interrupt, the dsp clears the status bit by writing ?1? to the corresponding bit in the dspintclr register (see figure 4-22 ). the arm may poll the status bit to determine when the dsp has completed the interrupt service. the dsp may generate an interrupt to the arm in the same manner using the armintset and armintclr registers shown/described in figure 4-24 , table 4-44 , and figure 4-25 , table 4-45 , respectively. the dsp can then view the status of the dsp-to-arm interrupts via the armint register shown/described in figure 4-23 and table 4-43 . 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved r-0000 0000 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved intnmi reserved intdsp3 intdsp2 intdsp1 intdsp0 r-0000 000 r-0 r-0000 r-0 r-0 r-0 r-0 legend: r = read only, n = value at reset figure 4-20. dspint status register [0x01c4 0060] table 4-40. dspint status register bit descriptions (1) bit name description 31:9 reserved reserved. a read returns 0. 8 intnmi dsp nmi status 7:4 reserved reserved. a read returns 0. 3 intdsp3 arm-to-dsp int3 status 2 intdsp2 arm-to-dsp int2 status 1 intdsp1 arm-to-dsp int1 status 0 intdsp0 arm-to-dsp int0 status (1) read only, writes have no effect. submit documentation feedback device configurations 131
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved r-0000 0000 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved intnmi reserved intdsp3 intdsp2 intdsp1 intdsp0 r-0000 000 r/w-0 r-0000 r/w-0 r/w-0 r/w-0 r/w-0 legend: r = read, w = write, n = value at reset figure 4-21. dspintset register [0x01c4 0064] table 4-41. dspintset register bit descriptions bit name description 31:9 reserved reserved. a read returns 0. 8 intnmi dsp nmi set (1) 7:4 reserved reserved. a read returns 0. 3 intdsp3 arm-to-dsp int3 set (1) 2 intdsp2 arm-to-dsp int2 set (1) 1 intdsp1 arm-to-dsp int1 set (1) 0 intdsp0 arm-to-dsp int0 set (1) (1) writing a '1' generates the interrupt and sets the corresponding bit in the dspint status register. the register bit automatically clears to a value of '0'. writing a '0' has no effect. this register always reads as '0'. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved r-0000 0000 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved intnmi reserved intdsp3 intdsp2 intdsp1 intdsp0 r-0000 000 r/w-0 r-0000 r/w-0 r/w-0 r/w-0 r/w-0 legend: r = read, w = write, n = value at reset figure 4-22. dspintclr register [0x01c4 0068] table 4-42. dspintclr register bit descriptions bit name description 31:9 reserved reserved. a read returns 0. 8 intnmi dsp nmi clear (1) 7:4 reserved reserved. a read returns 0. 3 intdsp3 arm-to-dsp int3 clear (1) 2 intdsp2 arm-to-dsp int2 clear (1) 1 intdsp1 arm-to-dsp int1 clear (1) 0 intdsp0 arm-to-dsp int0 clear (1) (1) writing a '1' clears the corresponding bit in the dspint status register. the register bit automatically clears to a value of '0'. writing a '0' has no effect. this register always reads as '0'. device configurations 132 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved r-0000 0000 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved intarm0 r-0000 0000 0000 000 r-0 legend: r = read only, n = value at reset figure 4-23. armint status register [0x01c4 0070] table 4-43. armint status register bit descriptions (1) bit name description 31:1 reserved reserved. a read returns 0. 0 intarm0 dsp-to-arm int0 status (1) read only, writes have no effect. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved r-0000 0000 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved intarm0 r-0000 0000 0000 000 r/w-0 legend: r = read, w = write, n = value at reset figure 4-24. armintset register [0x01c4 0074] table 4-44. armintset register bit descriptions bit name description 31:1 reserved reserved. a read returns 0. 0 intarm0 dsp-to-arm int0 set (1) (1) writing a '1' generates the interrupt and sets the corresponding bit in the armint status register. the register bit automatically clears to a value of '0'. writing a '0' has no effect. this register always reads as '0'. submit documentation feedback device configurations 133
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved r-0000 0000 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved intarm0 r-0000 0000 0000 000 r/w-0 legend: r = read, w = write, n = value at reset figure 4-25. armintclr register [0x01c4 0078] table 4-45. armintclr register bit descriptions bit name description 31:1 reserved reserved. a read returns 0. 0 intarm0 dsp-to-arm int0 clear (1) (1) writing a '1' clears the corresponding bit in the armint status register. the register bit automatically clears to a value of '0'. writing a '0' has no effect. this register always reads as '0'. 134 device configurations submit documentation feedback
4.7.3.13 emulation control tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the flexibility of the dm646x dmsoc architecture allows either the arm or dsp to control the various peripherals (setup registers, service interrupts, etc.). while this assignment is purely a matter of software convention, during an emulation halt it is necessary for the device to know which peripherals are associated with the halting processor so that only those modules receive the suspend signal. this allows peripherals associated with the other (unhalted) processor to continue normal operation. the suspsrc register indicates the emulation suspend source for those peripherals which support emulation suspend. the suspsrc register format is shown in figure 4-26 . brief details on the peripherals which correspond to the register bits are listed in table 4-46 . when the associated suspsrc bit is ?0?, the peripheral?s emulation suspend signal is controlled by the arm emulator and when set to ?1? it is controlled by the dsp emulator. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 crgen1 crgen0 timr2 timr1 timr0 gpio pwm1 pwm0 spi uart2 uart1 uart0 i2c mcasp1 mcasp0 rsv src src src src src src src src src src src src src src src r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 15 13 12 11 10 9 8 7 6 5 4 3 0 hpi emac usb vdce tsif1 tsif0 vpif reserved rsv rsv reserved src src src src src src src r-000 r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r/w-0 r-0000 legend: r/w = read/write; r = read only; - n = value after reset figure 4-26. suspsrc register table 4-46. suspsrc register bit descriptions bit name description clock recovery generator 1 emulation suspend source. 31 crgen1src 0 = arm emulation suspend. 1 = dsp emulation suspend. clock recovery generator 0 emulation suspend source. 30 crgen0src 0 = arm emulation suspend. 1 = dsp emulation suspend. timer2 (wd timer) emulation suspend source. 29 timr2src 0 = arm emulation suspend. 1 = dsp emulation suspend. timer1 emulation suspend source. 28 timr1src 0 = arm emulation suspend. 1 = dsp emulation suspend. timer0 emulation suspend source. 27 timr0src 0 = arm emulation suspend. 1 = dsp emulation suspend. gpio emulation suspend source. 26 gpiosrc 0 = arm emulation suspend. 1 = dsp emulation suspend. 25 rsv reserved. read returns "0". pwm1 emulation suspend source. 24 pwm1src 0 = arm emulation suspend. 1 = dsp emulation suspend. pwm0 emulation suspend source. 23 pwm0src 0 = arm emulation suspend. 1 = dsp emulation suspend. spi emulation suspend source. 22 spisrc 0 = arm emulation suspend. 1 = dsp emulation suspend. submit documentation feedback device configurations 135
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 4-46. suspsrc register bit descriptions (continued) bit name description uart2 emulation suspend source. 21 uart2src 0 = arm emulation suspend. 1 = dsp emulation suspend. uart1 emulation suspend source. 20 uart1src 0 = arm emulation suspend. 1 = dsp emulation suspend. uart0 emulation suspend source. 19 uart0src 0 = arm emulation suspend. 1 = dsp emulation suspend. i2c emulation suspend source. 18 i2csrc 0 = arm emulation suspend. 1 = dsp emulation suspend. mcasp1 emulation suspend source. 17 mcasp1src 0 = arm emulation suspend. 1 = dsp emulation suspend. mcasp0 emulation suspend source. 16 mcasp0src 0 = arm emulation suspend. 1 = dsp emulation suspend. 15:13 reserved reserved. read returns "0". hpi emulation suspend source. 12 hpisrc 0 = arm emulation suspend. 1 = dsp emulation suspend. 11 rsv reserved. read returns "0". ethernet mac emulation suspend source. 10 emacsrc 0 = arm emulation suspend. 1 = dsp emulation suspend. usb emulation suspend source. 9 usbsrc 0 = arm emulation suspend. 1 = dsp emulation suspend. vdce emulation suspend source. 8 vdcesrc 0 = arm emulation suspend. 1 = dsp emulation suspend. tsif1 emulation suspend source. 7 tsif1src 0 = arm emulation suspend. 1 = dsp emulation suspend. tsif0 emulation suspend source. 6 tsif0src 0 = arm emulation suspend. 1 = dsp emulation suspend. 5 rsv reserved. read returns "0". video port emulation suspend source. 4 vpifsrc 0 = arm emulation suspend. 1 = dsp emulation suspend. 3:0 reserved reserved. read returns "0". device configurations 136 submit documentation feedback
4.8 debugging considerations 4.8.1 pullup/pulldown resistors tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 proper board design should ensure that input pins to the tms320dm646x dmsoc device always be at a valid logic level and not floating. this may be achieved via pullup/pulldown resistors. the tms320dm646x dmsoc features internal pullup (ipu) and internal pulldown (ipd) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors. an external pullup/pulldown resistor needs to be used in the following situations: boot and configuration pins: if the pin is both routed out and 3-stated (not driven), an external pullup/pulldown resistor is strongly recommended, even if the ipu/ipd matches the desired value/state. other input pins: if the ipu/ipd does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail. for the boot and configuration pins (listed in table 3-5 , boot terminal functions), if they are both routed out and 3-stated (not driven), it is strongly recommended that an external pullup/pulldown resistor be implemented. although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device boot and configuration pins. in addition, applying external pullup/pulldown resistors on the boot and configuration pins adds convenience to the user in debugging and flexibility in switching operating modes. tips for choosing an external pullup/pulldown resistor: consider the total amount of current that may pass through the pullup or pulldown resistor. make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors. decide a target value for the net. for a pulldown resistor, this should be below the lowest v il level of all inputs connected to the net. for a pullup resistor, this should be above the highest v ih level of all inputs on the net. a reasonable choice would be to target the v ol or v oh levels for the logic family of the limiting device; which, by definition, have margin to the v il and v ih levels. select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. the current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net. for bidirectional nets, there is an additional consideration which sets a lower limit on the resistance value of the external resistor. verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin). remember to include tolerances when selecting the resistor value. for pullup resistors, also remember to include tolerances on the dv dd rail. for most systems, a 1-k w resistor can be used to oppose the ipu/ipd while meeting the above criteria. users should confirm this resistor value is correct for their specific application. for most systems, a 20-k w resistor can be used to compliment the ipu/ipd on the boot and configuration pins while meeting the above criteria. users should confirm this resistor value is correct for their specific application. for most systems, a 20-k w resistor can also be used as an external pu/pd on the pins that have ipus/ipds disabled and require an external pu/pd resistor while still meeting the above criteria. users should confirm this resistor value is correct for their specific application. for more detailed information on input current (i i ), and the low-/high-level input voltages (v il and v ih ) for the dm6467 dmsoc, see section 6.3 , electrical characteristics over recommended ranges of supply voltage and operating temperature. submit documentation feedback device configurations 137
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com for the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal functions table. 138 device configurations submit documentation feedback
5 system interconnect tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 on the dm6467 device, the c64x+ megamodule, the arm subsystem, the edma3 transfer controllers, and the system peripherals are interconnected through a switch fabric architecture. the switch fabric is composed of multiple switched central resources (scrs) and multiple bridges. for more detailed information on the dmsoc system interconnect architecture, including the device-specific scrs, bridges, and the system connection matrix, see the tms320dm6467 soc architecture and throughput overview application report (literature number spraaw4). submit documentation feedback system interconnect 139
6 device operating conditions 6.1 absolute maximum ratings over operating case temperature range (unless otherwise tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com noted) (1) supply voltage ranges: core (cv dd , dev_cv dd , aux_cv dd ) (2) ?0.5 v to 1.5 v i/o, 3.3v (dv dd33 , usb_v dda3p3 ) (2) ?0.3 v to 3.8 v i/o, 1.8v (dv ddr2 , pll1v dd18 , pll2v dd18 , dev_dv dd18 , aux_dv dd18 , ?0.3 v to 2.6 v usb_v dd1p8 ) (2) input and output voltage ranges: ?0.3 v to 3.8 v v i/o, 3.3-v pins (except pci-capable pins) ?0.3 v to dv dd33 + 0.3 v ?0.5 v to 4.2 v v i/o, 3.3-v pins pci-capable pins ?0.5 v to dv dd33 + 0.5 v ?0.3 v to 2.6 v v i/o, 1.8 v ?0.3 v to dv dd18 + 0.3 v operating case temperature (default) [-594, -729] 0 c to 85 c ranges, t c : (a version) extended temperature [-594a, -594av only] -40 c to 105 c (d version) industrial temperature [-729d only] -40 c to 85 c storage temperature range, t stg (default) ?55 c to 150 c electrostatic discharge (esd) esd-hbm (human body model) (3) 2000 v performance: esd-cdm (charged-device model) ddr2 (silicon revision 1.1 and 150 v pins (4) 1.0) (silicon revision 3.0) 500 v esd-cdm (charged-device model) ? all pins except ddr2 pins (4) 500 v (1) stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to v ss. (3) based on jedec jesd22-a114e ( electrostatic discharge (esd) sensitivity testing human body model (hbm)). (4) based on jedec jesd22-c101c ( field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components). device operating conditions 140 submit documentation feedback
6.2 recommended operating conditions tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 min nom max unit supply voltage, core (cv dd , dev_cv dd , aux_cv dd ) (1) 1.14 1.2 1.26 v cv dd 1.14 1.2 1.26 v supply voltage, core (cv dd , dev_cv dd , aux_cv dd ) (1) [-594v, -594av only] (smartreflex) [see table 4-39 ] 1.00 1.05 1.1 v supply voltage, i/o, 3.3v (dv dd33 , usb_v dda3p3 ) 3.14 3.3 3.46 v dv dd supply voltage, i/o, 1.8v (dv ddr2 , pll1v dd18 , pll2v dd18 , 1.71 1.8 1.89 v dev_dv dd18 , aux_dv dd18 , usb_v dd1p8 (2) ) supply ground (v ss , pll1v ss , pll2v ss , dev_v ss (3) , v ss 0 0 0 v aux_v ss (3) , usb_v ssref ) ddr_vref ddr2 reference voltage (4) 0.49dv ddr2 0.5dv ddr2 0.51dv ddr2 v ddr2 impedance control, connected via 50- w ( 0.5% tolerance) ddr_zp v ss v resistor to v ss ddr2 impedance control, connected via 50- w ( 0.5% tolerance) ddr_zn dv ddr2 v resistor to dv ddr2 high-level input voltage, 3.3 v (except jtag[tck], pci-capable, 2 v and i2c pins) high-level input voltage, jtag [tck] 2.5 v v ih high-level input voltage, pci 0.5dv dd33 v high-level input voltage, i2c 0.7dv dd33 v high-level input voltage, non-ddr i/o, 1.8 v 0.65dv dd18 v low-level input voltage, 3.3 v (except pci-capable and i2c 0.8 v pins) low-level input voltage, pci 0.3dv dd33 v v il low-level input voltage, i2c 0 0.3dv dd33 v low-level input voltage, non-ddr i/o, 1.8 v 0.35dv dd18 v default 0 85 t c operating case temperature (a version) -40 105 c (d version) -40 85 -594 20 594 mhz f sysclk1 dsp operating frequency (sysclk1) -729 20 729 mhz (1) future variants of ti soc devices may operate at voltages ranging from 0.9 v to 1.4 v to provide a range of system power/performance options. ti highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 v, 1.05 v, 1.1 v, 1.14 v, 1.2 v, 1.26 v with 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of ti soc devices. (2) oscillator 1.8 v power supply (dev_dv dd18 ) can be connected to the same 1.8 v power supply as dv ddr2 . (3) oscillator ground (dev_v ss and aux_v ss ) must be kept separate from other grounds and connected directly to the crystal load capacitor ground. (4) ddr_vref is expected to equal 0.5dv ddr2 of the transmitting device and to track variations in the dv ddr2 . submit documentation feedback device operating conditions 141
6.3 electrical characteristics over recommended ranges of supply voltage and operating tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com temperature (unless otherwise noted) parameter test conditions (1) min typ max unit low/full speed: usb_dn and usb_dp 2.8 usb_v dda3p3 v high speed: usb_dn and usb_dp 360 440 mv high-level output voltage (3.3v i/o except v oh dv dd33 = min, i oh = max 2.4 v pci-capable and i2c pins) high-level output voltage (3.3v i/o i oh = ?0.5 ma, dv dd33 = 3.3 v 0.9dv dd33 (2) v pci-capable pins) low/full speed: usb_dn and usb_dp 0.0 0.3 v high speed: usb_dn and usb_dp ?10 10 mv low-level output voltage (3.3v i/o except dv dd33 = min, i ol = max 0.4 v v ol pci-capable and i2c pins) low-level output voltage (3.3v i/o i ol = 1.5 ma, dv dd33 = 3.3 v 0.1dv dd33 (2) v pci-capable pins) low-level output voltage (3.3v i/o i2c pins) i o = 3 ma 0 0.4 v v ldo usb_v dda1p2ldo output voltage 1.14 1.2 1.26 v v i = v ss to dv dd33 without opposing 20 m a internal resistor input current [dc] (except i2c and v i = v ss to dv dd33 with opposing 50 100 250 m a pci-capable pins) internal pullup resistor (4) v i = v ss to dv dd33 with opposing ?250 ?100 ?50 m a internal pulldown resistor (4) i i (3) input current [dc] (i2c) v i = v ss to dv dd33 20 m a 0 < v i < dv dd33 = 3.3 v without 50 m a opposing internal resistor 0 < v i < dv dd33 = 3.3 v with opposing input current (pci-capable pins) [dc] (5) 50 250 m a internal pullup resistor (4) 0 < v i < dv dd33 = 3.3 v with opposing ?250 ?50 m a internal pulldown resistor (4) gmtclk, mtxd[7:0], mtxen ?8 ma ddr2; v oh = dv ddr2 ? 0.4 v ?8 ma i oh high-level output current [dc] pci-capable pins ?0.5 (2) ma (pci pin function only) all other peripherals ?4 ma gmtclk, mtxd[7:0], mtxen 8 ma ddr2; v ol = 0.4 v 8 ma i ol low-level output current [dc] pci-capable pins 1.5 (2) ma (pci pin function only) all other peripherals 4 ma v o = dv dd33 or v ss ; internal pull 20 m a disabled i oz (6) i/o off-state output current v o = dv dd33 or v ss ; internal pull 100 m a enabled (1) for test conditions shown as min, max, or typ, use the appropriate value specified in the recommended operating conditions table. (2) these rated numbers are from the pci local bus specification revision 2.3. the dc specifications and ac specifications are defined in table 4-3 (dc specifications for 3.3v signaling) and table 4-4 (ac specifications for 3.3v signaling), respectively. (3) i i applies to input-only pins and bi-directional pins. for input-only pins, i i indicates the input leakage current. for bi-directional pins, i i indicates the input leakage current and off-state (hi-z) output leakage current. (4) applies only to pins with an internal pullup (ipu) or pulldown (ipd) resistor. (5) pci input leakage currents include hi-z output leakage for all bidirectional buffers with 3-state outputs. (6) i oz applies to output-only pins, indicating off-state (hi-z) output leakage current. 142 device operating conditions submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 electrical characteristics over recommended ranges of supply voltage and operating temperature (unless otherwise noted) (continued) parameter test conditions (1) min typ max unit cv dd = 1.2 v, dsp clock = 594 mhz arm clock = 297 mhz, ddr clock = 1318.58 ma 297 mhz cv dd = 1.05 v, dsp clock = 594 mhz arm clock = 297 mhz, ddr clock = 814.00 ma 297 mhz (smartreflex v parts) core (cv dd , dev_cv dd , aux_cv dd ) i cdd supply current (7) cv dd = 1.2 v, dsp clock = 594 mhz arm clock = 297 mhz, ddr clock = 915.39 ma 297 mhz (smartreflex v parts) cv dd = 1.2 v, dsp clock = 729 mhz arm clock = 364.5 mhz, ddr clock = 1622.09 ma 310.5 mhz dv dd = 3.3 v, dsp clock = 594 mhz arm clock = 297 mhz, ddr clock = 25.32 ma 297 mhz 3.3v i/o (dv dd33 , usb_v dda3p3 ) supply i ddd current (7) dv dd = 3.3 v, dsp clock = 729 mhz arm clock = 364.5 mhz, ddr clock = 26.17 ma 310.5 mhz dv dd = 1.8 v, dsp clock = 594 mhz arm clock = 297 mhz, ddr clock = 255.15 ma 1.8v i/o (dv ddr2 , pll1v prw18 , 297 mhz i ddd pll2v prw18 , dev_dv dd18 , aux_dv dd18 , dv dd = 1.8 v, dsp clock = 729 mhz usb_v dd1p8 ) supply current (7) arm clock = 364.5 mhz, ddr clock = 260.42 ma 310.5 mhz c i input capacitance 4 pf c o output capacitance 4 pf (7) measured under the following conditions: 60% dsp cpu utilization; arm doing typical activity (peripheral configurations, other housekeeping activities); ddr2 memory controller at 50% utilization, 50% writes, 32 bits, 50% bit switching at room temperature (25 c). the actual current draw varies across manufacturing processes and is highly application-dependent. for more details on core and i/o activity, as well as information relevant to board power supply design, see the tms320dm646x power consumption summary application report (literature number spraas2 ). submit documentation feedback device operating conditions 143
7 peripheral information and electrical specifications 7.1 parameter information 7.1.1 1..8-v and 3.3-v signal transition levels 7.1.2 3.3-v signal transition rates tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com figure 7-1. test load circuit for ac timing measurements the load capacitance value stated is only for characterization and measurement of ac timing signals. this load capacitance value does not indicate the maximum load the device is capable of driving. all input and output timing parameters are referenced to v ref for both "0" and "1" logic levels. for 3.3-v i/o, v ref = 1.5 v. for 1.8-v i/o, v ref = 0.9 v. figure 7-2. input and output voltage reference levels for ac timing measurements all rise and fall transition timing parameters are referenced to v il max and v ih min for input clocks, v ol max and v oh min for output clocks. figure 7-3. rise and fall transition time voltage reference levels all timings are tested with an input edge rate of 4 volts per nanosecond (4 v/ns). 144 peripheral information and electrical specifications submit documentation feedback v ref transmissionline 4.0pf 1.85pf z0=50(seenote) testerpinelectronics datasheettimingreferencepoint output under test note: the data sheet provides timing at the device pin. for output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. a transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. the transmission line is intended as a load only. it is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings. input requirements in this data sheet are tested with an input slew rate of < 4 volts per nanosecond (4 v/ns) at the device pin. 42 3.5nh devicepin(seenote) v = v max (or v max) ref il ol v = v min (or v min) ref ih oh
7.1.3 timing parameters and board routing analysis 7.2 recommended clock and control signal transition behavior tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the timing parameter values specified in this data manual do not include delays by board routings. as a good board design practice, such delays must always be taken into account. timing values may be adjusted by increasing/decreasing such delays. ti recommends utilizing the available i/o buffer information specification (ibis) models to analyze the timing characteristics correctly. to properly use ibis models to attain accurate timing analysis for a given system, see the using ibis models for timing analysis application report (literature number spra839). if needed, external logic hardware such as buffers may be used to compensate any timing differences. for the ddr2 memory controller interface, it is not necessary to use the ibis models to analyze timing characteristics. ti provides a pcb routing rules solution that describes the routing rules to ensure the ddr2 memory controller interface timings are met. see the implementing ddr2 pcb layout on the tms320dm646x dmsoc application report (literature number spraam1a ). all clocks and control signals must transition between v ih and v il (or between v il and v ih ) in a monotonic manner. submit documentation feedback peripheral information and electrical specifications 145
7.3 power supplies 7.3.1 power-supply sequencing 7.3.2 power-supply design considerations 7.3.3 power-supply decoupling 7.3.4 dm6467 power and clock domains tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com for more information regarding ti's power management products and suggested devices to power ti dsps, visit www.ti.com/processorpower . the dm6467 includes one core supply (cv dd ), and two i/o supplies?dv dd33 and dv ddr2 . to ensure proper device operation, a specific power-up sequence must be followed. some ti power-supply devices include features that facilitate power sequencing?for example, auto-track and slow-start/enable features. for more information on ti power supplies and their features, visit www.ti.com/processorpower . here is a summary of the power sequencing requirements: the power ramp order must be cv dd before dv ddr2 , and dv ddr2 before dv dd33 ?meaning during power up, the voltage at the dv ddr2 rail should never exceed the voltage at the cv dd rail. similarly, the voltage at the dv ddd33 rail should never exceed the voltage at the dv ddr2 rail. from the time that power ramp begins, all power supplies (cv dd , dv ddr2 , dv dd33 ) must be stable within 200 ms. the term "stable" means reaching the recommended operating condition (see section 6.2 , recommended operating conditions table). core and i/o supply voltage regulators should be located close to the dsp (or dsp array) to minimize inductance and resistance in the power delivery path. additionally, when designing for high-performance applications utilizing the dm6467 device, the pc board should include separate power planes for core, i/o, and ground; all bypassed with high-quality low-esl/esr capacitors. in order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the dm6467. these caps need to be close to the dm6467 power pins, no more than 1.25 cm maximum distance to be effective. physically smaller caps, such as 0402, are better but need to be evaluated from a yield/manufacturing point-of-view. parasitic inductance limits the effectiveness of the decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest available capacitance value. larger caps for each supply can be placed further away for bulk decoupling. large bulk caps (on the order of 100 m f) should be furthest away, but still as close as possible. large caps for each supply should be placed outside of the bga footprint. as with the selection of any component, verification of capacitor availability over the product's production lifetime should be considered. for more details on capacitor usage and placement, see the implementing ddr2 pcb layout on the tms320dm646x dmsoc application report (literature number spraam1a ). the dm6467 includes one single power domain ? the "always on" power domain. the "always on" power domain is always on when the chip is on. the "always on" domain is powered by the cv dd pins of the dm6467. all dm6467 modules lie within the "always on" power domain. table 7-1 provides a listing of the dm6467 clock domains. two primary reference clocks are required for the dm6467 device. these can either be crystal inputs or driven by external oscillators. a 27-mhz crystal is recommended for the system plls, which generate the internal clocks for the arm926, dsp, hdvicps, peripherals, and the edma3. a 24- or 48-mhz crystal is also required if the usb (24-mhz only) or uart (either 24- or 48-mhz) peripherals are to be used. in addition, the 24- or 48-mhz input clock can be used to source the mcasps' clocks. for further description of the dm6467 clock domains, see table 7-2 and figure 7-4 . peripheral information and electrical specifications 146 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the dm6467 architecture is divided into the power and clock domains shown in table 7-1 . table 7-2 further discusses the clock domains and their ratios. figure 7-4 shows the clock domain block diagram. table 7-1. dm6467 power and clock domains power domain clock domain peripheral/module always on sysclk3 uart0 always on sysclk3 uart1 always on sysclk3 uart2 always on sysclk3 i2c always on sysclk3 timer0 always on sysclk3 timer1 always on sysclk3 timer2 always on sysclk3 pwm0 always on sysclk3 pwm1 always on sysclk2 ddr2 always on sysclk2 vpif always on sysclk2 tsif0 always on sysclk2 tsif1 always on sysclk2 vdce always on sysclk2 hdvicp0 always on sysclk2 hdvicp1 always on sysclk2 edma3 always on sysclk2 pci always on sysclk2 scr always on sysclk3 gpsc always on sysclk3 lpscs always on sysclk3 pllc1 always on sysclk3 pllc2 always on sysclk3 ice pick always on sysclk3 emifa always on sysclk3 usb always on sysclk3 hpi always on sysclk3 vlynq always on sysclk3 emac/mdio always on sysclk3 spi always on sysclk3 mcasp0 always on sysclk3 mcasp1 always on sysclk3 crgen0 always on sysclk3 crgen1 always on sysclk4 ata always on sysclk3 gpio always on sysclk1 c64x+ cpu always on sysclk2 arm926 submit documentation feedback peripheral information and electrical specifications 147
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-2. dm6467 clock domains domain fixed ratio vs. clock clock sysclk1 clock modes frequency (mhz) domain source frequency subsystem pll mode pll mode bypass mode (-594) (1) (-729) (2) dsp subsystem pllc1 1:1 plldiv1 27 mhz 594 mhz 729 mhz sysclk1 arm926 subsystem, 1:2 edma3, hdvicp, pci, pllc1 plldiv2 13.5 mhz 297 mhz 364.5 mhz vdce, vpif, tsifs, sysclk2 ddr2 mem ctlr peripherals (gpio, 1:4 timers, i2c, pwms, hpi, emac, emifa, vlynq, pllc1 plldiv3 6.75 mhz 148.5 mhz 182.25 mhz spi, arm intc, usb2.0, sysclk3 uarts, mcasps, crgens, system) ata pllc1 1:6 (-594) [default] (3) plldiv4 4.5 mhz 99 mhz 104.14 mhz sysclk4 1:7 (-729) (3) tsif0 (4) pllc1 1:8 (-594) [default] (3) plldiv5 3.38 mhz 74.25 mhz 72.9 mhz sysclk5 1:10 (-729) (3) tsif1 (4) pllc1 1:8 (-594) [default] (3) plldiv6 3.38 mhz 74.25 mhz 72.9 mhz sysclk6 1:10 (-729) (3) vpif (4) pllc1 1:6 (-594) [default] (3) plldiv8 3.38 mhz 99 mhz 104.14 mhz (5) sysclk8 1:7 (-729) (3) vlynq pllc1 1:6 (-594) [default] (3) plldiv9 4.5 mhz 99 mhz 104.14 mhz sysclk9 1:7 (-729) (3) ddr2 phy pllc2 1:1 plldiv1 27 mhz 594 mhz 621 mhz sysclk1 (1) these table values assume a dev_mxi/dev_clkin of 27 mhz and a pll1 multiplier equal to 22. (2) these table values assume a dev_mxi/dev_clkin of 27 mhz and a pll1 multiplier equal to 27. (3) the default sysclkx ratios apply to the -594 mhz device only. for the -729 mhz device to achieve the quoted frequencines, the pllc1 sysclkx (for sysclk4, sysclk5, sysclk6, sysclk8, sysclk9) default divider values must be changed. for the steps to change the pllc1 sysclkx divider values, see the tms320dm646x dmsoc arm subsystem reference guide (literature number spruep9 ). (4) these domain clock sources, along with vp_clkin[3:0], stc_clkin, crg0_vcxi, and crg1_vcxi clock signals, go through the clock select logic to determine the clock source enabled as the input to the vpif and tsif peripherals. (5) for the -729 device, use an external clock source for the 54-/74.25-/108-mhz vpif clock. peripheral information and electrical specifications 148 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 figure 7-4. pll1 and pll2 clock domain block diagram for further detail on pll1 and pll2, see the structure block diagrams shown in figure 7-5 and figure 7-6 , respectively. figure 7-5. pll1 structure block diagram submit documentation feedback peripheral information and electrical specifications 149 pll controller 1 plldiv1 (/1 fixed) sysclk1 plldiv2 (/2 fixed) sysclk2 plldiv3 (/4 fixed) sysclk3 plldiv4 (/6 prog) sysclk4 plldiv9 (/6 prog) sysclk9 plldiv5 (/8 prog) sysclk5 plldiv6 (/8 prog) sysclk6 plldiv8 (/8 prog) sysclk8 bpdiv (/1 prog) sysclkbpauxclk dev_mxi/ dev_clkin (27 mhz) dsp subsystem pci vdce hdvicp0hdvicp1 edma3 crossbar/scr arm subsystem gpio timer 0 timer 1 timer 2 (wd) i2c pwm (x2) hpi emac/mdio emifa vlynq spi arm intc ata tinp0ltinp0u tinp1l usb 2.0 60 mhz usb phy uart0 mcasp0mcasp1 aux_mxi/aux_clkin (24/48 mhz) clock select logic tsif0 tsif1 video port i/f clkout0audio_clk0 audio_clk1 crgen0crgen1 ddr2 mem cltr uart1uart2 vp_clkin0 vp_clkin1 vp_clkin2 vp_clkin3 stc_clkin crg0_vcxicrg1_vcxi plldiv1 (/1 prog) pll controller 2 pll2_sysclk1 pllm pllm plldiv1 (/1 fixed)plldiv2 (/2 fixed) plldiv3 (/4 fixed) plldiv4 (/6 prog) plldiv5 (/8 prog) plldiv6 (/8 prog)plldiv8 (/8 prog) plldiv9 (/6 prog) bpdiv (/1 prog) sysclk1sysclk2 sysclk3 sysclk4sysclk5 sysclk6 sysclk8 sysclk9sysclkbp auxclk 1 0 pllen pll 1 0 clkmode pllm clkin oscin pllout
7.3.5 power and sleep controller (psc) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com figure 7-6. pll2 structure block diagram the power and sleep controller (psc) controls device power by gating off clocks to individual peripherals/modules. the psc consists of a global psc (gpsc) and a set of local pscs (lpscs). the gpsc contains memory mapped registers, psc interrupt control, and a state machine for each peripheral/module. an lpsc is associated with each peripheral/module and provides clock and reset control. the gpsc controls all of the dm6467's lpscs. the arm subsystem does not have an lpsc module. arm sleep mode is accomplished through the wait for interrupt instruction. the lpscs for dm6467 are shown in table 7-3 . the psc register memory map is given in table 7-4 . for more details on the psc, see the tms320dm646x dmsoc arm subsystem reference guide (literature number spruep9 ). table 7-3. dm6467 lpsc assignments lpsc peripheral/module lpsc peripheral/module lpsc peripheral/module number number number 0 reserved 16 video port 32 spi 1 c64x+ cpu 17 video port 33 gpio 2 hdvicp0 18 tsif0 34 timer0 3 hdvicp1 19 tsif1 35 timer1 4 edma cc 20 ddr2 memory controller 36 reserved 5 edma tc0 21 emifa 37 reserved 6 edma tc1 22 mcasp0 38 reserved 7 edma tc2 23 mcasp1 39 reserved 8 edma tc3 24 crgen0 40 reserved 9 usb2.0 25 crgen1 41 reserved 10 ata 26 uart0 42 reserved 11 vlynq 27 uart1 43 reserved 12 hpi 28 uart2 44 reserved 13 pci 29 pwm0 45 arm intc 14 emac/mdio 30 pwm1 15 vdce 31 i2c peripheral information and electrical specifications 150 submit documentation feedback plldiv1 (/1 prog) pll2_sysclk1(ddr2_phy) 1 0 pllen pll pllm clkin/oscin (a) (a) as selected by the pll2 pllctl register pllout
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-4. psc registers register hex address range description acronym 0x01c4 1000 pid peripheral revision and class information register 0x01c4 1004 - 0x01c4 1017 ? reserved 0x01c4 1018 inteval interrupt evaluation register 0x01c4 101c - 0x01c4 1039 ? reserved 0x01c4 1040 merrpr0 module error pending 0 (mod 0- 31) register 0x01c4 1044 merrpr1 module error pending 1 (mod 32- 63) register 0x01c4 1048 - 0x01c4 1049 ? reserved 0x01c4 1050 merrcr0 module error clear 0 (mod 0 - 31) register 0x01c4 1054 merrcr1 module error clear 1 (mod 32 - 63) register 0x01c4 1058 - 0x01c4 111f reserved 0x01c4 1120 ptcmd power domain transition command register 0x01c4 1124 - 0x01c4 1127 ? reserved 0x01c4 1128 ptstat power domain transition status register 0x01c4 112c - 0x01c4 11ff ? reserved 0x01c4 1200 pdstat0 power domain status 0 register (always on) 0x01c4 1204 - 0x01c4 12ff ? reserved 0x01c4 1300 pdctl0 power domain control 0 register (always on) 0x01c4 1304 - 0x01c4 17ff ? reserved 0x01c4 1800 - 0x01c4 1803 ? reserved 0x01c4 1804 mdstat1 module status 1 register (c64x+ cpu) 0x01c4 1808 mdstat2 module status 2 register (hdvicp0) 0x01c4 180c mdstat3 module status 3 register (hdvicp1) 0x01c4 1810 mdstat4 module status 4 register (edma cc) 0x01c4 1814 mdstat5 module status 5 register (edma tc0) 0x01c4 1818 mdstat6 module status 6 register (edma tc1) 0x01c4 181c mdstat7 module status 7 register (edma tc2) 0x01c4 1820 mdstat8 module status 8 register (edma tc3) 0x01c4 1824 mdstat9 module status 9 register (usb) 0x01c4 1828 mdstat10 module status 10 register (ata) 0x01c4 182c mdstat11 module status 11 register (vlynq) 0x01c4 1830 mdstat12 module status 12 register (hpi) 0x01c4 1834 mdstat13 module status 13 register (pci) 0x01c4 1838 mdstat14 module status 14 register (emac) 0x01c4 183c mdstat15 module status 15 register (vdce) 0x01c4 1840 mdstat16 module status 16 register (vdieo port) 0x01c4 1844 mdstat17 module status 17 register (video port) 0x01c4 1848 mdstat18 module status 18 register (tsif0) 0x01c4 184c mdstat19 module status 19 register (tsif1) 0x01c4 1850 mdstat20 module status 20 register (ddr2 mem ctlr) 0x01c4 1854 mdstat21 module status 21 register (emifa) 0x01c4 1858 mdstat22 module status 22 register (mcasp0) 0x01c4 185c mdstat23 module status 23 register (mcasp1) 0x01c4 1860 mdstat24 module status 24 register (crgen0) 0x01c4 1864 mdstat25 module status 25 register (crgen1) 0x01c4 1868 mdstat26 module status 26 register (uart0) 0x01c4 186c mdstat27 module status 27 register (uart1) submit documentation feedback peripheral information and electrical specifications 151
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-4. psc registers (continued) register hex address range description acronym 0x01c4 1870 mdstat28 module status 28 register (uart2) 0x01c4 1874 mdstat29 module status 29 register (pwm0) 0x01c4 1878 mdstat30 module status 30 register (pwm1) 0x01c4 187c mdstat31 module status 31 register (i2c) 0x01c4 1880 mdstat32 module status 32 register (spi) 0x01c4 1884 mdstat33 module status 33 register (gpio) 0x01c4 1888 mdstat34 module status 34 register (timer0) 0x01c4 188c mdstat35 module status 35 register (timer1) 0x01c4 1890 - 0x01c4 18b3 ? reserved 0x01c4 18b4 mdstat45 module status 45 register (arm intc) 0x01c4 18b8 - 0x01c4 19ff ? reserved 0x01c4 1a00 - 0x01c4 1a03 ? reserved 0x01c4 1a04 mdctl1 module control 1 register (c64x+ cpu) 0x01c4 1a08 mdctl2 module control 2 register (hdvicp0) 0x01c4 1a0c mdctl3 module control 3 register (hdvicp1) 0x01c4 1a10 mdctl4 module control 4 register (edma cc) 0x01c4 1a14 mdctl5 module control 5 register (edma tc0) 0x01c4 1a18 mdctl6 module control 6 register (edma tc1) 0x01c4 1a1c mdctl7 module control 7 register (edma tc2) 0x01c4 1a20 mdctl8 module control 8 register (edma tc3) 0x01c4 1a24 mdctl9 module control 9 register (usb) 0x01c4 1a28 mdctl10 module control 10 register (ata) 0x01c4 1a2c mdctl11 module control 11 register (vlynq) 0x01c4 1a30 mdctl12 module control 12 register (hpi) 0x01c4 1a34 mdctl13 module control 13 register (pci) 0x01c4 1a38 mdctl14 module control 14 register (emac) 0x01c4 1a3c mdctl15 module control 15 register (vdce) 0x01c4 1a40 mdctl16 module control 16 register (video port) 0x01c4 1a44 mdctl17 module control 17 register (video port) 0x01c4 1a48 mdctl18 module control 18 register (tsif0) 0x01c4 1a4c mdctl19 module control 19 register (tsif1) 0x01c4 1a50 mdctl20 module control 20 register (ddr2 mem ctlr) 0x01c4 1a54 mdctl21 module control 21 register (emifa) 0x01c4 1a58 mdctl22 module control 22 register (mcasp0) 0x01c4 1a5c mdctl23 module control 23 register (mcasp1) 0x01c4 1a60 mdctl24 module control 24 register (crgen0) 0x01c4 1a64 mdctl25 module control 25 register (crgen1) 0x01c4 1a68 mdctl26 module control 26 register (uart0) 0x01c4 1a6c mdctl27 module control 27 register (uart1) 0x01c4 1a70 mdctl28 module control 28 register (uart2) 0x01c4 1a74 mdctl29 module control 29 register (pwm0) 0x01c4 1a78 mdctl30 module control 30 register (pwm1) 0x01c4 1a7c mdctl31 module control 31 register (i2c) 0x01c4 1a80 mdctl32 module control 32 register (spi) 0x01c4 1a84 mdctl33 module control 33 register (gpio) 0x01c4 1a88 mdctl34 module control 34 register (timer0) peripheral information and electrical specifications 152 submit documentation feedback
7.3.6 smartreflex (voltage scaling) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-4. psc registers (continued) register hex address range description acronym 0x01c4 1a8c mdctl35 module control 35 register (timer1) 0x01c4 1a90 - 0x01c4 1ab3 ? reserved 0x01c4 1ab4 mdctl45 module control 45 register (arm intc) 0x01c4 1ab8 - 0x01c4 1fff ? reserved increasing the device complexity increases its power consumption and with the smaller transistor structures responsible for higher achievable clock rates and increased performance, comes an inevitable penalty, increasing the leakage currents. leakage currents are present in any active circuit, independently of clock rates and usage scenarios. this static power consumption is mainly determined by transistor type and process technology. higher clock rates also increase dynamic power, the power used when transistors switch. the dynamic power depends mainly on a specific usage scenario, clock rates, and i/o activity. texas instruments' smartreflex? technology is used to decrease both static and dynamic power consumption while maintaining the device performance. smartreflex in the tms320dm6467 dmsoc device (-594v parts only) is a feature that allows the core voltage to be optimized based on the process corner of the device. this requires an adjustable power supply design with a voltage regulator. on the dm6467, devices with different strengths are partitioned into two groups: weak and strong. "weak" devices should run at 1.2-v core power supply where as "strong" devices can run at 1.05-v core to reduce power consumption. during manufacturing test, the device characterization information is stored permanently on the dm6467 device. on the dm6467 device, the smartreflex feature is disabled by default. it can be enabled by pulling the configuration pin vadjen (ab7) high before releasing the device out-of-reset. the vadjen input value is latched into bootcfg register (vadjen bit) at the rising edge of reset or por. once smartreflex is enabled, the pins gp[7]/cvddadj1 (a12) and gp[6]/cvddadj0 (e11) function as smartreflex control outputs to the adjustable core power supply and the gpio functionality is disabled. for more detailed information on the smartreflex and gpio pin muxing, see section 4.7.3.11 , smartreflex and gpio pin muxing. the read-only smtrefelx register [bits 1:0] reflects the status of the cvddadj[1:0] pins (see figure 7-7 , smtreflex register [0x01c4 0018]). for additional information on smartreflex, see the enabling smartreflex on the tms320dm6467 application report (literature number spraaz2 ). 31 16 reserved r-0000 0000 0000 0000 15 2 1 0 reserved smtreflex r-0000 0000 0000 00 r-pp legend: r = read only; p = pin value figure 7-7. smtreflex status register [0x01c4 0018] (voltage scale adjustment (v) parts only) submit documentation feedback peripheral information and electrical specifications 153
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-5. smtreflex status register bit descriptions bit name description 31:2 reserved reserved. read returns "0". when smartreflex control outputs are enabled (vadjen = 1), these bits reflect the status of the cvddadj[1:0] pins. 00 = 1.2 v core supply voltage 1:0 smtreflex 11 = 1.05 v core supply voltage for more detailed information on the smartreflex and gpio pin muxing, see section 4.7.3.11 , smartreflex and gpio pin muxing. peripheral information and electrical specifications 154 submit documentation feedback
7.4 external clock input from dev_mxi/dev_clkin and aux_mxi/aux_clkin pins 7.4.1 clock input option 1?crystal 7.4.1.1 27-mhz for system oscillator clock input option 1?crystal tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the dm6467 device includes two options to provide an external clock input for both the system and auxiliary oscillators: use an on-chip oscillator with external crystal (fundamental parallel resonant mode only, no overtone support). use an external 1.8-v lvcmos-compatible clock input. the optimal external clock input frequency for the crystals are 27 mhz for the system oscillator (dev_mxi/dev_clkin) and 24 mhz for the auxiliary oscillator. section 7.4.1.1 provides more details on option 1, using an on-chip oscillator with external crystal for the 27-mhz system oscillator. section 7.4.1.2 provides more details on option 1, using an on-chip oscillator with external crystal for the 24-mhz auxiliary oscillator. section 7.4.2.1 provides details on option 2, using an external 1.8-v lvcmos-compatible clock input for the 27-mhz system oscillator. section 7.4.2 provides details on option 2, using an external 1.8-v lvcmos-compatible clock input for the 24-mhz auxiliary oscillator. in this option, a crystal is used as the external clock input to the dm6467 system oscillator. the 27-mhz oscillator provides the reference clock for all dm6467 subsystems and peripherals. the on-chip oscillator requires an external 27-mhz crystal connected across the dev_mxi and dev_mxo pins, along with two load capacitors, as shown in figure 7-8 . the external crystal load capacitors must be connected only to the 27-mhz oscillator ground pin (dev_v ss ). do not connect to board ground (v ss ). the dev_dv dd18 pin can be connected to the same 1.8 v power supply as dv ddr2 . figure 7-8. 27-mhz system oscillator the load capacitors, c1 and c2, should be chosen such that the equation is satisfied (typical values are c1 = c2 = 10 pf). c l in the equation is the load specified by the crystal manufacturer. all discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (dev_mxi and dev_mxo) and to the dev_v ss pin. submit documentation feedback peripheral information and electrical specifications 155 dev_mxi/ dev_clkin dev_mxo c1 c2 crystal dev_v ss 27 mhz 1.8 v dev_dv dd18 1.2 v dev_cv dd dev_dv ss ( ) c c 1 2 c l c c 1 2 = +
7.4.1.2 24-mhz auxiliary oscillator clock input option 1?crystal tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-6. input requirements for crystal on the 27-mhz system oscillator parameter min nom max unit start-up time (from power up until oscillating at stable frequency of 4 ms 27 mhz) oscillation frequency 27 mhz esr 60 w in this option, a crystal is used as the external clock input to the dm6467 auxiliary oscillator. the 24-mhz oscillator provides the reference clock for usb and uart peripherals and the internal clock source for the mcasp peripherals. the on-chip oscillator requires an external 24-mhz crystal connected across the aux_mxi and aux_mxo pins, along with two load capacitors, as shown in figure 7-9 . the external crystal load capacitors must be connected only to the 24-mhz oscillator ground pin (aux_v ss ). do not connect to board ground (v ss ). the aux_dv dd18 pin can be connected to the same 1.8 v power supply as dv ddr2 . figure 7-9. 24-mhz auxiliary oscillator the load capacitors, c1 and c2, should be chosen such that the equation is satisfied (typical values are c1 = c2 = 10 pf). c l in the equation is the load specified by the crystal manufacturer. all discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (aux_mxi and aux_mxo) and to the aux_v ss pin. table 7-7. input requirements for crystal on the 24-mhz auxiliary oscillator parameter min nom max unit start-up time (from power up until oscillating at stable frequency of 4 ms 24 mhz) oscillation frequency 24 mhz esr 60 w (1) frequency stability 50 ppm (1) if the usb is used, a 24-mhz, 50-ppm crystal is recommended. peripheral information and electrical specifications 156 submit documentation feedback ( ) c c 1 2 c l c c 1 2 = + aux_mxi/ aux_clkin aux_mxo c1 c2 crystal aux_v ss 24 mhz 1.8 v aux_dv dd18 1.2 v aux_cv dd aux_dv ss
7.4.2 clock input option 2?1.8-v lvcmos-compatible clock input 7.4.2.1 27-mhz system oscillator clock input option 2?1.8-v lvcmos-compatible clock input 7.4.2.2 24-mhz auxiliary oscillator clock input option 2?1.8-v lvcmos-compatible clock input tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 in this option, a 1.8-v lvcmos-compatible clock input is used as the external clock input to the system oscillator. the external connections are shown in figure 7-10 . the dev_mxi/dev_clkin pin is connected to the 1.8-v lvcmos-compatible clock source. the dev_mxo pin is left unconnected. the dev_v ss pin is connected to board ground (v ss ). the dev_dv dd18 pin can be connected to the same 1.8-v power supply as dv ddr2 . figure 7-10. 1.8-v lvcmos-compatible clock input the clock source must meet the dev_mxi/dev_clkin timing requirements in section 7.5.5 , clock pll electrical data/timing (input and output clocks). in this option, a 1.8-v lvcmos-compatible clock input is used as the external clock input to the auxiliary oscillator. the external connections are shown in figure 7-11 . the aux_mxi/aux_clkin pin is connected to the 1.8-v lvcmos-compatible clock source. the aux_mxo pin is left unconnected. the aux_v ss pin is connected to board ground (v ss ). the aux_dv dd18 pin can be connected to the same 1.8-v power supply as dv ddr2 . figure 7-11. 1.8-v lvcmos-compatible clock input the clock source must meet the aux_mxi/aux_clkin timing requirements in section 7.5.5 , clock pll electrical data/timing (input and output clocks). submit documentation feedback peripheral information and electrical specifications 157 aux_mxi/ aux_clkin aux_mxo nc aux_v ss 1.8 v aux_dv dd18 aux_dv ss 1.2 v aux_cv dd dev_mxi/ dev_clkin dev_mxo nc dev_v ss 1.8 v dev_dv dd18 dev_dv ss 1.2 v dev_cv dd
7.5 clock plls 7.5.1 pll1 and pll2 tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com there are two independently controlled plls on dm6467. pll1 generates the frequencies required for the arm, dsp, hdvicp0/1, edma, and peripherals. pll2 generates the frequencies required for the ddr2 interface. the recommended reference clock for both plls is the 27-mhz crystal input. the dm6467 has a third pll that is embedded within the usb2.0 phy and the 24-mhz oscillator is its reference clock source. this particular pll is only usable for usb operation, and is discussed further in the tms320dm646x dmsoc universal serial bus (usb) controller user's guide (literature number spruer7 ). both pll1 and pll2 power are supplied externally via the 1.8-v pll power-supply pins (pll1v dd18 and pll2v dd18 ). an external emi filter circuit must be added to pll1v dd18 and pll2v dd18 , as shown in figure 7-12 . the 1.8-v supply of the emi filters must be from the same 1.8-v power plane supplying the device?s 1.8-v i/o power-supply pins (dv ddr2 ). ti recommends emi filter manufacturer murata, part number nfm18cc222r1c3. all pll external components (c1, c2, c3, c4, and the emi filters) must be placed as close to the device as possible. for the best performance, ti recommends that all the pll external components be on a single side of the board without jumpers, switches, or components other than the ones shown in figure 7-12 . for reduced pll jitter, maximize the spacing between switching signals and the pll external components (c1, c2, c3, c4, and the emi filters). figure 7-12. pll1 and pll2 external connection the minimum clkin rise and fall times should also be observed. for the input clock timing requirements, see section 7.5.5 , clock pll electrical data/timing (input and output clocks). there is an allowable range for pll multiplier (pllm). there is a minimum and maximum operating frequency for dev_mxi/dev_clkin, pllout, aux_mxi/aux_clkin, and the device clocks (sysclks). the pll controllers must be configured not to exceed any of these constraints documented in this section (certain combinations of external clock inputs, internal dividers, and pll multiply ratios might not be supported). for these constraints (ranges), see table 7-8 through table 7-10 . peripheral information and electrical specifications 158 submit documentation feedback dm646x pll2v dd18 c2 c1 emifilter +1.8v 0.01 f pll2 0.1 f c4 c3 emifilter +1.8v 0.01 f pll1 0.1 f pll1v dd18
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-8. pll1 and pll2 multiplier ranges -594 -729 pll multiplier (pllm) min max min max pll1 multiplier x14 x22 x14 x27 pll2 multiplier x14 x22 x14 x23 table 7-9. pllc1 clock frequency ranges -594 -729 clock signal name unit min max min max dev_mxi/dev_clkin (1) 20 30 20 30 mhz pllout 400 594 400 729 mhz sysclk1 (plldiv1 domain) 594 729 mhz (1) dev_mxi/dev_clkin input clock is used for both pll controllers (pllc1 and pllc2). table 7-10. pllc2 clock frequency ranges -594 -729 clock signal name unit min max min max dev_mxi/dev_clkin (1) 20 30 20 30 mhz pllout 400 594 400 621 mhz pll2_sysclk1 (to ddr2 phy) 594 621 mhz (1) dev_mxi/dev_clkin input clock is used for both pll controllers (pllc1 and pllc2). both pll1 and pll2 have stabilization, lock, and reset timing requirements that must be followed. the pll stabilization time is the amount of time that must be allotted for the internal pll regulators to become stable after the pll is powered up (after the pllctl.pllpwrdn bit goes through a 1-to-0 transition). the pll should not be operated until this stabilization time has expired. this stabilization step must be applied after these resets?a power-on reset, a warm reset, or a max reset, as the pllctl.pllpwrdn bit resets to a "1". for the pll stabliziation time value, see table 7-11 . the pll reset time is the amount of wait time needed for the pll to properly reset (writing pllrst = 1) before bringing the pll out of reset (writing pllrst = 0). for the pll reset time value, see table 7-11 . the pll lock time is the amount of time needed from when the pll is taken out of reset (pllrst = 0 with pllen = 0) to when to when the pll controller can be switched to pll mode (pllen = 1). for the pll lock time value, see table 7-11 . table 7-11. pll1 and pll2 stabilization, lock, and reset times pll stabilization/ min nom max unit lock/reset time pll stabilization time 150 m s pll lock time 2000c (1) ns pll reset time 128c (1) ns (1) c = clkin cycle time in ns. for example, when dev_mxi/dev_clkin or aux_mxi/aux_clkin frequency is 27 mhz, use c = 37. 037 ns. for details on the pll initialization software sequence, see the tms320dm646x dmsoc arm subsystem reference guide (literature number spruep9 ). for more information on the clock domains and their clock ratio restrictions, see section 7.3.4 , dm6467 power and clock domains. submit documentation feedback peripheral information and electrical specifications 159
7.5.2 pll controller register description(s) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com a summary of the pll controller registers is shown in table 7-12 . for more details, see the tms320dm646x dmsoc arm subsystem reference guide (literature number spruep9 ). table 7-12. pll and reset controller registers hex address range acronym register name pll1 controller registers 0x01c4 0800 pid peripheral id register 0x01c4 08e4 rstype reset type register 0x01c4 0900 pllctl pll controller 1 pll control register 0x01c4 0910 pllm pll controller 1 pll multiplier control register 0x01c4 0918 plldiv1 pll controller 1 divider 1 register (sysclk1) 0x01c4 091c plldiv2 pll controller 1 divider 2 register (sysclk2) 0x01c4 0920 plldiv3 pll controller 1 divider 3 register (sysclk3) 0x01c4 0928 ? reserved 0x01c4 092c bpdiv pll controller 1 bypass control-divider register (sysclkbp) 0x01c4 0938 pllcmd pll controller 1 command register 0x01c4 093c pllstat pll controller 1 status register (shows pllc1 pllctl status) pll controller 1 clock align control register 0x01c4 0940 alnctl (indicates which sysclks need to be aligned for proper device operation) pll controller 1 plldiv divider ratio change status register 0x01c4 0944 dchange (indicates if sysclk divide ratio has been modified) 0x01c4 0948 cken pll controller 1 clock enable control register 0x01c4 094c ckstat pll controller 1 clock status register (for all clocks except sysclkx) 0x01c4 0950 systat pll controller 1 sysclk status register (indicates sysclk on/off status) 0x01c4 0960 plldiv4 pll controller 1 divider 4 register (sysclk4) 0x01c4 0964 plldiv5 pll controller 1 divider 5 register (sysclk5) 0x01c4 0968 plldiv6 pll controller 1 divider 6 register (sysclk6) 0x01c4 096c ? reserved 0x01c4 0970 plldiv8 pll controller 1 divider 8 register (sysclk8) 0x01c4 0974 plldiv9 pll controller 1 divider 9 register (sysclk9) pll2 controller registers 0x01c4 0c00 pid peripheral id register 0x01c4 0d00 pllctl pll controller 2 pll control register 0x01c4 0d10 pllm pll controller 2 pll multiplier control register 0x01c4 0d18 plldiv1 pll controller 2 divider 1 register (pll2_sysclk1 ddr2 phy) 0x01c4 0d28 ? reserved 0x01c4 0d38 pllcmd pll controller 2 command register 0x01c4 0d3c pllstat pll controller 2 status register (shows pllc2 pllctl status) pll controller 2 clock align control register 0x01c4 0d40 alnctl (indicates which sysclks need to be aligned for proper device operation) pll controller 2 plldiv divider ratio change status register 0x01c4 0d44 dchange (indicates if sysclk divide ratio has been modified) 0x01c4 0d48 cken pll controller 2 clock enable control register 0x01c4 0d4c ckstat pll controller 2 clock status register (for all clocks except sysclkx) 0x01c4 0d50 systat pll controller 2 sysclk status register (indicates sysclk on/off status) 0x01c4 0d54 - 0x01c4 0fff ? reserved peripheral information and electrical specifications 160 submit documentation feedback
7.5.3 clock pll considerations with external clock sources 7.5.4 output clocks (clkout0, audio_clk1, audio_clk0) - clock select logic tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 if the internal oscillator is bypassed, to minimize the clock jitter a single clean power supply should power both the dm6467 device and the external clock oscillator circuit. the minimum clkin rise and fall times should also be observed. for the input clock timing requirements, see section 7.5.5 , clock pll electrical data/timing (input and output clocks). rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source must meet the device requirements in this data manual (see section 6.3 , electrical characteristics over recommended ranges of supply voltage and operating temperature, and section 7.5.5 , clock pll electrical data/timing (input and output clocks). the dm6467 includes a selectable general-purpose clock output (clkout0) [see figure 7-13 ] and two selectable audio output clocks (audio_clk0 and audio_clk1) for synchronizing external audio devices with the on-chip system or video clocks [see figure 7-14 and figure 7-15 ]. the source for these output clocks is controlled by the clkctl register (0x01c4 005c). for more detailed information on the clkctl register, see section 4.3.3 , clock and oscillator control. figure 7-13. clkout0 source selection submit documentation feedback peripheral information and electrical specifications 161 pll controller 1 0101 01000001 0011 10101001 0110 10000000 clkctl.clkout aux_mxi/aux_clkin dev_mxi/dev_clkin clkout0 plldiv9 (/6 prog) aux_mxisysclk9 sysclk8 plldiv8 (/8 prog) sysclk6 plldiv6 (/8 prog) sysclk5 plldiv5 (/8 prog) plldiv4 (/6 prog) sysclk4sysclk3 plldiv3 (/4 fixed) auxclk
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com figure 7-14. audio_clk0 source selection figure 7-15. audio_clk1 source selection 162 peripheral information and electrical specifications submit documentation feedback 0110 01010010 0100 1001 0111 10000000 clkctl.aud_clk1 gp[4]/stc_clkin aux_mxi/aux_clkin audio_clk1 stc_clkinaux_mxi vp0_clkin3vp0_clkin2 vp0_clkin1 vp0_clkin0 crg0_vcxi 1 0 gp[2] urxd2/crg1_vcxi/gp[39]/crg0_vcxi 11x 10x ucts2/usd2/crg0_vcxi/gp[42]/ts1_ptso 0001 auxclk pll controller 1 pinmux0.audck1 pinmux0.crgmux 0011 crg1_vcxi vp_clkin3/ts1_clko vp_clkin2 vp_clkin1 vp_clkin0 urxd2/crg1_vcxi/gp[39]/crg0_vcxi dev_mxi/dev_clkin 0110 01010010 0100 1001 0111 10000000 clkctl.aud_clk0 gp[4]/stc_clkin aux_mxi/aux_clkin audio_clk0 stc_clkinaux_mxi vp0_clkin3vp0_clkin2 vp0_clkin1 vp0_clkin0 crg0_vcxi 1 0 gp[3] urxd2/crg1_vcxi/gp[39]/crg0_vcxi 11x 10x ucts2/usd2/crg0_vcxi/gp[42]/ts1_ptso 0001 auxclk pll controller 1 pinmux0.audck0 pinmux0.crgmux 0011 crg1_vcxi vp_clkin3/ts1_clko vp_clkin2 vp_clkin1 vp_clkin0 urxd2/crg1_vcxi/gp[39]/crg0_vcxi dev_mxi/dev_clkin
7.5.5 clock pll electrical data/timing (input and output clocks) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-13. timing requirements for dev_mxi/dev_clkin (1) (2) (3) (4) (see figure 7-16 ) -594, -729 no. unit min nom max 1 t c(dmxi) cycle time, dev_mxi/dev_clkin 33. 33 37. 037 50 ns 2 t w(dmxih) pulse duration, dev_mxi/dev_clkin high 0.45c 0.55c ns 3 t w(dmxil) pulse duration, dev_mxi/dev_clkin low 0.45c 0.55c ns 4 t t(dmxi) transition time, dev_mxi/dev_clkin 7 ns 5 t j(dmxi) period jitter, dev_mxi/dev_clkin 0.02c ns (1) the dev_mxi/dev_clkin frequency and pll multiply factor should be chosen such that the resulting clock frequency is within the specific range for cpu operating frequency. for example, for a -594 speed device with a 27-mhz dev_clkin frequency, the pll multiply factor should be 22 and for a -729 speed device with a 27-mhz dev_clkin frequency, the pll multiply factor should be 27. (2) the reference points for the rise and fall transitions are measured at v il max and v ih min. (3) for more details on the pll multiplier factors, see the tms320dm646x dmsoc arm subsystem reference guide (literature number spruep9 ). (4) c = dev_clkin cycle time in ns. for example, when dev_mxi/dev_clkin frequency is 27 mhz, use c = 37. 037 ns. figure 7-16. dev_mxi/dev_clkin timing submit documentation feedback peripheral information and electrical specifications 163 dev_mxi/ dev_clkin 2 3 4 4 5 1 1
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-14. timing requirements for aux_mxi/aux_clkin (1) (2) (3) (see figure 7-17 ) -594, -729 no. unit min nom max 1 t c(amxi) cycle time, aux_mxi/aux_clkin 41. 6 or 20.8 3 (4) ns 2 t w(amxih) pulse duration, aux_mxi/aux_clkin high 0.45c 0.55c ns 3 t w(amxil) pulse duration, aux_mxi/aux_clkin low 0.45c 0.55c ns 4 t t(amxi) transition time, aux_mxi/aux_clkin 7 ns 5 t j(amxi) period jitter, aux_mxi/aux_clkin 0.02c ns 6 s f frequency stability, aux_mxi/aux_clkin (4) 50 ppm (1) the reference points for the rise and fall transitions are measured at v il max and v ih min. (2) for more details on the pll, see the tms320dm646x dmsoc universal serial bus (usb) controller user's guide (literature number spruer7 ). (3) c = dev_clkin cycle time in ns. for example, when aux_mxi/aux_clkin frequency is 24 mhz, use c = 41. 6 ns and when aux_mxi/aux_clkin frequency is 48 mhz, use c = 20.8 3 ns. (4) if the usb is used, a 24-mhz, 50-ppm crystal is recommended. figure 7-17. aux_mxi/aux_clkin timing 164 peripheral information and electrical specifications submit documentation feedback aux_mxi/ aux_clkin 2 3 4 4 5 1 1
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-15. switching characteristics over recommended operating conditions for clkout0 (1) (2) (see figure 7-18 ) -594, -729 no. parameter unit min max 1 t c(clkout0) cycle time, clkout0 6.734 296. 296 ns 2 t w(clkout0h) pulse duration, clkout0 high 0.4p 0.6p ns 3 t w(clkout0l) pulse duration, clkout0 low 0.4p 0.6p ns 4 t t(clkout0) transition time, clkout0 0.05p ns (1) the reference points for the rise and fall transitions are measured at v ol max and v oh min. (2) p = 1/clkout0 clock frequency in nanoseconds (ns). for example, when clkout0 frequency is 27 mhz, use p = 37. 037 ns. figure 7-18. clkout0 timing submit documentation feedback peripheral information and electrical specifications 165 clkout0 (divide-by-1) 1 2 4 4 3
7.6 enhanced direct memory access (edma3) controller 7.6.1 edma3 channel synchronization events tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the edma controller handles all data transfers between memories and the device slave peripherals on the dm6467 device. these data transfers include cache servicing, non-cacheable memory accesses, user-programmed data transfers, and host accesses. these are summarized as follows: transfer to/from on-chip memories ? arm926 tcm ? dsp l1d memory ? dsp l2 memory transfer to/from external storage ? ddr2 sdram ? nand flash ? asynchronous emif (emifa) ? ata transfer to/from peripherals/hosts ? vlynq ? hpi ? mcasp0/1 ? spi ? i2c ? pwm0/1 ? uart0/1/2 ? pci the edma supports two addressing modes: constant addressing and increment addressing. on the dm6467, constant addressing mode is not supported by any peripheral or internal memory. for more information on these two addressing modes, see the tms320dm646x dmsoc enhanced direct memory access (edma) controller user?s guide (literature number sprueq5 ). the dm6467 device supports a programmable default burst size feature. the default burst size of each edma3 transfer controller (tc) is configured via the edma transfer controller default burst size configuration register (edmatccfg). for more detailed information on the edmatccfg register, see section 4.6.2 , peripheral selection after device reset. the edma supports up to 64 edma channels which service peripheral devices and external memory. table 7-16 lists the source of edma synchronization events associated with each of the programmable edma channels. for the dm6467 device, the association of an event to a channel is fixed; each of the edma channels has one specific event associated with it. these specific events are captured in the edma event registers (er, erh) even if the events are disabled by the edma event enable registers (eer, eerh). for more detailed information on the edma module and how edma events are enabled, captured, processed, linked, chained, and cleared, etc., see the tms320dm646x dmsoc enhanced direct memory access (edma) controller user?s guide (literature number sprueq5 ) table 7-16. dm6467 edma channel synchronization events (1) edma event name event description channel 0-3 ? reserved 4 axevte0 mcasp0 transmit event even (1) in addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. for more detailed information on edma event-transfer chaining, see the tms320dm646x dmsoc enhanced direct memory access (edma) controller user's guide (literature number sprueq5 ). peripheral information and electrical specifications 166 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-16. dm6467 edma channel synchronization events (continued) edma event name event description channel 5 axevto0 mcasp0 transmit event odd 6 axevt0 mcasp0 transmit event 7 arevte0 mcasp0 receive event even 8 arevto0 mcasp0 receive event odd 9 arevt0 mcasp0 receive event 10 axevte1 mcasp1 transmit event even 11 axevto1 mcasp1 transmit event odd 12 axevt1 mcasp1 transmit event 13-15 ? reserved 16 spixevt spi transmit event 17 spirevt spi receive event 18 urxevt0 uart 0 receive event 19 utxevt0 uart 0 transmit event 20 urxevt1 uart 1 receive event 21 utxevt1 uart 1 transmit event 22 urxevt2 uart 2 receive event 23 utxevt2 uart 2 transmit event 24-27 ? reserved 28 icrevt i2c receive event 29 icxevt i2c transmit event 30-31 ? reserved [unused] 32 gpint0 gpio 0 interrupt event 33 gpint1 gpio 1 interrupt event 34 gpint2 gpio 2 interrupt event 35 gpint3 gpio 3 interrupt event 36 gpint4 gpio 4 interrupt event 37 gpint5 gpio 5 interrupt event 38 gpint6 gpio 6 interrupt event 39 gpint7 gpio 7 interrupt event 40 gpbnkint0 gpio bank 0 interrupt event 41 gpbnkint1 gpio bank 1 interrupt event 42 gpbnkint2 gpio bank 2 interrupt event 43 cp_ecdcmp1 hdvicp1 ecdcmp interrupt event 44 cp_mc1 hdvicp1 mc interrupt event 45 cp_bs1 hdvicp1 bs interrupt event 46 cp_calc1 hdvicp1 calc interrupt event 47 cp_lpf1 hdvicp1 lpf interrupt event 48 tevtl0 timer 0 event low interrupt 49 tevth0 timer 0 event high interrupt 50 tevtl1 timer 1 event low interrupt 51 tevth1 timer 1 event high interrupt 52 pwm0 pwm 0 interrupt event 53 pwm1 pwm 1 interrupt event 54-56 ? reserved 57 cp_me0 hdvicp0 me interrupt event 58 cp_ipe0 hdvicp0 ipe interrupt event submit documentation feedback peripheral information and electrical specifications 167
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-16. dm6467 edma channel synchronization events (continued) edma event name event description channel 59 cp_ecdcmp0 hdvicp0 ecdcmp interrupt event 60 cp_mc0 hdvicp0 mc interrupt event 61 cp_bs0 hdvicp0 bs interrupt event 62 cp_calc0 hdvicp0 calc interrupt event 63 cp_lpf0 hdvicp0 lpf interrupt event peripheral information and electrical specifications 168 submit documentation feedback
7.6.2 edma peripheral register description(s) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-17 lists the edma registers, their corresponding acronyms, and dm6467 device memory locations. table 7-17. dm6467 edma registers hex address range acronym register name channel controller registers 0x01c0 0000 pid peripheral identification register 0x01c0 0004 cccfg edma3cc configuration register 0x01c0 0008 - 0x01c0 00ff ? reserved global registers 0x01c0 0100 dchmap0 dma channel 0 mapping to param register 0x01c0 0104 dchmap1 dma channel 1 mapping to param register 0x01c0 0108 dchmap2 dma channel 2 mapping to param register 0x01c0 010c dchmap3 dma channel 3 mapping to param register 0x01c0 0110 dchmap4 dma channel 4 mapping to param register 0x01c0 0114 dchmap5 dma channel 5 mapping to param register 0x01c0 0118 dchmap6 dma channel 6 mapping to param register 0x01c0 011c dchmap7 dma channel 7 mapping to param register 0x01c0 0120 dchmap8 dma channel 8 mapping to param register 0x01c0 0124 dchmap9 dma channel 9 mapping to param register 0x01c0 0128 dchmap10 dma channel 10 mapping to param register 0x01c0 012c dchmap11 dma channel 11 mapping to param register 0x01c0 0130 dchmap12 dma channel 12 mapping to param register 0x01c0 0134 dchmap13 dma channel 13 mapping to param register 0x01c0 0138 dchmap14 dma channel 14 mapping to param register 0x01c0 013c dchmap15 dma channel 15 mapping to param register 0x01c0 0140 dchmap16 dma channel 16 mapping to param register 0x01c0 0144 dchmap17 dma channel 17 mapping to param register 0x01c0 0148 dchmap18 dma channel 18 mapping to param register 0x01c0 014c dchmap19 dma channel 19 mapping to param register 0x01c0 0150 dchmap20 dma channel 20 mapping to param register 0x01c0 0154 dchmap21 dma channel 21 mapping to param register 0x01c0 0158 dchmap22 dma channel 22 mapping to param register 0x01c0 015c dchmap23 dma channel 23 mapping to param register 0x01c0 0160 dchmap24 dma channel 24 mapping to param register 0x01c0 0164 dchmap25 dma channel 25 mapping to param register 0x01c0 0168 dchmap26 dma channel 26 mapping to param register 0x01c0 016c dchmap27 dma channel 27 mapping to param register 0x01c0 0170 dchmap28 dma channel 28 mapping to param register 0x01c0 0174 dchmap29 dma channel 29 mapping to param register 0x01c0 0178 dchmap30 dma channel 30 mapping to param register 0x01c0 017c dchmap31 dma channel 31 mapping to param register 0x01c0 0180 dchmap32 dma channel 32 mapping to param register 0x01c0 0184 dchmap33 dma channel 33 mapping to param register 0x01c0 0188 dchmap34 dma channel 34 mapping to param register 0x01c0 018c dchmap35 dma channel 35 mapping to param register 0x01c0 0190 dchmap36 dma channel 36 mapping to param register 0x01c0 0194 dchmap37 dma channel 37 mapping to param register submit documentation feedback peripheral information and electrical specifications 169
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-17. dm6467 edma registers (continued) hex address range acronym register name 0x01c0 0198 dchmap38 dma channel 38 mapping to param register 0x01c0 019c dchmap39 dma channel 39 mapping to param register 0x01c0 01a0 dchmap40 dma channel 40 mapping to param register 0x01c0 01a4 dchmap41 dma channel 41 mapping to param register 0x01c0 01a8 dchmap42 dma channel 42 mapping to param register 0x01c0 01ac dchmap43 dma channel 43 mapping to param register 0x01c0 01b0 dchmap44 dma channel 44 mapping to param register 0x01c0 01b4 dchmap45 dma channel 45 mapping to param register 0x01c0 01b8 dchmap46 dma channel 46 mapping to param register 0x01c0 01bc dchmap47 dma channel 47 mapping to param register 0x01c0 01c0 dchmap48 dma channel 48 mapping to param register 0x01c0 01c4 dchmap49 dma channel 49 mapping to param register 0x01c0 01c8 dchmap50 dma channel 50 mapping to param register 0x01c0 01cc dchmap51 dma channel 51 mapping to param register 0x01c0 01d0 dchmap52 dma channel 52 mapping to param register 0x01c0 01d4 dchmap53 dma channel 53 mapping to param register 0x01c0 01d8 dchmap54 dma channel 54 mapping to param register 0x01c0 01dc dchmap55 dma channel 55 mapping to param register 0x01c0 01e0 dchmap56 dma channel 56 mapping to param register 0x01c0 01e4 dchmap57 dma channel 57 mapping to param register 0x01c0 01e8 dchmap58 dma channel 58 mapping to param register 0x01c0 01ec dchmap59 dma channel 59 mapping to param register 0x01c0 01f0 dchmap60 dma channel 60 mapping to param register 0x01c0 01f4 dchmap61 dma channel 61 mapping to param register 0x01c0 01f8 dchmap62 dma channel 62 mapping to param register 0x01c0 01fc dchmap63 dma channel 63 mapping to param register 0x01c0 0200 qchmap0 qdma channel 0 mapping to param register 0x01c0 0204 qchmap1 qdma channel 1 mapping to param register 0x01c0 0208 qchmap2 qdma channel 2 mapping to param register 0x01c0 020c qchmap3 qdma channel 3 mapping to param register 0x01c0 0210 qchmap4 qdma channel 4 mapping to param register 0x01c0 0214 qchmap5 qdma channel 5 mapping to param register 0x01c0 0218 qchmap6 qdma channel 6 mapping to param register 0x01c0 021c qchmap7 qdma channel 7 mapping to param register 0x01c0 0220 - 0x01c0 023f ? reserved 0x01c0 0240 dmaqnum0 dma queue number register 0 (channels 00 to 07) 0x01c0 0244 dmaqnum1 dma queue number register 1 (channels 08 to 15) 0x01c0 0248 dmaqnum2 dma queue number register 2 (channels 16 to 23) 0x01c0 024c dmaqnum3 dma queue number register 3 (channels 24 to 31) 0x01c0 0250 dmaqnum4 dma queue number register 4 (channels 32 to 39) 0x01c0 0254 dmaqnum5 dma queue number register 5 (channels 40 to 47) 0x01c0 0258 dmaqnum6 dma queue number register 6 (channels 48 to 55) 0x01c0 025c dmaqnum7 dma queue number register 7 (channels 56 to 63) 0x01c0 0260 qdmaqnum cc qdma queue number 0x01c0 0264 - 0x01c0 0283 ? reserved 0x01c0 0284 quepri queue priority register 0x01c0 0288 - 0x01c0 02ff ? reserved peripheral information and electrical specifications 170 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-17. dm6467 edma registers (continued) hex address range acronym register name 0x01c0 0300 emr event missed register 0x01c0 0304 emrh event missed register high 0x01c0 0308 emcr event missed clear register 0x01c0 030c emcrh event missed clear register high 0x01c0 0310 qemr qdma event missed register 0x01c0 0314 qemcr qdma event missed clear register 0x01c0 0318 ccerr edma3cc error register 0x01c0 031c ccerrclr edma3cc error clear register 0x01c0 0320 eeval error evaluate register 0x01c0 0324 - 0x01c0 033f ? reserved 0x01c0 0340 drae0 dma region access enable register for region 0 0x01c0 0344 draeh0 dma region access enable register high for region 0 0x01c0 0348 drae1 dma region access enable register for region 1 0x01c0 034c draeh1 dma region access enable register high for region 1 0x01c0 0350- 0x01c0 035f ? reserved 0x01c0 0360 drae4 dma region access enable register for region 4 0x01c0 0364 draeh4 dma region access enable register high for region 4 0x01c0 0368 drae5 dma region access enable register for region 5 0x01c0 036c draeh5 dma region access enable register high for region 5 0x01c0 0370 drae6 dma region access enable register for region 6 0x01c0 0374 draeh6 dma region access enable register high for region 6 0x01c0 0378 drae7 dma region access enable register for region 7 0x01c0 037c draeh7 dma region access enable register high for region 7 0x01c0 0380 qrae0 qdma region access enable register for region 0 0x01c0 0384 qrae1 qdma region access enable register for region 1 0x01c0 0388 - 0x01c0 038f ? reserved 0x01c0 0390 qrae4 qdma region access enable register for region 4 0x01c0 0394 qrae5 qdma region access enable register for region 5 0x01c0 0398 qrae6 qdma region access enable register for region 6 0x01c0 039c qrae7 qdma region access enable register for region 7 0x01c0 03a0 - 0x01c0 03ff ? reserved 0x01c0 0400 q0e0 event q0 entry 0 register 0x01c0 0404 q0e1 event q0 entry 1 register 0x01c0 0408 q0e2 event q0 entry 2 register 0x01c0 040c q0e3 event q0 entry 3 register 0x01c0 0410 q0e4 event q0 entry 4 register 0x01c0 0414 q0e5 event q0 entry 5 register 0x01c0 0418 q0e6 event q0 entry 6 register 0x01c0 041c q0e7 event q0 entry 7 register 0x01c0 0420 q0e8 event q0 entry 8 register 0x01c0 0424 q0e9 event q0 entry 9 register 0x01c0 0428 q0e10 event q0 entry 10 register 0x01c0 042c q0e11 event q0 entry 11 register 0x01c0 0430 q0e12 event q0 entry 12 register 0x01c0 0434 q0e13 event q0 entry 13 register 0x01c0 0438 q0e14 event q0 entry 14 register 0x01c0 043c q0e15 event q0 entry 15 register submit documentation feedback peripheral information and electrical specifications 171
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-17. dm6467 edma registers (continued) hex address range acronym register name 0x01c0 0440 q1e0 event q1 entry 0 register 0x01c0 0444 q1e1 event q1 entry 1 register 0x01c0 0448 q1e2 event q1 entry 2 register 0x01c0 044c q1e3 event q1 entry 3 register 0x01c0 0450 q1e4 event q1 entry 4 register 0x01c0 0454 q1e5 event q1 entry 5 register 0x01c0 0458 q1e6 event q1 entry 6 register 0x01c0 045c q1e7 event q1 entry 7 register 0x01c0 0460 q1e8 event q1 entry 8 register 0x01c0 0464 q1e9 event q1 entry 9 register 0x01c0 0468 q1e10 event q1 entry 10 register 0x01c0 046c q1e11 event q1 entry 11 register 0x01c0 0470 q1e12 event q1 entry 12 register 0x01c0 0474 q1e13 event q1 entry 13 register 0x01c0 0478 q1e14 event q1 entry 14 register 0x01c0 047c q1e15 event q1 entry 15 register 0x01c0 0480 q2e0 event q2 entry 0 register 0x01c0 0484 q2e1 event q2 entry 1 register 0x01c0 0488 q2e2 event q2 entry 2 register 0x01c0 048c q2e3 event q2 entry 3 register 0x01c0 0490 q2e4 event q2 entry 4 register 0x01c0 0494 q2e5 event q2 entry 5 register 0x01c0 0498 q2e6 event q2 entry 6 register 0x01c0 049c q2e7 event q2 entry 7 register 0x01c0 04a0 q2e8 event q2 entry 8 register 0x01c0 04a4 q2e9 event q2 entry 9 register 0x01c0 04a8 q2e10 event q2 entry 10 register 0x01c0 04ac q2e11 event q2 entry 11 register 0x01c0 04b0 q2e12 event q2 entry 12 register 0x01c0 04b4 q2e13 event q2 entry 13 register 0x01c0 04b8 q2e14 event q2 entry 14 register 0x01c0 04bc q2e15 event q2 entry 15 register 0x01c0 04c0 q3e0 event q3 entry 0 register 0x01c0 04c4 q3e1 event q3 entry 1 register 0x01c0 04c8 q3e2 event q3 entry 2 register 0x01c0 04cc q3e3 event q3 entry 3 register 0x01c0 04d0 q3e4 event q3 entry 4 register 0x01c0 04d4 q3e5 event q3 entry 5 register 0x01c0 04d8 q3e6 event q3 entry 6 register 0x01c0 04dc q3e7 event q3 entry 7 register 0x01c0 04e0 q3e8 event q3 entry 8 register 0x01c0 04e4 q3e9 event q3 entry 9 register 0x01c0 04e8 q3e10 event q3 entry 10 register 0x01c0 04ec q3e11 event q3 entry 11 register 0x01c0 04f0 q3e12 event q3 entry 12 register 0x01c0 04f4 q3e13 event q3 entry 13 register 0x01c0 04f8 q3e14 event q3 entry 14 register peripheral information and electrical specifications 172 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-17. dm6467 edma registers (continued) hex address range acronym register name 0x01c0 04fc q3e15 event q3 entry 15 register 0x01c0 0500 - 0x01c0 05ff ? reserved 0x01c0 0600 qstat0 queue 0 status register 0x01c0 0604 qstat1 queue 1 status register 0x01c0 0608 qstat2 queue 2 status register 0x01c0 060c qstat3 queue 3 status register 0x01c0 0610 - 0x01c0 061f ? reserved 0x01c0 0620 qwmthra queue watermark threshold a register for q[3:0] 0x01c0 0624 - 0x01c0 063f ? reserved 0x01c0 0640 ccstat edma3cc status register 0x01c0 0644 - 0x01c0 0fff ? reserved global channel registers 0x01c0 1000 er event register 0x01c0 1004 erh event register high 0x01c0 1008 ecr event clear register 0x01c0 100c ecrh event clear register high 0x01c0 1010 esr event set register 0x01c0 1014 esrh event set register high 0x01c0 1018 cer chained event register 0x01c0 101c cerh chained event register high 0x01c0 1020 eer event enable register 0x01c0 1024 eerh event enable register high 0x01c0 1028 eecr event enable clear register 0x01c0 102c eecrh event enable clear register high 0x01c0 1030 eesr event enable set register 0x01c0 1034 eesrh event enable set register high 0x01c0 1038 ser secondary event register 0x01c0 103c serh secondary event register high 0x01c0 1040 secr secondary event clear register 0x01c0 1044 secrh secondary event clear register high 0x01c0 1048 - 0x01c0 104f ? reserved 0x01c0 1050 ier interrupt enable register 0x01c0 1054 ierh interrupt enable register high 0x01c0 1058 iecr interrupt enable clear register 0x01c0 105c iecrh interrupt enable clear register high 0x01c0 1060 iesr interrupt enable set register 0x01c0 1064 iesrh interrupt enable set register high 0x01c0 1068 ipr interrupt pending register 0x01c0 106c iprh interrupt pending register high 0x01c0 1070 icr interrupt clear register 0x01c0 1074 icrh interrupt clear register high 0x01c0 1078 ieval interrupt evaluate register 0x01c0 107c - 0x01c0 107f ? reserved 0x01c0 1080 qer qdma event register 0x01c0 1084 qeer qdma event enable register 0x01c0 1088 qeecr qdma event enable clear register 0x01c0 108c qeesr qdma event enable set register submit documentation feedback peripheral information and electrical specifications 173
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-17. dm6467 edma registers (continued) hex address range acronym register name 0x01c0 1090 qser qdma secondary event register 0x01c0 1094 qsecr qdma secondary event clear register 0x01c0 1098 - 0x01c0 1fff ? reserved shadow region 0 channel registers 0x01c0 2000 er event register 0x01c0 2004 erh event register high 0x01c0 2008 ecr event clear register 0x01c0 200c ecrh event clear register high 0x01c0 2010 esr event set register 0x01c0 2014 esrh event set register high 0x01c0 2018 cer chained event register 0x01c0 201c cerh chained event register high 0x01c0 2020 eer event enable register 0x01c0 2024 eerh event enable register high 0x01c0 2028 eecr event enable clear register 0x01c0 202c eecrh event enable clear register high 0x01c0 2030 eesr event enable set register 0x01c0 2034 eesrh event enable set register high 0x01c0 2038 ser secondary event register 0x01c0 203c serh secondary event register high 0x01c0 2040 secr secondary event clear register 0x01c0 2044 secrh secondary event clear register high 0x01c0 2048 - 0x01c0 204f ? reserved 0x01c0 2050 ier interrupt enable register 0x01c0 2054 ierh interrupt enable register high 0x01c0 2058 iecr interrupt enable clear register 0x01c0 205c iecrh interrupt enable clear register high 0x01c0 2060 iesr interrupt enable set register 0x01c0 2064 iesrh interrupt enable set register high 0x01c0 2068 ipr interrupt pending register 0x01c0 206c iprh interrupt pending register high 0x01c0 2070 icr interrupt clear register 0x01c0 2074 icrh interrupt clear register high 0x01c0 2078 ieval interrupt evaluate register 0x01c0 207c - 0x01c0 207f ? reserved 0x01c0 2080 qer qdma event register 0x01c0 2084 qeer qdma event enable register 0x01c0 2088 qeecr qdma event enable clear register 0x01c0 208c qeesr qdma event enable set register 0x01c0 2090 qser qdma secondary event register 0x01c0 2094 qsecr qdma secondary event clear register 0x01c0 2098 - 0x01c0 21ff ? reserved shadow region 1 channel registers 0x01c0 2200 er event register 0x01c0 2204 erh event register high 0x01c0 2208 ecr event clear register 0x01c0 220c ecrh event clear register high peripheral information and electrical specifications 174 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-17. dm6467 edma registers (continued) hex address range acronym register name 0x01c0 2210 esr event set register 0x01c0 2214 esrh event set register high 0x01c0 2218 cer chained event register 0x01c0 221c cerh chained event register high 0x01c0 2220 eer event enable register 0x01c0 2224 eerh event enable register high 0x01c0 2228 eecr event enable clear register 0x01c0 222c eecrh event enable clear register high 0x01c0 2230 eesr event enable set register 0x01c0 2234 eesrh event enable set register high 0x01c0 2238 ser secondary event register 0x01c0 223c serh secondary event register high 0x01c0 2240 secr secondary event clear register 0x01c0 2244 secrh secondary event clear register high 0x01c0 2248 - 0x01c0 224f ? reserved 0x01c0 2250 ier interrupt enable register 0x01c0 2254 ierh interrupt enable register high 0x01c0 2258 iecr interrupt enable clear register 0x01c0 225c iecrh interrupt enable clear register high 0x01c0 2260 iesr interrupt enable set register 0x01c0 2264 iesrh interrupt enable set register high 0x01c0 2268 ipr interrupt pending register 0x01c0 226c iprh interrupt pending register high 0x01c0 2270 icr interrupt clear register 0x01c0 2274 icrh interrupt clear register high 0x01c0 2278 ieval interrupt evaluate register 0x01c0 227c - 0x01c0 227f ? reserved 0x01c0 2280 qer qdma event register 0x01c0 2284 qeer qdma event enable register 0x01c0 2288 qeecr qdma event enable clear register 0x01c0 228c qeesr qdma event enable set register 0x01c0 2290 qser qdma secondary event register 0x01c0 2294 qsecr qdma secondary event clear register 0x01c0 2298 - 0x01c0 23ff ? reserved 0x01c0 2400 - 0x01c0 25ff ? reserved 0x01c0 2600 - 0x01c0 27ff ? reserved shadow region 4 channel registers 0x01c0 2800 er event register 0x01c0 2804 erh event register high 0x01c0 2808 ecr event clear register 0x01c0 280c ecrh event clear register high 0x01c0 2810 esr event set register 0x01c0 2814 esrh event set register high 0x01c0 2818 cer chained event register 0x01c0 281c cerh chained event register high 0x01c0 2820 eer event enable register 0x01c0 2824 eerh event enable register high submit documentation feedback peripheral information and electrical specifications 175
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-17. dm6467 edma registers (continued) hex address range acronym register name 0x01c0 2828 eecr event enable clear register 0x01c0 282c eecrh event enable clear register high 0x01c0 2830 eesr event enable set register 0x01c0 2834 eesrh event enable set register high 0x01c0 2838 ser secondary event register 0x01c0 283c serh secondary event register high 0x01c0 2840 secr secondary event clear register 0x01c0 2844 secrh secondary event clear register high 0x01c0 2848 - 0x01c0 284f ? reserved 0x01c0 2850 ier interrupt enable register 0x01c0 2854 ierh interrupt enable register high 0x01c0 2858 iecr interrupt enable clear register 0x01c0 285c iecrh interrupt enable clear register high 0x01c0 2860 iesr interrupt enable set register 0x01c0 2864 iesrh interrupt enable set register high 0x01c0 2868 ipr interrupt pending register 0x01c0 286c iprh interrupt pending register high 0x01c0 2870 icr interrupt clear register 0x01c0 2874 icrh interrupt clear register high 0x01c0 2878 ieval interrupt evaluate register 0x01c0 287c - 0x01c0 287f ? reserved 0x01c0 2880 qer qdma event register 0x01c0 2884 qeer qdma event enable register 0x01c0 2888 qeecr qdma event enable clear register 0x01c0 288c qeesr qdma event enable set register 0x01c0 2890 qser qdma secondary event register 0x01c0 2894 qsecr qdma secondary event clear register 0x01c0 2898 - 0x01c0 29ff ? reserved shadow region 5 channel registers 0x01c0 2a00 er event register 0x01c0 2a04 erh event register high 0x01c0 2a08 ecr event clear register 0x01c0 2a0c ecrh event clear register high 0x01c0 2a10 esr event set register 0x01c0 2a14 esrh event set register high 0x01c0 2a18 cer chained event register 0x01c0 2a1c cerh chained event register high 0x01c0 2a20 eer event enable register 0x01c0 2a24 eerh event enable register high 0x01c0 2a28 eecr event enable clear register 0x01c0 2a2c eecrh event enable clear register high 0x01c0 2a30 eesr event enable set register 0x01c0 2a34 eesrh event enable set register high 0x01c0 2a38 ser secondary event register 0x01c0 2a3c serh secondary event register high 0x01c0 2a40 secr secondary event clear register 0x01c0 2a44 secrh secondary event clear register high peripheral information and electrical specifications 176 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-17. dm6467 edma registers (continued) hex address range acronym register name 0x01c0 2a48 - 0x01c0 2a4f ? reserved 0x01c0 2a50 ier interrupt enable register 0x01c0 2a54 ierh interrupt enable register high 0x01c0 2a58 iecr interrupt enable clear register 0x01c0 2a5c iecrh interrupt enable clear register high 0x01c0 2a60 iesr interrupt enable set register 0x01c0 2a64 iesrh interrupt enable set register high 0x01c0 2a68 ipr interrupt pending register 0x01c0 2a6c iprh interrupt pending register high 0x01c0 2a70 icr interrupt clear register 0x01c0 2a74 icrh interrupt clear register high 0x01c0 2a78 ieval interrupt evaluate register 0x01c0 2a7c - 0x01c0 2a7f ? reserved 0x01c0 2a80 qer qdma event register 0x01c0 2a84 qeer qdma event enable register 0x01c0 2a88 qeecr qdma event enable clear register 0x01c0 2a8c qeesr qdma event enable set register 0x01c0 2a90 qser qdma secondary event register 0x01c0 2a94 qsecr qdma secondary event clear register 0x01c0 2a98 - 0x01c0 2bff ? reserved shadow region 6 channel registers 0x01c0 2c00 er event register 0x01c0 2c04 erh event register high 0x01c0 2c08 ecr event clear register 0x01c0 2c0c ecrh event clear register high 0x01c0 2c10 esr event set register 0x01c0 2c14 esrh event set register high 0x01c0 2c18 cer chained event register 0x01c0 2c1c cerh chained event register high 0x01c0 2c20 eer event enable register 0x01c0 2c24 eerh event enable register high 0x01c0 2c28 eecr event enable clear register 0x01c0 2c2c eecrh event enable clear register high 0x01c0 2c30 eesr event enable set register 0x01c0 2c34 eesrh event enable set register high 0x01c0 2c38 ser secondary event register 0x01c0 2c3c serh secondary event register high 0x01c0 2c40 secr secondary event clear register 0x01c0 2c44 secrh secondary event clear register high 0x01c0 2c48 - 0x01c0 2c4f ? reserved 0x01c0 2c50 ier interrupt enable register 0x01c0 2c54 ierh interrupt enable register high 0x01c0 2c58 iecr interrupt enable clear register 0x01c0 2c5c iecrh interrupt enable clear register high 0x01c0 2c60 iesr interrupt enable set register 0x01c0 2c64 iesrh interrupt enable set register high 0x01c0 2c68 ipr interrupt pending register submit documentation feedback peripheral information and electrical specifications 177
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-17. dm6467 edma registers (continued) hex address range acronym register name 0x01c0 2c6c iprh interrupt pending register high 0x01c0 2c70 icr interrupt clear register 0x01c0 2c74 icrh interrupt clear register high 0x01c0 2c78 ieval interrupt evaluate register 0x01c0 2c7c - 0x01c0 2c7f ? reserved 0x01c0 2c80 qer qdma event register 0x01c0 2c84 qeer qdma event enable register 0x01c0 2c88 qeecr qdma event enable clear register 0x01c0 2c8c qeesr qdma event enable set register 0x01c0 2c90 qser qdma secondary event register 0x01c0 2c94 qsecr qdma secondary event clear register 0x01c0 2c98 - 0x01c0 2dff ? reserved shadow region 7 channel registers 0x01c0 2e00 er event register 0x01c0 2e04 erh event register high 0x01c0 2e08 ecr event clear register 0x01c0 2e0c ecrh event clear register high 0x01c0 2e10 esr event set register 0x01c0 2e14 esrh event set register high 0x01c0 2e18 cer chained event register 0x01c0 2e1c cerh chained event register high 0x01c0 2e20 eer event enable register 0x01c0 2e24 eerh event enable register high 0x01c0 2e28 eecr event enable clear register 0x01c0 2e2c eecrh event enable clear register high 0x01c0 2e30 eesr event enable set register 0x01c0 2e34 eesrh event enable set register high 0x01c0 2e38 ser secondary event register 0x01c0 2e3c serh secondary event register high 0x01c0 2e40 secr secondary event clear register 0x01c0 2e44 secrh secondary event clear register high 0x01c0 2e48 - 0x01c0 2e4f ? reserved 0x01c0 2e50 ier interrupt enable register 0x01c0 2e54 ierh interrupt enable register high 0x01c0 2e58 iecr interrupt enable clear register 0x01c0 2e5c iecrh interrupt enable clear register high 0x01c0 2e60 iesr interrupt enable set register 0x01c0 2e64 iesrh interrupt enable set register high 0x01c0 2e68 ipr interrupt pending register 0x01c0 2e6c iprh interrupt pending register high 0x01c0 2e70 icr interrupt clear register 0x01c0 2e74 icrh interrupt clear register high 0x01c0 2e78 ieval interrupt evaluate register 0x01c0 2e7c - 0x01c0 2e7f ? reserved 0x01c0 2e80 qer qdma event register 0x01c0 2e84 qeer qdma event enable register 0x01c0 2e88 qeecr qdma event enable clear register peripheral information and electrical specifications 178 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-17. dm6467 edma registers (continued) hex address range acronym register name 0x01c0 2e8c qeesr qdma event enable set register 0x01c0 2e90 qser qdma secondary event register 0x01c0 2e94 qsecr qdma secondary event clear register 0x01c0 2e98 - 0x01c0 2fff ? reserved 0x01c0 3000 - 0x01c0 3fff ? reserved 0x01c0 4000 - 0x01c0 7fff ? parameter set ram (see table 7-18 ) 0x01c0 8000 - 0x01c0 ffff ? reserved transfer controller 0 registers 0x01c1 0000 pid peripheral identification register 0x01c1 0004 tccfg edma3 tc0 configuration register 0x01c1 0008 - 0x01c1 00ff ? reserved 0x01c1 0100 tcstat edma3 tc0 channel status register 0x01c1 0104 - 0x01c1 0113 ? reserved 0x01c1 0114 - 0x01c1 011f ? reserved 0x01c1 0120 errstat edma3 tc0 error status register 0x01c1 0124 erren edma3 tc0 error enable register 0x01c1 0128 errclr edma3 tc0 error clear register 0x01c1 012c errdet edma3 tc0 error details register 0x01c1 0130 errcmd edma3 tc0 error interrupt command register 0x01c1 0134 - 0x01c1 013f ? reserved 0x01c1 0140 rdrate edma3 tc0 read command rate register 0x01c1 0144 - 0x01c1 01ff ? reserved 0x01c1 0200 - 0x01c1 023f ? reserved 0x01c1 0240 saopt edma3 tc0 source active options register 0x01c1 0244 sasrc edma3 tc0 source active source address register 0x01c1 0248 sacnt edma3 tc0 source active count register 0x01c1 024c sadst edma3 tc0 source active destination address register 0x01c1 0250 sabidx edma3 tc0 source active b-index register 0x01c1 0254 sampprxy edma3 tc0 source active memory protection proxy register 0x01c1 0258 sacntrld edma3 tc0 source active count reload register 0x01c1 025c sasrcbref edma3 tc0 source active source address b-reference register 0x01c1 0260 sadstbref edma3 tc0 source active destination address b-reference register 0x01c1 0264 - 0x01c1 027f ? reserved 0x01c1 0280 dfcntrld edma3 tc0 destination fifo set count reload register 0x01c1 0284 dfsrcbref edma3 tc0 destination fifo set source address b-reference register edma3 tc0 destination fifo set destination address b-reference 0x01c1 0288 dfdstbref register 0x01c1 028c - 0x01c1 02ff ? reserved 0x01c1 0300 dfopt0 edma3 tc0 destination fifo options register 0 0x01c1 0304 dfsrc0 edma3 tc0 destination fifo source address register 0 0x01c1 0308 dfcnt0 edma3 tc0 destination fifo count register 0 0x01c1 030c dfdst0 edma3 tc0 destination fifo destination address register 0 0x01c1 0310 dfbidx0 edma3 tc0 destination fifo b-index register 0 0x01c1 0314 dfmpprxy0 edma3 tc0 destination fifo memory protection proxy register 0 0x01c1 0318 - 0x01c1 033f ? reserved 0x01c1 0340 dfopt1 edma3 tc0 destination fifo options register 1 0x01c1 0344 dfsrc1 edma3 tc0 destination fifo source address register 1 submit documentation feedback peripheral information and electrical specifications 179
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-17. dm6467 edma registers (continued) hex address range acronym register name 0x01c1 0348 dfcnt1 edma3 tc0 destination fifo count register 1 0x01c1 034c dfdst1 edma3 tc0 destination fifo destination address register 1 0x01c1 0350 dfbidx1 edma3 tc0 destination fifo b-index register 1 0x01c1 0354 dfmpprxy1 edma3 tc0 destination fifo memory protection proxy register 1 0x01c1 0358 - 0x01c1 037f ? reserved 0x01c1 0380 dfopt2 edma3 tc0 destination fifo options register 2 0x01c1 0384 dfsrc2 edma3 tc0 destination fifo source address register 2 0x01c1 0388 dfcnt2 edma3 tc0 destination fifo count register 2 0x01c1 038c dfdst2 edma3 tc0 destination fifo destination address register 2 0x01c1 0390 dfbidx2 edma3 tc0 destination fifo b-index register 2 0x01c1 0394 dfmpprxy2 edma3 tc0 destination fifo memory protection proxy register 2 0x01c1 0398 - 0x01c1 03bf ? reserved 0x01c1 03c0 dfopt3 edma3 tc0 destination fifo options register 3 0x01c1 03c4 dfsrc3 edma3 tc0 destination fifo source address register 3 0x01c1 03c8 dfcnt3 edma3 tc0 destination fifo count register 3 0x01c1 03cc dfdst3 edma3 tc0 destination fifo destination address register 3 0x01c1 03d0 dfbidx3 edma3 tc0 destination fifo b-index register 3 0x01c1 03d4 dfmpprxy3 edma3 tc0 destination fifo memory protection proxy register 3 0x01c1 03d8 - 0x01c1 03ff ? reserved transfer controller 1 registers 0x01c1 0400 pid peripheral identification register 0x01c1 0404 tccfg edma3 tc1 configuration register 0x01c1 0408 - 0x01c1 04ff ? reserved 0x01c1 0500 tcstat edma3 tc1 channel status register 0x01c1 0504 - 0x01c1 0513 ? reserved 0x01c1 0514 - 0x01c1 051f ? reserved 0x01c1 0520 errstat edma3 tc1 error status register 0x01c1 0524 erren edma3 tc1 error enable register 0x01c1 0528 errclr edma3 tc1 error clear register 0x01c1 052c errdet edma3 tc1 error details register 0x01c1 0530 errcmd edma3 tc1 error interrupt command register 0x01c1 0534 - 0x01c1 053f ? reserved 0x01c1 0540 rdrate edma3 tc1 read command rate register 0x01c1 0544 - 0x01c1 05ff ? reserved 0x01c1 0600 - 0x01c1 063f ? reserved 0x01c1 0640 saopt edma3 tc1 source active options register 0x01c1 0644 sasrc edma3 tc1 source active source address register 0x01c1 0648 sacnt edma3 tc1 source active count register 0x01c1 064c sadst edma3 tc1 source active destination address register 0x01c1 0650 sabidx edma3 tc1 source active b-index register 0x01c1 0654 sampprxy edma3 tc1 source active memory protection proxy register 0x01c1 0658 sacntrld edma3 tc1 source active count reload register 0x01c1 065c sasrcbref edma3 tc1 source active source address b-reference register 0x01c1 0660 sadstbref edma3 tc1 source active destination address b-reference register 0x01c1 0664 - 0x01c1 067f ? reserved 0x01c1 0680 dfcntrld edma3 tc1 destination fifo set count reload register 0x01c1 0684 dfsrcbref edma3 tc1 destination fifo set source address b-reference register peripheral information and electrical specifications 180 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-17. dm6467 edma registers (continued) hex address range acronym register name edma3 tc1 destination fifo set destination address b-reference 0x01c1 0688 dfdstbref register 0x01c1 068c - 0x01c1 06ff ? reserved 0x01c1 0700 dfopt0 edma3 tc1 destination fifo options register 0 0x01c1 0704 dfsrc0 edma3 tc1 destination fifo source address register 0 0x01c1 0708 dfcnt0 edma3 tc1 destination fifo count register 0 0x01c1 070c dfdst0 edma3 tc1 destination fifo destination address register 0 0x01c1 0710 dfbidx0 edma3 tc1 destination fifo b-index register 0 0x01c1 0714 dfmpprxy0 edma3 tc1 destination fifo memory protection proxy register 0 0x01c1 0718 - 0x01c1 073f ? reserved 0x01c1 0740 dfopt1 edma3 tc1 destination fifo options register 1 0x01c1 0744 dfsrc1 edma3 tc1 destination fifo source address register 1 0x01c1 0748 dfcnt1 edma3 tc1 destination fifo count register 1 0x01c1 074c dfdst1 edma3 tc1 destination fifo destination address register 1 0x01c1 0750 dfbidx1 edma3 tc1 destination fifo b-index register 1 0x01c1 0754 dfmpprxy1 edma3 tc1 destination fifo memory protection proxy register 1 0x01c1 0758 - 0x01c1 077f ? reserved 0x01c1 0780 dfopt2 edma3 tc1 destination fifo options register 2 0x01c1 0784 dfsrc2 edma3 tc1 destination fifo source address register 2 0x01c1 0788 dfcnt2 edma3 tc1 destination fifo count register 2 0x01c1 078c dfdst2 edma3 tc1 destination fifo destination address register 2 0x01c1 0790 dfbidx2 edma3 tc1 destination fifo b-index register 2 0x01c1 0794 dfmpprxy2 edma3 tc1 destination fifo memory protection proxy register 2 0x01c1 0798 - 0x01c1 07bf ? reserved 0x01c1 07c0 dfopt3 edma3 tc1 destination fifo options register 3 0x01c1 07c4 dfsrc3 edma3 tc1 destination fifo source address register 3 0x01c1 07c8 dfcnt3 edma3 tc1 destination fifo count register 3 0x01c1 07cc dfdst3 edma3 tc1 destination fifo destination address register 3 0x01c1 07d0 dfbidx3 edma3 tc1 destination fifo b-index register 3 0x01c1 07d4 dfmpprxy3 edma3 tc1 destination fifo memory protection proxy register 3 0x01c1 07d8 - 0x01c1 07ff ? reserved transfer controller 2 registers 0x01c1 0800 pid peripheral identification register 0x01c1 0804 tccfg edma3 tc2 configuration register 0x01c1 0808 - 0x01c1 08ff ? reserved 0x01c1 0900 tcstat edma3 tc2 channel status register 0x01c1 0904 - 0x01c1 0913 ? reserved 0x01c1 0914 - 0x01c1 091f ? reserved 0x01c1 0920 errstat edma3 tc2 error status register 0x01c1 0924 erren edma3 tc2 error enable register 0x01c1 0928 errclr edma3 tc2 error clear register 0x01c1 092c errdet edma3 tc2 error details register 0x01c1 0930 errcmd edma3 tc2 error interrupt command register 0x01c1 0934 - 0x01c1 093f ? reserved 0x01c1 0940 rdrate edma3 tc2 read command rate register 0x01c1 0944 - 0x01c1 09ff ? reserved 0x01c1 0a00 - 0x01c1 0a3f ? reserved submit documentation feedback peripheral information and electrical specifications 181
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-17. dm6467 edma registers (continued) hex address range acronym register name 0x01c1 0a40 saopt edma3 tc2 source active options register 0x01c1 0a44 sasrc edma3 tc2 source active source address register 0x01c1 0a48 sacnt edma3 tc2 source active count register 0x01c1 0a4c sadst edma3 tc2 source active destination address register 0x01c1 0a50 sabidx edma3 tc2 source active b-index register 0x01c1 0a54 sampprxy edma3 tc2 source active memory protection proxy register 0x01c1 0a58 sacntrld edma3 tc2 source active count reload register 0x01c1 0a5c sasrcbref edma3 tc2 source active source address b-reference register 0x01c1 0a60 sadstbref edma3 tc2 source active destination address b-reference register 0x01c1 0a64 - 0x01c1 0a7f ? reserved 0x01c1 0a80 dfcntrld edma3 tc2 destination fifo set count reload register 0x01c1 0a84 dfsrcbref edma3 tc2 destination fifo set source address b-reference register edma3 tc2 destination fifo set destination address b-reference 0x01c1 0a88 dfdstbref register 0x01c1 0a8c - 0x01c1 0aff ? reserved 0x01c1 0b00 dfopt0 edma3 tc2 destination fifo options register 0 0x01c1 0b04 dfsrc0 edma3 tc2 destination fifo source address register 0 0x01c1 0b08 dfcnt0 edma3 tc2 destination fifo count register 0 0x01c1 0b0c dfdst0 edma3 tc2 destination fifo destination address register 0 0x01c1 0b10 dfbidx0 edma3 tc2 destination fifo b-index register 0 0x01c1 0b14 dfmpprxy0 edma3 tc2 destination fifo memory protection proxy register 0 0x01c1 0b18 - 0x01c1 0b3f ? reserved 0x01c1 0b40 dfopt1 edma3 tc2 destination fifo options register 1 0x01c1 0b44 dfsrc1 edma3 tc2 destination fifo source address register 1 0x01c1 0b48 dfcnt1 edma3 tc2 destination fifo count register 1 0x01c1 0b4c dfdst1 edma3 tc2 destination fifo destination address register 1 0x01c1 0b50 dfbidx1 edma3 tc2 destination fifo b-index register 1 0x01c1 0b54 dfmpprxy1 edma3 tc2 destination fifo memory protection proxy register 1 0x01c1 0b58 - 0x01c1 0b7f ? reserved 0x01c1 0b80 dfopt2 edma3 tc2 destination fifo options register 2 0x01c1 0b84 dfsrc2 edma3 tc2 destination fifo source address register 2 0x01c1 0b88 dfcnt2 edma3 tc2 destination fifo count register 2 0x01c1 0b8c dfdst2 edma3 tc2 destination fifo destination address register 2 0x01c1 0b90 dfbidx2 edma3 tc2 destination fifo b-index register 2 0x01c1 0b94 dfmpprxy2 edma3 tc2 destination fifo memory protection proxy register 2 0x01c1 0b98 - 0x01c1 0bbf ? reserved 0x01c1 0bc0 dfopt3 edma3 tc2 destination fifo options register 3 0x01c1 0bc4 dfsrc3 edma3 tc2 destination fifo source address register 3 0x01c1 0bc8 dfcnt3 edma3 tc2 destination fifo count register 3 0x01c1 0bcc dfdst3 edma3 tc2 destination fifo destination address register 3 0x01c1 0bd0 dfbidx3 edma3 tc2 destination fifo b-index register 3 0x01c1 0bd4 dfmpprxy3 edma3 tc2 destination fifo memory protection proxy register 3 0x01c1 0bd8 - 0x01c1 0bff ? reserved transfer controller 3 registers 0x01c1 0c00 pid peripheral identification register 0x01c1 0c04 tccfg edma3 tc3 configuration register 0x01c1 0c08 - 0x01c1 0cff ? reserved peripheral information and electrical specifications 182 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-17. dm6467 edma registers (continued) hex address range acronym register name 0x01c1 0d00 tcstat edma3 tc3 channel status register 0x01c1 0d04 - 0x01c1 0d1f ? reserved 0x01c1 0d20 errstat edma3 tc3 error status register 0x01c1 0d24 erren edma3 tc3 error enable register 0x01c1 0d28 errclr edma3 tc3 error clear register 0x01c1 0d2c errdet edma3 tc3 error details register 0x01c1 0d30 errcmd edma3 tc3 error interrupt command register 0x01c1 0d34 - 0x01c1 0d3f ? reserved 0x01c1 0d40 rdrate edma3 tc3 read command rate register 0x01c1 0d44 - 0x01c1 0e3f ? reserved 0x01c1 0e40 saopt edma3 tc3 source active options register 0x01c1 0e44 sasrc edma3 tc3 source active source address register 0x01c1 0e48 sacnt edma3 tc3 source active count register 0x01c1 0e4c sadst edma3 tc3 source active destination address register 0x01c1 0e50 sabidx edma3 tc3 source active b-index register 0x01c1 0e54 sampprxy edma3 tc3 source active memory protection proxy register 0x01c1 0e58 sacntrld edma3 tc3 source active count reload register 0x01c1 0e5c sasrcbref edma3 tc3 source active source address b-reference register 0x01c1 0e60 sadstbref edma3 tc3 source active destination address b-reference register 0x01c1 0e64 - 0x01c1 0e7f ? reserved 0x01c1 0e80 dfcntrld edma3 tc3 destination fifo set count reload register 0x01c1 0e84 dfsrcbref edma3 tc3 destination fifo set source address b-reference register edma3 tc3 destination fifo set destination address b-reference 0x01c1 0e88 dfdstbref register 0x01c1 0e8c - 0x01c1 0eff ? reserved 0x01c1 0f00 dfopt0 edma3 tc3 destination fifo options register 0 0x01c1 0f04 dfsrc0 edma3 tc3 destination fifo source address register 0 0x01c1 0f08 dfcnt0 edma3 tc3 destination fifo count register 0 0x01c1 0f0c dfdst0 edma3 tc3 destination fifo destination address register 0 0x01c1 0f10 dfbidx0 edma3 tc3 destination fifo b-index register 0 0x01c1 0f14 dfmpprxy0 edma3 tc3 destination fifo memory protection proxy register 0 0x01c1 0f18 - 0x01c1 0f3f ? reserved 0x01c1 0f40 dfopt1 edma3 tc3 destination fifo options register 1 0x01c1 0f44 dfsrc1 edma3 tc3 destination fifo source address register 1 0x01c1 0f48 dfcnt1 edma3 tc3 destination fifo count register 1 0x01c1 0f4c dfdst1 edma3 tc3 destination fifo destination address register 1 0x01c1 0f50 dfbidx1 edma3 tc3 destination fifo b-index register 1 0x01c1 0f54 dfmpprxy1 edma3 tc3 destination fifo memory protection proxy register 1 0x01c1 0f58 - 0x01c1 0f7f ? reserved 0x01c1 0f80 dfopt2 edma3 tc3 destination fifo options register 2 0x01c1 0f84 dfsrc2 edma3 tc3 destination fifo source address register 2 0x01c1 0f88 dfcnt2 edma3 tc3 destination fifo count register 2 0x01c1 0f8c dfdst2 edma3 tc3 destination fifo destination address register 2 0x01c1 0f90 dfbidx2 edma3 tc3 destination fifo b-index register 2 0x01c1 0f94 dfmpprxy2 edma3 tc3 destination fifo memory protection proxy register 2 0x01c1 0f98 - 0x01c1 0fbf ? reserved 0x01c1 0fc0 dfopt3 edma3 tc3 destination fifo options register 3 submit documentation feedback peripheral information and electrical specifications 183
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-17. dm6467 edma registers (continued) hex address range acronym register name 0x01c1 0fc4 dfsrc3 edma3 tc3 destination fifo source address register 3 0x01c1 0fc8 dfcnt3 edma3 tc3 destination fifo count register 3 0x01c1 0fcc dfdst3 edma3 tc3 destination fifo destination address register 3 0x01c1 0fd0 dfbidx3 edma3 tc3 destination fifo b-index register 3 0x01c1 0fd4 dfmpprxy3 edma3 tc3 destination fifo memory protection proxy register 3 0x01c1 0fd8 - 0x01c1 0fff ? reserved table 7-18 shows an abbreviation of the set of registers which make up the parameter set for each of 512 edma events. each of the parameter register sets consist of 8 32-bit word entries. table 7-19 shows the parameter set entry registers with relative memory address locations within each of the parameter sets. peripheral information and electrical specifications 184 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-18. edma parameter set ram hex address range description 0x01c0 4000 - 0x01c0 401f parameters set 0 (8 32-bit words) 0x01c0 4020 - 0x01c0 403f parameters set 1 (8 32-bit words) 0x01c0 4040 - 0x01c0 405f parameters set 2 (8 32-bit words) 0x01c0 4060 - 0x01c0 407f parameters set 3 (8 32-bit words) 0x01c0 4080 - 0x01c0 409f parameters set 4 (8 32-bit words) 0x01c0 40a0 - 0x01c0 40bf parameters set 5 (8 32-bit words) ... ... 0x01c0 7fc0 - 0x01c0 7fdf parameters set 510 (8 32-bit words) 0x01c0 7fe0 - 0x01c0 7fff parameters set 511 (8 32-bit words) table 7-19. parameter set entries hex offset address acronym parameter entry within the parameter set 0x0000 opt option 0x0004 src source address 0x0008 a_b_cnt a count, b count 0x000c dst destination address 0x0010 src_dst_bidx source b index, destination b index 0x0014 link_bcntrld link address, b count reload 0x0018 src_dst_cidx source c index, destination c index 0x001c ccnt c count submit documentation feedback peripheral information and electrical specifications 185
7.7 reset 7.7.1 power-on reset ( por pin) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the reset controller detects the different type of resets supported on the dm6467 device and manages the distribution of those resets throughout the device. the dm6467 device has several types of device-level global resets?power-on reset, warm reset, max reset, and system reset. table 7-20 explains further the types of reset, the reset initiator, and the effects of each reset on the chip. see section 7.7.9 , reset electrical data/timing, for more information on the effects of each reset on the pll controllers and their clocks. table 7-20. device-level global reset types type initiator effect(s) por pin global chip reset (cold reset). activates the por signal on chip, which resets the entire chip including the emulation logic. power-on reset the power-on reset ( por) pin must be driven low during power (por) ramp of the device. device boot and configuration pins are latched. resets everything except for the emulation logic. emulator stays warm reset reset pin alive during warm reset. device boot and configuration pins are latched. same as a warm reset, except the dm6467 device boot and max reset emulator, wd timer (timer 2) configuration pins are not re-latched. a system reset maintains memory contents and does not reset the system reset emulator test and emulation circuitry. the device boot and configuration pins are also not re-latched. mmr controls the c64x+ reset input. this is used for control of c64x+ local reset software (register bit) c64x+ reset by the arm. the c64x+ slave dma port is still alive (dsp reset) when in local reset. in addition to device-level global resets, the psc provides the capability to cause local resets to peripherals and/or the c64x+ dsp. power-on reset (por) is initiated by the por pin and is used to reset the entire chip, including the test and emulation logic. power-on reset is also referred to as a cold reset since the device usually goes through a power-up cycle. during power-up, the por pin must be asserted (driven low) until the power supplies have reached their normal operating conditions. if an external 27-mhz oscillator is used on the dev_mxi/dev_clkin pin, the source clock should also be running at the correct frequency prior to de-asserting the por pin. note: a device power-up cycle is not required to initiate a power-on reset. the following sequence must be followed during a power-on reset. 1. wait for the power supplies to reach normal operating conditions while keeping the por pin asserted (driven low). 2. wait for the input clock source to be stable while keeping the por pin asserted (low). 3. once the power supplies and the input clock source are stable, the por pin must remain asserted (low) for a minimum of 12 dev_mxi cycles. within the low period of the por pin, the following happens: ? the reset signals flow to the entire chip (including the test and emulation logic), resetting the modules on chip. ? the pll controller clocks start at the frequency of the dev_mxi clock. the clocks are propagated throughout the chip to reset the chip synchronously. by default, both pll1 and pll2 are in reset and unlocked. the pll controllers default to pll bypass mode. 4. the por pin may now be deasserted (driven high). peripheral information and electrical specifications 186 submit documentation feedback
7.7.1.1 usage of por versus reset pins 7.7.1.2 latching boot and configuration pins 7.7.2 warm reset ( reset pin) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 when the por pin is deasserted (high), the configuration pin values are latched and the pll controllers changed their system clocks to their default divide-down values. both pll controllers are still in pll bypass mode. other device initialization also begins. 5. after device initialization is complete, the pll controllers pause the system clocks for 10 cycles. at this point: ? the i/o pins are controlled by the default peripherals (default peripherals are determined by pinmux0 and pinmux1 registers). ? the clock and reset of each peripheral is determined by the default settings of the power and sleep controller (psc). ? the pll controllers are operating in pll bypass mode. ? the arm926 begins executing from the default address (either arm boot rom or emifa). after the reset sequence, the boot sequence begins. for more details on the boot sequence, see the using the tms320dm646x bootloader application report (literature number spraas0 ). por and reset are independent resets. if the device needs to go through a power-up cycle, por ( not reset) must be used to fully reset the device. in functional end-system, emulation/debugger logic is typically not needed; therefore, the recommendation for functional end-system is to use the por pin for full device reset. if reset pin is not needed, it can be pulled inactive (high) via an external pullup resistor. in a debug system, it is typically desirable to allow the reset of the device without crashing an emulation session. in this case, the user can use the por pin to achieve full device reset and use the reset pin to achieve a debug reset?which resets the entire device except test and emulation logic. internal to the chip, the two device reset pins reset and por are logically and?ed together only for the purpose of latching device boot and configuration pins. the values on all device and boot configuration pins are latched into the bootcfg register when the logical and of reset and por transitions from low to high. a warm reset is activated by driving the reset pin active-low. this resets everything in the device except the test or emulation logic. an emulator session will stay alive during warm reset. for more information on por vs. reset usage, see section 7.7.1.1 , usage of por versus reset pins and section 7.7.1.2 , latching boot and configuration pins. the following sequence must be followed during a warm reset: 1. power supplies and input clock source should already be stable. 2. the reset pin must be asserted (low) for a minimum of 12 dev_mxi cycles. within the low period of the reset pin, the following happens: ? the reset signals flow to the entire chip resetting all the modules on chip, except the test and emulation logic. ? the pll controllers are reset thereby, switching back to pll bypass mode and resetting all their registers to default values. both pll1 and pll2 are placed in reset and lose lock. 3. the reset pin may now be deasserted (driven high). when the reset pin is deasserted (high), the configuration pin values are latched and the pll controllers changed their system clocks to their default divide-down values. both pll controllers are still in pll bypass mode. other device initialization also begins. 4. after device initialization is complete, the pll controllers pause the system clocks for 10 cycles. submit documentation feedback peripheral information and electrical specifications 187
7.7.3 maximum reset 7.7.4 system reset tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com at this point: ? the i/o pins are controlled by the default peripherals (default peripherals are determined by pinmux0 and pinmux1 registers). ? the clock and reset of each peripheral is determined by the default settings of the power and sleep controller (psc). ? the pll controllers are operating in pll bypass mode. ? the arm926 begins executing from the default address (either arm boot rom, tcm ram, or emifa). after the reset sequence, the boot sequence begins. for more details on the boot sequence, see the using the tms320dm646x bootloader application report (literature number spraas0 ). a maximum (max) reset is initiated by the emulator or the watchdog timer (timer 2). the effects are the same as a warm reset, except the device boot and configuration pins are not re-latched. the emulator initiates a maximum reset via the icepick module. this icepick-initiated reset is non-maskable. when the watchdog timer counter reaches zero, this will also initiate a maximum reset to recover from a runaway condition. to invoke the maximum reset via the icepick module, the user can perform the following from the code composer studio? ide menu: debug ? advanced resets ? system reset this is the max reset sequence: 1. max reset is initiated by the emulator or the watchdog timer. during this time, the following happens: ? the reset signals flow to the entire chip, resetting all the modules on chip except the test and emulation logic. ? the pll controllers are reset ?thereby, switching back to pll bypass mode and resetting all their registers to default values. both pll1 and pll2 are placed in reset and lose lock. 2. after device initialization is complete, the pll controllers pause the system clocks for 10 cycles. at this point: ? the i/o pins are controlled by the default peripherals (default peripherals are determined by pinmux0 and pinmux1 registers). ? the clock and reset of each peripheral is determined by the default settings of the power and sleep controller (psc). ? the pll controllers are operating in pll bypass mode. ? the arm926 begins executing from the default address (either arm boot rom, tcm ram, or emifa). after the reset sequence, the boot sequence begins. since the boot and configuration pins are not latched with a max reset, the previous values (as shown in the bootcfg register) are used to select the boot mode. for more details on the boot sequence, see the using the tms320dm646x bootloader application report (literature number spraas0 ). a system reset is initiated by the emulator. the following memory contents are maintained: l1/l2 ram: the c64x+ l1/l2 ram content is retained. the l1/l2 cache content is not retained because tag information is reset. ddr2 memory controller: the ddr2 memory controller registers are not reset. in addition, the ddr2 sdram memory content is retained if the user places the ddr2 sdram in self-refresh mode before invoking the system reset. test, emulation, clock, and power control logic are unaffected. the emulator initiates a system reset via the c64x+ emulation logic. this reset can be masked by the emulator. peripheral information and electrical specifications 188 submit documentation feedback
7.7.5 c64x+ local reset (dsp local reset) 7.7.6 peripheral local reset 7.7.7 reset priority tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 this is the system reset sequence: 1. the system reset is initiated by the emulator. during this time, the following happens: ? the reset signals flow to the entire chip resetting all the modules on chip, except the test and emulation logic. ? the pll controllers are not reset. internal system clocks are unaffected. if pll1/pll2 were locked before the system reset, they remain locked. 2. after device initialization is complete, the pll controllers pause the system clocks for 10 cycles. at this point: ? the i/o pins are controlled by the default peripherals (default peripherals are determined by pinmux0 and pinmux1 registers). ? the clock and reset of each peripheral (except the ddr2 memory controller) is determined by the default settings of the power and sleep controller (psc). ? the ddr2 memory controller registers retain their previous values. only the ddr2 memory controller state machines are reset by the system reset. ? the pll controllers are operating in the mode prior to system reset. the system clocks are unaffected. ? the arm926 begins executing from the default address (either arm boot rom, tcm ram, or emifa). after the reset sequence, the boot sequence begins. since the boot and configuration pins are not latched with a system reset, the previous values (as shown in the bootcfg register) are used to select the boot mode. for more details on the boot sequence, see the using the tms320dm646x bootloader application report (literature number spraas0 ). with access to the psc registers, the arm can perform two types of dsp reset: dsp local reset and dsp module reset. when dsp local reset is asserted, the dsp?s internal memories (l1p, l1d, and l2) are still accessible. the local reset only resets the dsp cpu core, not the rest of the dsp subsystem, as the dsp module reset would. local reset is useful when the dsp module is in the enable state or in the disable state. the dsp module reset takes precedence over local reset. the arm uses local reset to reset the dsp to initiate the dsp boot process. the intent of module reset is to completely reset the dsp (like hard reset). for more detailed information on dsp local reset and dsp module reset, see the arm-dsp integration chapter in the tms320dm646x dmsoc arm subsystem reference guide (literature number spruep9 ). for information on peripheral selection at the rising edge of por or reset, see section 4 , device configurations of this data manual. the user can configure the local reset and clock state of a peripheral through programming the psc. table 7-3 , dm6467 lpsc assignments, identifies the lpsc numbers and the peripherals capable of being locally reset by the psc. for more detailed information on the programming of these peripherals by the psc, see the tms320dm646x dmsoc arm subsystem reference guide (literature number spruep9 ). if any of the above reset sources occur simultaneously, the pllc only processes the highest-priority reset request. the reset request priorities, from high to low, are as follows: power-on reset maximum reset warm reset submit documentation feedback peripheral information and electrical specifications 189
7.7.7.1 reset type status (rstype) register 7.7.8 pin behaviors at reset tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com system reset the reset type status (rstype) register (0x01c4 08e4) is the only register for the reset controller. this register falls in the same memory range as the pll1 controller registers (see table 7-12 for the pll1 controller registers (including reset controller)). for more details on the rstype register and its bit descriptions, see figure 7-19 and table 7-21 . 31 16 reserved r-0000 0000 0000 0000 15 4 3 2 1 0 reserved srst mrst wrst por r-0000 0000 0000 r-0/1 r-0/1 r-0/1 r-0/1 legend: r = read only; - n = value after reset figure 7-19. reset type status (rstype) register [0x01c4 08e4] table 7-21. rstype register bit descriptions bit name description 30:4 reserved reserved. read returns "0". writes have no effect. system reset. 3 srst 0 = system reset was not the last reset to occur. 1 = system reset was the last reset to occur. max reset. 2 mrst 0 = max reset was not the last reset to occur. 1 = max reset was the last reset to occur. warm reset. 1 wrst 0 = warm reset was not the last reset to occur. 1 = warm reset was the last reset to occur. power-on reset. 0 por 0 = power-on reset was not the last reset to occur. 1 = power-on reset was the last reset to occur. during normal operations, pins are controlled by the respective peripheral selected in the pinmux0 or pinmux1 register. during device level global reset, the pin behaves as follows: multiplexed boot and configuration pins these pins are forced 3-stated when the device is in reset. this is to ensure the proper boot and configuration values can be latched on these multiplexed pins. this is particularly useful in the case where the boot and configuration values are driven by an external control device. once the device is out of reset, these pins are controlled by their respective default peripheral. boot and configuration pins group: vp_dout6/dspboot, vp_dout5/pcien, vp_dout4/cs2bw, vp_dout3/btmode3, vp_dout2/btmode2, vp_dout1/btmode1, and vp_dout0/btmode0. for information on whether external pullup/pulldown resistors should be used on the boot and configuration pins, see section 4.8.1 , pullup/pulldown resistors. peripheral information and electrical specifications 190 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 default power down pins as discussed in section 4.2 , power considerations, the vdd3p3v_pwdn register controls power to the 3.3-v pins. the vdd3p3v_pwdn register defaults to powering down some 3.3-v pins to save power. for more details on the vdd3p3v_pwdn register and which 3.3-v pins default to power up or power down, see section 4.2 , power considerations. the pins that default to power down, are both reset to power down and high-impedance. they remain in that state until configured otherwise by vdd3p3_pwdn and pinmux0/pinmux1 programming. default power down pin group: usb_drvvbus/gp[22], clkout0, spi_clk, spi_en, spi_cs0, spi_cs1, spi_miso, spi_mosi, vlynq_clock, vlynq_scrun, vlynq_txd[3:0], vlynq_rxd[3:0], rftclk, gmtclk, mtxd[7:4], mrxd[7:4], mtclk, mtxd[3:0], mtxen, mcol, mcrs, mrclk, mrxd[3:0], mrxdv, mrxer, mdclk, mdio, aclkx1, ahclkx1, axr1[0], aclkr0, ahclkr0, afsr0, aclkx0, ahclkx0, afsx0, axr0[3:0], amute0, amutein0, pci_clk/gp[10], pci_devsel/hcntl1/em_ba[1], pci_frame/ hint/em_ba[0], pci_irdy/ hrdy/em_a[17], pci_trdy/hhwil/em_a[16], pci_stop/hcntl0/ em_we, pci_serr/ hds1/ em_oe, pci_perr/ hcs/ em_dqm1, pci_par/ has/ em_dqm0, pci_inta/em_wait2, pci_cbe3/hr/ w/ em_cs3, pci_cbe2/ hds2/ em_cs2, pci_ad[15:0]/hd[15:0]/em_d[15:0], pci_rst/da2/gp[13]/em_a[22], pci_idsel/hddir/em_r/ w, pci_req/dmarq/gp[11]/ em_cs5, pci_gnt/ dmack/gp[12]/ em_cs4, pci_cbe1/ ata_cs1/gp[32]/em_a[19], pci_cbe0/ ata_cs0/gp[33]/em_a[18], diow/gp[20]/em_wait4, iordy/gp[21]/em_wait3, dior/gp[19]/em_wait5, da1/gp[16]/em_a[21], da0/gp[17]/em_a[20], intrq/gp[18]/rsv, pci_ad[31:16]/dd[15:0]/hd[31:16]/em_a[15:0], gp[7]/cvddadj1, gp[6]/cvddadj0, gp[5], gp[4]/stc_clkin, gp[3]/audio_clk0, gp[2]/audio_clk1, gp[1], gp[0], tout2, tinp1l, tout1l, tout1u, tinp0l, tinp0u, tout0l, tout0u, pwm1/ts1_dout, pwm0/crg0_po/ts1_enao, urts2/uirtx2/ts0_pstin/gp[41], ucts2/usd2/crg0_vcxi/gp[42]/ts1_psto, urxd2/crg1_vcxi/gp[39]/crg0_vcxi, utxd2/urctx2/crg1_po/gp[40]/crg0_po, urts1/uirtx1/ts0_waito/gp[25], ucts1/usd1/ts0_en_waito/gp[26], urxd1/ts0_din7/gp[23], utxd1/urctx1/ts0_dout7/gp[24], udtr0/ts0_enao/gp[36], udsr0/ts0_psto/gp[37], udcd0/ts0_waitin/gp[38], urin0/gp[8]/ts1_waitin, urxd0/ts1_din, utxd0/urctx0/ts1_pstin, urts0/uirtx0/ts1_en_waito, ucts0/usd0, vp_dout15/ts1_din, vp_dout14/ts1_pstin, vp_dout13/ts1_en_waito, vp_dout12/ts1_waito, vp_dout11/ts1_dout, vp_dout10/ts1_psto, vp_dout9/ts1_enao, vp_dout8/ts1_waitin, vp_clkin3/ts1_clko, vp_clko3/ts0_clko, vp_dout7/vadjen, vp_dout6/dspboot, vp_dout5/pcien, vp_dout4/cs2bw, vp_dout3/btmode3, vp_dout2/btmode2, vp_dout1/btmode1, vp_dout0/btmode0, vp_clkin2, vp_clko2, vp_din15_vsync/ts0_din7, vp_din14_hsync/ts0_din6, vp_din13_field/ts0_din5, vp_din12/ts0_din4, vp_din11/ts0_din3, vp_din10/ts0_din2, vp_din9/ts0_din1, vp_din8/ts0_din0, vp_clkin1, vp_din7/ts0_dout7/ts1_din, vp_din6/ts0_dout6/ts1_pstin, vp_din5/ts0_dout5/ts1_en_waito, vp_din4/ts0_dout4/ts1_waito, vp_din3/ts0_dout3, vp_din2/ts0_dout2, vp_din1/ts0_dout1, vp_din0/ts0_dout0, vp_clkin0. submit documentation feedback peripheral information and electrical specifications 191
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com all other pins during device reset, all other pins are controlled by the default peripheral. the default peripheral is determined by the default settings of the pinmux0 or pinmux1 registers. some of the pinmux0/pinmux1 settings are determined by configuration pins latched at reset. to determine the reset behavior of these pins, see section 4.7 , multiplexed pin configurations and read the rest of the this subsection to understand how that default peripheral controls the pin. the reset behaviors for all these other pins during all boot modes, except pci boot, are categorized as follows (also see figure 7-20 and figure 7-21 in section 7.7.9 , reset electrical data/timing): ddr2 z group: ddr_dqs[3:0], ddr_dqs[3:0], ddr_d[31:0], ddr_dqgate1, ddr_dqgate3 ddr2 low group: ddr_clk, ddr_cke, ddr_odt0, ddr_a[14:0], ddr_dqgate0, ddr_dqgate2 ddr2 high group: ddr_clk, ddr_cs, ddr_we, ddr_ras, ddr_cas ddr2 z/high group: ddr_dqm[3:0] ddr2 low/high group: ddr_ba[2:0] z group: these pin are 3-stated by default, and these pins remain 3-stated throughout por or reset assertion. when por or reset is deasserted, these pins remain 3-stated until configured otherwise by their respective peripheral (after the peripheral is enabled by the psc). pci_clk/gp[10], pci_inta/em_wait2, diow/gp[20]/em_wait4, iordy/gp[21]/em_wait3, pci_ad[15:0]/hd[15:0]/em_d[15:0], rftclk, gmtclk, mtclk, mtxd[7:0], mtxen, mcol, mcrs, mrclk, mrxd[7:0], mrxdv, mrxer, mdclk, mdio, urxd0/ts1_din, utxd0/urctx0/ts1_pstin, urts0/uirtx0/ts1_en_waito, ucts0/usd0, udtr0/ts0_enao/gp[36], udsr0/ts0_psto/gp[37], udcd0/ts0_waitin/gp[38], urin0/gp[8]/ts1_waitin, urxd1/ts0_din7/gp[23], utxd1/urctx1/ts0_dout7/gp[24], urts1/uirtx1/ts0_waito/gp[25], ucts1/usd1/ts0_en_waito/gp[26], urxd2/crg1_vcxi/gp[39]/crg0_vcxi, utxd2/urctx2/crg1_po/gp[40]/crg0_po, urts2/uirtx2/ts0_pstin/gp[41], ucts2/usd2/crg0_vcxi/gp[42]/ts1_psto, aclkr0, ahclkr0, afsr0, aclkx0, ahclkx0, afsx0, axr0[3:0], amute0, amutein0, aclkx1, ahclkx1, axr1[0], scl, sda, spi_clk, spi_en, spi_cs0, spi_cs1, spi_miso, spi_mosi, pwm0/crg0_po/ts1_enao, pwm1/ts1_dout, vlynq_clock, vlynq_scrun, vlynq_txd[3:0], vlynq_rxd[3:0], usb_drvvbus/gp[22], tinp0l, tinp0u, tout0l, tout0u, tinp1l, tout1l, tout1u, tout2, ts0_clkin, ts1_clkin, vp_clkin0, vp_clkin1, vp_din15_vsync/ts0_din7, vp_din14_hsync/ts0_din6, vp_din13_field/ts0_din5, vp_din12/ts0_din4, vp_din11/ts0_din3, vp_din10/ts0_din2, vp_din9/ts0_din1, vp_din8/ts0_din0, vp_din7/ts0_dout7/ts1_din, vp_din6/ts0_dout6/ts1_pstin, vp_din5/ts0_dout5/ts1_en_waito, vp_din4/ts0_dout4/ts1_waito, vp_din3/ts0_dout3, vp_din2/ts0_dout2, vp_din1/ts0_dout1, vp_din0/ts0_dout0, vp_clkin2, vp_clkin3/ts1_clko, vp_clko2, vp_clko3/ts0_clko, vp_dout15/ts1_din, vp_dout14/ts1_pstin, vp_dout13/ts1_en_waito, vp_dout12/ts1_waito, vp_dout11/ts1_dout, vp_dout10/ts1_psto, vp_dout9/ts1_enao, vp_dout8/ts1_waitin, vp_dout7/vadjen, gp[0], gp[1], gp[2]/audio_clk1, gp[3]/audio_clk0, gp[4]/stc_clkin, gp[5], gp[6]/cvddadj0, gp[7]/cvddadj1, tims, tdo, tdi, tck, trst, emu1, emu0, dev_mxi/dev_clkin, aux_mxi/aux_clkin low group: these pins are low by default, and remain low until configured otherwise by their respective peripheral (after the peripheral is enabled by the psc). pci_rst/da2/gp[13]/em_a[22], pci_idsel/hddir/em_r/ w, pci_irdy/ hrdy/em_a[17], pci_trdy/hhwil/em_a[16], pci_cbe1/ ata_cs1/gp[32]/em_a[19], pci_cbe0/ ata_cs0/gp[33]/em_a[18], pci_ad[31:16]/dd[15:0]/hd[31:16]/em_a[15:0], clkout0, rtclk, high group: these pins are high by default, and remain high until configured otherwise by their respective peripheral (after the peripheral is enabled by the psc). pci_devsel/hcntl1/em_ba[1], pci_frame/ hint/em_ba[0], pci_stop/hcntl0/ em_we, peripheral information and electrical specifications 192 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 pci_serr/ hds1/ em_oe, pci_perr/ hcs/ em_dqm1, pci_par/ has/ em_dqm0, pci_req/dmarq/gp[11]/ em_cs5, pci_gnt/ dmack/gp[12]/ em_cs4, pci_cbe3/hr/ w/ em_cs3, pci_cbe2/ hds2/ em_cs2, note: for pci boot mode, all pci pins now behave according to z group. for more information on the pin behaviors during device-level global reset, see figure 7-20 and figure 7-21 in section 7.7.9 , reset electrical data/timing. submit documentation feedback peripheral information and electrical specifications 193
7.7.9 reset electrical data/timing tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com note: if a configuration pin must be routed out from the device, the internal pullup/pulldown (ipu/ipd) resistor should not be relied upon; ti recommends the use of an external pullup/pulldown resistor. table 7-22. timing requirements for reset (see figure 7-20 and figure 7-21 ) -594, -729 no. unit min max 1 t w(reset) pulse duration, por low or reset low 12c (1) ns setup time, boot and configuration pins valid before por high or reset 2 t su(config) 12c (1) ns high (2) hold time, boot and configuration pins valid after por high or reset 3 t h(config) 0 ns high (2) (1) c = 1/dev_mxi clock frequency in ns. the device clock source must be stable and at a valid frequency prior to meeting the t w(reset) requirement. (2) for the list of boot and configuration pins, see table 3-5 , boot terminal functions. table 7-23. switching characteristics over recommended operating conditions during reset (1) (see figure 7-21 ) -594, -729 no. parameter unit min max 4 t w(pause) pulse duration, sysclks paused (low) 10c 10c ns 23 t d(rsth-pause) delay time, reset high or por high to sysclks paused (low) 1990c ns 5 t d(rstl-bootz) delay time, reset low to boot configuration group high impedance 0 20 ns 6 t d(rstl-ddrzz) delay time, reset low to ddr2 z group high impedance 0 7p + 20 ns 7 t d(rstl-ddrll) delay time, reset low to ddr2 low group low 0 3p + 20 ns 8 t d(rstl-ddrhh) delay time, reset low to ddr2 high group high 0 20 ns 13 t d(rstl-ddrzhz) delay time, reset low to ddr2 z/high group high impedance 0 7p + 20 ns 14 t d(rstl-ddrlhl) delay time, reset low to ddr2 low/high group low 0 20 ns 17 t d(rstl-zz) delay time, reset low to z group high impedance 0 20 ns 18 t d(rstl-lowl) delay time, reset low to low group low 0 20 ns 19 t d(rstl-highh) delay time, reset low to high group high 0 20 ns 9 t d(rstl-bootv) delay time, reset high to boot configuration group valid (2) ns 10 t d(rsth-ddrzv) delay time, reset high to ddr2 z group valid (2) ns 11 t d(rsth-ddrlv) delay time, reset high to ddr2 low group valid (2) ns 12 t d(rsth-ddrhv) delay time, reset high to ddr2 high group valid (2) ns 15 t d(rsth-ddrzhv) delay time, reset high to ddr2 z/high group valid high (2) ns 16 t d(rsth-ddrlhv) delay time, reset high to ddr2 low/high group valid high (2) ns 20 t d(rsth-zv) delay time, reset high to z group valid (2) ns 21 t d(rsth-lowv) delay time, reset high to low group valid (2) ns 22 t d(rsth-highv) delay time, reset high to high group valid (2) ns (1) c = 1/dev_clkin clock frequency in ns. (2) following reset high or por high, this signal group maintains the state the pins(s) achieved while reset or por was driven low until the peripheral is enabled via the psc. for example, the ddr2 z group goes high impedance following reset low or por low and remains in the high-impedance state following reset high or por high until the ddr2 controller is enabled via the psc. figure 7-20 shows the power-up timing. figure 7-21 shows the warm reset ( reset) timing. max reset timing is identical to warm reset timing, except the boot and configuration pins are not relatched and the bootcfg register retains its previous value latched before the max reset was initiated. peripheral information and electrical specifications 194 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 a. power supplies and dev_mxi must be stable before the start of t w(reset). . b. pin reset behavior depends on which peripheral defaults to controlling the multiplexed pin. for more details on what pin group (e.g., z group, z/low group, z/high group, etc.) each pin belongs to, see section 7.7.8 , pin behaviors at reset. figure 7-20. power-up timing (b) submit documentation feedback peripheral information and electrical specifications 195 dev_mxi (a) por reset sysclkrefclk (pllc1) sysclkx clkout0 boot and configuration pins ddr2 z group ddr2 low group ddr2 z/high group power supplies ramping power supplies stable hi-zhi-z clock source stable 1 2 3 ddr2 high group ddr2 low/high group z group hi-z low group high group 22 10 11 12 15 16 20 21 config 9 hi-z 23 4
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com a. pin reset behavior depends on which peripheral defaults to controlling the multiplexed pin. for more details on what pin group (e.g., z group, z/low group, z/high group, etc.) each pin belongs to, see section 7.7.8 , pin behaviors at reset. figure 7-21. warm reset ( reset) timing (a) 196 peripheral information and electrical specifications submit documentation feedback dev_mxi por reset sysclkrefclk (pllc1) sysclkx clkout0 boot and configuration pins ddr2 z group ddr2 low group ddr2 z/high group power supplies stable hi-zhi-z 1 2 3 ddr2 high group ddr2 low/high group z group hi-z low group high group 22 10 11 12 15 16 20 21 config 9 hi-z pll1 clock divx clock 5 6 19 7 8 14 17 18 13 23 4
7.8 interrupts 7.8.1 arm cpu interrupts tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the dm6467 device has a large number of interrupts to service the needs of its many peripherals and subsystems. both the arm and c64x+ are capable of servicing these interrupts. all of the device interrupts are routed to the arm interrupt controller with only a limited set routed to the c64x+ interrupt controller. the interrupts can be selectively enabled or disabled in either of the controllers. in typical applications, the arm handles most of the peripheral interrupts and grants control to the c64x+ for interrupts that are relevant to dsp algorithms. also, the arm and dsp can communicate with each other through interrupts. the arm926 cpu core supports 2 direct interrupts: fiq and irq. the dm6467 arm interrupt controller prioritizes up to 64 interrupt requests from various peripherals and subsystems, which are listed in table 7-24 , and interrupts the arm cpu. each interrupt is programmable for up to 8 levels of priority. there are 6 levels for irq and 2 levels for fiq. interrupts at the same priority level are serviced in order by the arm interrupt number, with the lowest number having the highest priority. table 7-25 shows the arm interrupt controller registers and memory locations. for more details on arm interrupt control, see the tms320dm646x dmsoc arm subsystem reference guide (literature number spruep9 ). submit documentation feedback peripheral information and electrical specifications 197
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-24. dm6467 arm interrupts arm arm interrupt acronym source interrupt acronym source number number 0 vp_vertint0 vpif 32 tintl0 timer 0 lower ? tint12 1 vp_vertint1 vpif 33 tinth0 timer 0 upper ? tint34 2 vp_vertint2 vpif 34 tintl1 timer 1 lower ? tint12 3 vp_vertint3 vpif 35 tinth1 timer 1 upper ? tint34 4 vp_errint vpif 36 pwmint0 pwm 0 5 - reserved 37 pwmint1 pwm 1 6 - reserved 38 vlqint vlynq wdint wd timer (timer 2) ? i2cint i2c 7 39 tint12 8 crgenint0 crgen 0 40 uartint0 uart 0 9 crgenint1 crgen 1 41 uartint1 uart 1 10 tsint0 tsif 0 42 uartint2 uart 2 11 tsint1 tsif 1 43 spint0 spi 12 vdceint vdce 44 spint1 spi 13 usbint usb 45 dsp2arm0 dsp controller to arm 14 usbdmaint usb dma 46 - reserved 15 pciint pci 47 pscint power and sleep controller 16 ccint0 edma cc region 0 48 gpio0 gpio 17 ccerrint edma cc error 49 gpio1 gpio 18 tcerrint0 edma tc 0 error 50 gpio2 gpio 19 tcerrint1 edma tc 1 error 51 gpio3 gpio 20 tcerrint2 edma tc 2 error 52 gpio4 gpio 21 tcerrint3 edma tc 3 error 53 gpio5 gpio 22 ideint ata 54 gpio6 gpio 23 hpiint hpi 55 gpio7 gpio 24 mac_rxth emac rx threshold 56 gpiobnk0 gpio bank 0 25 mac_rx emac receive 57 gpiobnk1 gpio bank 1 26 mac_tx emac transmit 58 gpiobnk2 gpio bank 2 27 mac_misc emac miscellaneous 59 ddrint ddr2 memory controller 28 axint0 mcasp0 transmit 60 emifaint emifa 29 arint0 mcasp0 receive 61 commtx armss 30 axint1 mcasp1 transmit 62 commrx armss 31 - reserved 63 emuint e2ice peripheral information and electrical specifications 198 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-25. arm interrupt controller registers hex address range acronym register name 0x01c4 8000 fiq0 fiq interrupt status 0 [interrupt status of int[31:0] (if mapped to fiq)] 0x01c4 8004 fiq1 fiq interrupt status 1 [interrupt status of int[63:32] (if mapped to fiq)] 0x01c4 8008 irq0 irq interrupt status 0 [interrupt status of int[31:0] (if mapped to irq)] 0x01c4 800c irq1 irq interrupt status 1 [interrupt status of int[63:32] (if mapped to irq)] 0x01c4 8010 fiqentry entry address [28:0] for valid fiq interrupt 0x01c4 8014 irqentry entry address [28:0] for valid irq interrupt 0x01c4 8018 eint0 interrupt enable register 0 0x01c4 801c eint1 interrupt enable register 1 0x01c4 8020 inctl interrupt operation control register 0x01c4 8024 eabase interrupt entry table base address register 0x01c4 8028 - 0x01c4 802f - reserved 0x01c4 8030 intpri0 interrupt 0-7 priority select 0x01c4 8034 intpri1 interrupt 8-15 priority select 0x01c4 8038 intpri2 interrupt 16-23 priority select 0x01c4 803c intpri3 interrupt 24-31 priority select 0x01c4 8040 intpri4 interrupt 32-39 priority select 0x01c4 8044 intpri5 interrupt 40-47 priority select 0x01c4 8048 intpri6 interrupt 48-55 priority select 0x01c4 804c intpri7 interrupt 56-63 priority select 0x01c4 8050 - 0x01c4 83ff - reserved submit documentation feedback peripheral information and electrical specifications 199
7.8.2 dsp interrupts tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the c64x+ dsp interrupt controller combines device events into 12 prioritized interrupts. the source for each of the 12 cpu interrupts is user-programmable and is listed in table 7-26 . also, the interrupt controller controls the generation of the cpu exception, nmi, and emulation interrupts. table 7-27 summarizes the c64x+ interrupt controller registers and memory locations. for more details on dsp interrupt control, see the tms320dm646x dmsoc dsp subsystem reference guide (literature number spruep8 ). table 7-26. dm6467 dsp interrupts dsp dsp interrupt acronym source interrupt acronym source number number 0 evt0 c64x+ int ctl 0 64 gpio0 gpio 1 evt1 c64x+ int ctl 1 65 gpio1 gpio 2 evt2 c64x+ int ctl 2 66 gpio2 gpio 3 evt3 c64x+ int ctl 3 67 gpio3 gpio 4 tintl0 timer 0 lower ? tint12 68 gpio4 gpio 5 tinth0 timer 0 upper ? tint34 69 gpio5 gpio 6 tintl1 timer 1 lower ? tint12 70 gpio6 gpio 7 tinth1 timer 1 upper ? tint34 71 gpio7 gpio 8 ? reserved 72 ? reserved 9 emu_dtdma c64x+ emc 73 ? reserved 10 ? reserved 74 ? reserved 11 emu_rtdxrx c64x+ rtdx 75 ? reserved 12 emu_rtdxtx c64x+ rtdx 76 ? reserved 13 idmaint0 c64x+ emc 0 77 ? reserved 14 idmaint1 c64x+ emc 1 78 ? reserved 15 ? reserved 79 ? reserved 16 arm2dsp0 arm to dsp controller 0 80 ? reserved 17 arm2dsp1 arm to dsp controller 1 81 ? reserved 18 arm2dsp2 arm to dsp controller 2 82 ? reserved 19 arm2dsp3 arm to dsp controller 3 83 ? reserved 20 ? reserved 84 ccint1 edma cc region 1 21 ? reserved 85 ccerrint edma cc error 22 ? reserved 86 tcerrint0 edma tc0 error 23 ? reserved 87 tcerrint1 edma tc1 error 24 ? reserved 88 tcerrint2 edma tc2 error 25 ? reserved 89 tcerrint3 edma tc3 error 26 ? reserved 90 ideint ata 27 ? reserved 91 ? reserved 28 ? reserved 92 ? reserved 29 ? reserved 93 ? reserved 30 ? reserved 94 ? reserved 31 ? reserved 95 ? reserved ? reserved interr c64x+ interrupt controller 32 96 dropped cpu interrupt event ? reserved emc_idmaerr c64x+ emc invalid idma 33 97 parameters 34 ? reserved 98 ? reserved 35 ? reserved 99 ? reserved 36 ? reserved 100 ? reserved peripheral information and electrical specifications 200 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-26. dm6467 dsp interrupts (continued) dsp dsp interrupt acronym source interrupt acronym source number number 37 ? reserved 101 ? reserved 38 ? reserved 102 ? reserved 39 ? reserved 103 ? reserved 40 ? reserved 104 ? reserved 41 ? reserved 105 ? reserved 42 ? reserved 106 ? reserved 43 ? reserved 107 ? reserved 44 ? reserved 108 ? reserved 45 ? reserved 109 ? reserved 46 ? reserved 110 ? reserved 47 ? reserved 111 ? reserved 48 ? reserved 112 ? reserved 49 ? reserved 113 pmc_ed c64x+ pmc 50 ? reserved 114 ? reserved 51 ? reserved 115 ? reserved 52 ? reserved 116 umced1 c64x+ umc 1 53 ? reserved 117 umced2 c64x+ umc 2 54 axint0 mcasp 0 transmit 118 pdcint c64x+ pdc 55 arint0 mcasp 0 receive 119 syscmpa c64x+ sys 56 axint1 mcasp 1 transmit 120 pmccmpa c64x+ pmc 57 ? reserved 121 pmcdmpa c64x+ pmc 58 ? reserved 122 dmccmpa c64x+ dmc 59 ? reserved 123 dmcdmpa c64x+ dmc 60 ? reserved 124 umccmpa c64x+ umc 61 ? reserved 125 umcdmpa c64x+ umc 62 ? reserved 126 emccmpa c64x+ emc 63 ? reserved 127 emcbuserr c64x+ emc submit documentation feedback peripheral information and electrical specifications 201
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-27. c64x+ interrupt controller registers hex address acronym register name range 0x0180 0000 evtflag0 event flag register 0 0x0180 0004 evtflag1 event flag register 1 0x0180 0008 evtflag2 event flag register 2 0x0180 000c evtflag3 event flag register 3 0x0180 0020 evtset0 event set register 0 0x0180 0024 evtset1 event set register 1 0x0180 0028 evtset2 event set register 2 0x0180 002c evtset3 event set register 3 0x0180 0040 evtclr0 event clear register 0 0x0180 0044 evtclr1 event clear register 1 0x0180 0048 evtclr2 event clear register 2 0x0180 004c evtclr3 event clear register 3 0x0180 0080 evtmask0 event mask register 0 0x0180 0084 evtmask1 event mask register 1 0x0180 0088 evtmask2 event mask register 2 0x0180 008c evtmask3 event mask register 3 0x0180 00a0 mevtflag0 masked event flag register 0 0x0180 00a4 mevtflag1 masked event flag register 1 0x0180 00a8 mevtflag2 masked event flag register 2 0x0180 00ac mevtflag3 masked event flag register 3 0x0180 00c0 expmask0 exception mask register 0 0x0180 00c4 expmask1 exception mask register 1 0x0180 00c8 expmask2 exception mask register 2 0x0180 00cc expmask3 exception mask register 3 0x0180 00e0 mexpflag0 masked exception flag register 0 0x0180 00e4 mexpflag1 masked exception flag register 1 0x0180 00e8 mexpflag2 masked exception flag register 2 0x0180 00ec mexpflag3 masked exception flag register 3 0x0180 0104 intmux1 interrupt mux register 1 0x0180 0108 intmux2 interrupt mux register 2 0x0180 010c intmux3 interrupt mux register 3 0x0180 0180 intxstat interrupt exception status 0x0180 0184 intxclr interrupt exception clear 0x0180 0188 intdmask dropped interrupt mask register peripheral information and electrical specifications 202 submit documentation feedback
7.9 external memory interface (emif) 7.9.1 asynchronous emif (emifa) 7.9.2 nand (nand, smartmedia/ssfdc, xd) 7.9.3 emifa peripheral register description(s) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 dm6467 supports several memory and external device interfaces, including: asynchronous emif (emifa) for interfacing to nor flash, sram, etc. nand flash ata (see section 7.20 , ata controller) the dm6467 asynchronous emif (emifa) provides an 8-bit or 16-bit data bus, an address bus width up to 24 bits, and 4 chip selects, along with memory control signals. these signals are multiplexed between these peripherals: emifa and nand interfaces ata interface host-port interface (hpi) pci gpio the emifa interface provides both the asynchronous emif and nand interfaces. four chip selects are provided and each are individually configurable to provide either emifa or nand support. the nand features supported are as follows. nand flash on up to 4 asynchronous chip selects 8- or 16-bit data bus width programmable cycle timings performs ecc calculation nand mode also supports smartmedia/ssfdc (solid state floppy disk controller) and xd memory cards arm rom supports booting of the dm6467 arm926 processor from nand flash located at cs2 the memory map for emifa and nand registers is shown in table 7-28 . for more details on the emifa and nand interfaces, the tms320dm646x dmsoc asynchronous external memory interface (emif) user's guide (literature number sprueq7 ). table 7-28 shows the emifa/nand registers. submit documentation feedback peripheral information and electrical specifications 203
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-28. emifa/nand registers hex address range acronym register name 0x2000 8000 rcsr revision code and status register 0x2000 8004 awccr asynchronous wait cycle configuration register 0x2000 8008 - 0x2000 800f ? reserved 0x2000 8010 a1cr asynchronous 1 configuration register (cs2 space) 0x2000 8014 a2cr asynchronous 2 configuration register (cs3 space) 0x2000 8018 a3cr asynchronous 3 configuration register (cs4 space) 0x2000 801c a4cr asynchronous 4 configuration register (cs5 space) 0x2000 8020 - 0x2000 803f ? reserved 0x2000 8040 eirr emif interrupt raw register 0x2000 8044 eimr emif interrupt mask register 0x2000 8048 eimsr emif interrupt mask set register 0x2000 804c eimcr emif interrupt mask clear register 0x2000 8050 - 0x2000 805f ? reserved 0x2000 8060 nandfcr nand flash control register 0x2000 8064 nandfsr nand flash status register 0x2000 8070 nandf1ecc nand flash 1 ecc register (cs2 space) 0x2000 8074 nandf2ecc nand flash 2 ecc register (cs3 space) 0x2000 8078 nandf3ecc nand flash 3 ecc register (cs4 space) 0x2000 807c nandf4ecc nand flash 4 ecc register (cs5 space) 0x2000 8080 - 0x2000 8fff ? reserved peripheral information and electrical specifications 204 submit documentation feedback
7.9.4 emifa electrical data/timing tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-29. timing requirements for asynchronous memory cycles for emifa module (1) (see figure 7-22 and figure 7-23 ) -594, -729 no. unit min max reads and writes 2 t w(em_wait) pulse duration, em_waitx assertion and deassertion 2e ns reads 12 t su(emdv-emoeh) setup time, em_d[15:0] valid before em_oe high 5 ns 13 t h(emoeh-emdiv) hold time, em_d[15:0] valid after em_oe high 0 ns 14 t su(emwait-emoeh) setup time, em_waitx asserted before em_oe high (2) 4e + 3 ns writes 28 t su(emwait-emweh) setup time, em_waitx asserted before em_we high (2) 4e + 3 ns (1) e = sysclk3 period in ns for emifa. for example, when running the dsp cpu at 594 mhz, use e = 6.734 ns. (2) setup before end of strobe phase (if no extended wait states are inserted) by which em_waitx must be asserted to add extended wait states. figure 7-24 and figure 7-25 describe emif transactions that include extended wait states inserted during the strobe phase. however, cycles inserted as part of this extended wait period should not be counted; the 4e requirement is to the start of where the hold phase would begin if there were no extended wait cycles. submit documentation feedback peripheral information and electrical specifications 205
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-30. switching characteristics over recommended operating conditions for asynchronous memory cycles for emifa module (1) (2) (see figure 7-22 and figure 7-23 ) -594, -729 no. parameter unit min max reads and writes 1 t d(turnaround) turn around time (ta + 1) * e - 3 (ta + 1) * e + 3 ns reads (rs + rst + rh + (rs + rst + rh + ta + emif read cycle time (ew = 0) ns ta + 4) * e - 3 4) * e + 3 3 t c(emrcycle) (rs + rst + rh + emif read cycle time (ew = 1) 4184 * e + 3 ns ta + 4) * e - 3 output setup time, em_cs[5:2] low to em_oe low (rs + 1) * e - 3 (rs + 1) * e + 3 ns (ss = 0) 4 t su(emcsl-emoel) output setup time, em_cs[5:2] low to em_oe low 3 ns (ss = 1) output hold time, em_oe high to em_cs[5:2] high (rh + 1) * e - 3 (rh + 1) * e + 3 ns (ss = 0) 5 t h(emoeh-emcsh) output hold time, em_oe high to em_cs[5:2] high 3 ns (ss = 1) 6 t su(embav-emoel) output setup time, em_ba[1:0] valid to em_oe low (rs + 1) * e - 3 (rs + 1) * e + 3 ns 7 t h(emoeh-embaiv) output hold time, em_oe high to em_ba[1:0] invalid (rh + 1) * e - 3 (rh + 1) * e + 3 ns 8 t su(embav-emoel) output setup time, em_a[22:0] valid to em_oe low (rs + 1) * e - 3 (rs + 1) * e + 3 ns 9 t h(emoeh-embaiv) output hold time, em_oe high to em_a[22:0] invalid (rh + 1) * e - 3 (rh + 1) * e + 3 ns em_oe active low width (ew = 0) (rst + 1) * e - 3 (rst + 1) * e + 3 ns 10 t w(emoel) em_oe active low width (ew = 1) (rst + 1) * e - 3 (rst + 4097) * e + 3 ns 11 t d(emwaith-emoeh) delay time from em_waitx deasserted to em_oe high 4e + 3 ns writes (ws + wst + wh (ws + wst + wh + ta emif write cycle time (ew = 0) ns + ta + 4) * e - 3 + 4) * e + 3 15 t c(emwcycle) (ws + wst + wh emif write cycle time (ew = 1) 4184 * e + 3 ns + ta + 4) * e - 3 output setup time, em_cs[5:2] low to em_we low (ws + 1) * e - 3 (ws + 1) * e + 3 ns (ss = 0) 16 t su(emcsl-emwel) output setup time, em_cs[5:2] low to em_we low 3 ns (ss = 1) output hold time, em_we high to em_cs[5:2] high (wh + 1) * e - 3 (wh + 1) * e + 3 ns (ss = 0) 17 t h(emweh-emcsh) output hold time, em_we high to em_cs[5:2] high 3 ns (ss = 1) 18 t su(emrnw-emwel) output setup time, em_r/ w valid to em_we low (ws + 1) * e - 3 (ws + 1) * e + 3 ns 19 t h(emweh-emrnw) output hold time, em_we high to em_r/ w invalid (wh + 1) * e - 3 (wh + 1) * e + 3 ns 20 t su(embav-emwel) output setup time, em_ba[1:0] valid to em_we low (ws + 1) * e - 3 (ws + 1) * e + 3 ns 21 t h(emweh-embaiv) output hold time, em_we high to em_ba[1:0] invalid (wh + 1) * e - 3 (wh + 1) * e + 3 ns 22 t su(emav-emwel) output setup time, em_a[22:0] valid to em_we low (ws + 1) * e - 3 (ws + 1) * e + 3 ns 23 t h(emweh-emaiv) output hold time, em_we high to em_a[22:0] invalid (wh + 1) * e - 3 (wh + 1) * e + 3 ns em_we active low width (ew = 0) (wst + 1) * e - 3 (wst + 1) * e + 3 ns 24 t w(emwel) em_we active low width (ew = 1) (wst + 1) * e - 3 (wst + 4097) * e + 3 ns 25 t d(emwaith-emweh) delay time from em_waitx deasserted to em_we high 4e + 3 ns 26 t su(emdv-emwel) output setup time, em_d[15:0] valid to em_we low (ws + 1) * e - 3 (ws + 1) * e + 3 ns (1) rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold, ta = turn around, ew = extend wait mode, ss = select strobe mode. these parameters are programmed via the asynchronous n configuration and the asynchronous wait cycle configuration registers and support the following range of values: ta[0?3], rs[0?15], rst[0?63], rh[0?7], ws[0?15], wst[0?63], wh[0?7], ew[0?1], and mewc[0?255]. for more information, see the tms320dm646x dmsoc asynchronous external memory interface (emif) user's guide (literature number sprueq7 ). (2) e = sysclk3 period in ns for emifa. for example, when running the dsp cpu at 594 mhz, use e = 6.734 ns. peripheral information and electrical specifications 206 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-30. switching characteristics over recommended operating conditions for asynchronous memory cycles for emifa module (see figure 7-22 and figure 7-23 ) (continued) -594, -729 no. parameter unit min max 27 t h(emweh-emdiv) output hold time, em_we high to em_d[15:0] invalid (wh + 1) * e - 3 (wh + 1) * e + 3 ns figure 7-22. asynchronous memory read timing for emif submit documentation feedback peripheral information and electrical specifications 207 em_cs[5:2] em_ba[1:0] 13 12 em_a[22:0] em_oe em_d[15:0] em_we 10 5 9 7 4 8 6 3 1 em_r/w
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com figure 7-23. asynchronous memory write timing for emif figure 7-24. em_waitx read timing requirements 208 peripheral information and electrical specifications submit documentation feedback em_cs[5:2] em_ba[1:0] em_a[22:0] em_we em_d[15:0] em_oe em_r/w 15 1 16 18 20 22 24 17 19 21 23 26 27 em_cs[5:2] 11 asserted deasserted 2 2 em_ba[1:0] em_a[22:0]em_d[15:0] em_oe em_wait[5:2] setup strobe extended due to em_wait strobe hold 14 em_dqm[1:0]
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 figure 7-25. em_waitx write timing requirements submit documentation feedback peripheral information and electrical specifications 209 em_cs[5:2] 25 asserted deasserted 2 2 em_ba[1:0] em_a[22:0]em_d[15:0] em_we em_wait[5:2] setup strobe extended due to em_wait strobe hold 28 em_dqm[1:0]
7.10 ddr2 memory controller tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the ddr2 memory controller is a dedicated interface to ddr2 sdram. it supports jesd79d-2a standard compliant ddr2 sdram devices and can interface to either 16-bit or 32-bit ddr2 sdram devices. for details on the ddr2 memory controller, see the tms320dm646x dmsoc ddr2 memory controller user's guide (literature number sprueq4 ). a memory map of the ddr2 memory controller registers is shown in table 7-31 . table 7-31. ddr2 memory controller registers hex address range acronym register name 0x01c4 004c ? reserved 0x01c4 2038 ? reserved 0x2000 0000 - 0x2000 0003 ? reserved 0x2000 0004 sdrstat sdram status register 0x2000 0008 sdbcr sdram bank configuration register 0x2000 000c sdrcr sdram refresh control register 0x2000 0010 sdtimr sdram timing register 1 0x2000 0014 sdtimr2 sdram timing register 2 0x2000 0018 - 0x2000 001f ? reserved 0x2000 0020 pbbpr peripheral bus burst priority register 0x2000 0024 - 0x2000 00bf ? reserved 0x2000 00c0 irr interrupt raw register 0x2000 00c4 imr interrupt masked register 0x2000 00c8 imsr interrupt mask set register 0x2000 00cc imcr interrupt mask clear register 0x2000 00d0 - 0x2000 00e3 ? reserved 0x2000 00e4 ddrphycr ddr2 phy control register 0x2000 00e8 - 0x2000 00ef ? reserved 0x2000 00f0 vtpiocr ddr2 vtp io control register 0x2000 00f4 - 0x2000 7fff ? reserved peripheral information and electrical specifications 210 submit documentation feedback
7.10.1 ddr2 memory controller electrical data/timing 7.10.2 ddr2 interface 7.10.2.1 ddr2 interface schematic 7.10.2.2 compatible jedec ddr2 devices tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 ti only supports board designs that follow the guidelines outlined in this document. table 7-32. switching characteristics over recommended operating conditions for ddr2 memory controller (1) (2) (see figure 7-26 ) -594 -729 no. parameter unit min max min max 1 t c(ddr_clk) cycle time, ddr_clk 3.367 8 3.220 8 ns (1) ddr_clk cycle time = 2 x pll2 _sysclk1 cycle time. (2) the pll2 controller must be programmed such that the resulting ddr_clk clock frequency is within the specified range. figure 7-26. ddr2 memory controller clock timing this section provides the timing specification for the ddr2 interface as a pcb design and manufacturing specification. the design rules constrain pcb trace length, pcb trace skew, signal integrity, cross-talk, and signal timing. these rules, when followed, result in a reliable ddr2 memory system without the need for a complex timing closure process. for more information regarding the guidelines for using this ddr2 specification, see understanding ti?s pcb routing rule-based ddr2 timing specification application report (spraav0 ). figure 7-27 shows the ddr2 interface schematic for a x32 ddr2 memory system. the x16 ddr2 system schematic is identical except that the high word ddr2 device is deleted, see figure 7-28 . the pin numbers for the dm6467 can be obtained from the section 3.6 , pin assignments of this document. table 7-33 shows the parameters of the jedec ddr2 devices that are compatible with this interface. generally, the ddr2 interface is compatible with x16 ddr2-667 speed grade ddr2 devices. table 7-33. compatible jedec ddr2 devices no. parameter min max unit 1 jedec ddr2 device speed grade (1) ddr2-667 2 jedec ddr2 device bit width x16 x16 bits 3 jedec ddr2 device count (2) 1 2 devices 4 jedec ddr2 device ball count (3) 84 92 balls (1) higher ddr2 speed grades are supported due to inherent jedec ddr2 backwards compatibility. (2) 1 ddr2 device is used for 16 bit ddr2 memory system. 2 ddr2 devices are used for 32 bit ddr2 memory system. (3) 92 ball devices retained for legacy support. new designs will migrate to 84 ball ddr2 devices. electrrically the 92 and 84 ball ddr2 devices are the same. submit documentation feedback peripheral information and electrical specifications 211 ddr_clk 1
7.10.2.3 pcb stackup tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the minimum stackup required for routing the dm6467 is a six layer stack as shown in table 7-34 . additional layers may be added to the pcb stack up to accommodate other circuity or to reduce the size of the pcb footprint. table 7-34. dm6467 minimum pcb stack up layer type description 1 signal top routing mostly horizontal 2 plane ground 3 plane power 4 signal internal routing 5 plane ground 6 signal bottom routing mostly vertical peripheral information and electrical specifications 212 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 complete stack up specifications are provided in table 7-35 . figure 7-27. dm6467 32-bit ddr2 high level schematic submit documentation feedback peripheral information and electrical specifications 213 ddr_d0 ddr_d7 ddr_dqm0 ddr_dqs0ddr_dqs0 ddr_d8 ddr_d15 ddr_dqm1 ddr_dqs1ddr_dqs1 dq0dq7 ldm ldqs ldqs dq8dq15 udm udqs udqs ba0ba2 a0 a14 cs cas ras we ckeck ck vref dq0dq7 ldm ldqs ldqs dq8dq15 udm udqs udqs ba0ba2 a0 a14 cs cas ras we ckeck ck vref ddr_d16 ddr_d23 ddr_dqm2 ddr_dqs2ddr_dqs2 ddr_d24 ddr_d31 ddr_dqm3 ddr_dqs3ddr_dqs3 ddr_ba0 ddr_ba2 ddr_a0 ddr_a14 ddr_cs ddr_cas ddr_ras ddr_we ddr_cke ddr_clkddr_clk odt ddr_vref 1k 1% vio1.8 (a) ddr2 ddr2 ddr_dqgate0 ddr_dqgate1 ddr_dqgate2 ddr_dqgate3 vref terminator, if desired. see terminator comments. a vio1.8 is the power supply for the ddr2 memories and dm646x ddr2 interface. b one of these capacitors can be eliminated if the divider and its capacitors are placed near a device vref pin. t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t 0.1 f vref vref 0.1 f 1k 1% 0.1 f (b) 0.1 f (b) ddr_odt0 nc odt dm646x 50 (5%) 50 (5%) t t t ddr_zn ddr_zp 0.1 f (b) dv ddr2
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com figure 7-28. dm6467 16-bit ddr2 high level schematic 214 peripheral information and electrical specifications submit documentation feedback ddr_d0 ddr_d7 ddr_dqm0 ddr_dqs0ddr_dqs0 ddr_d8 ddr_d15 ddr_dqm1 ddr_dqs1 ddr_dqs1 dq0dq7 ldm ldqs ldqs dq8dq15 udm udqs udqs ba0ba2 a0 a14 cs cas ras we ckeck ck vref ddr_d16 ddr_d23 ddr_dqm2 ddr_dqs2 ddr_dqs2 ddr_d24 ddr_d31 ddr_dqm3 ddr_dqs3 ddr_dqs3 ddr_ba0 ddr_ba2 ddr_a0 ddr_a14 ddr_cs ddr_cas ddr_ras ddr_we ddr_cke ddr_clkddr_clk ddr_vref 1k 1% vio1.8 (a) ddr2 ddr_dqgate0 ddr_dqgate1 ddr_dqgate2 ddr_dqgate3 vref terminator, if desired. see terminator comments. a vio1.8 is the power supply for the ddr2 memories and dm646x ddr2 interface. b one of these capacitors can be eliminated if the divider and its capacitors are placed near a device vref pin. t t t t t t t t t t t t t t t t t t t t t 0.1 f vref 0.1 f 1k 1% 0.1 f (b) 0.1 f (b) ddr_odt0 nc odt dm646x ncnc ncnc 1k nc nc 1k 1k 1k t t t ddr_zp ddr_zn 50 ( 5%) 50 ( 5%) vio1.8 (a) vio1.8 (a) dv ddr2
7.10.2.4 placement tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-35. pcb stack up specifications no. parameter min typ max unit 1 pcb routing/plane layers 6 2 signal routing layers 3 3 full ground layers under ddr2 routing region 2 4 number of ground plane cuts allowed within ddr routing region 0 5 number of ground reference planes required for each ddr2 routing layer 1 6 number of layers between ddr2 routing layer and reference ground plane 0 7 pcb routing feature size 4 mils 8 pcb trace width w 4 mils 8 pcb bga escape via pad size 18 mils 9 pcb bga escape via hole size 8 mils 10 dsp device bga pad size (1) 11 ddr2 device bga pad size (2) 12 single ended impedance, zo 50 75 w 13 impedance control (3) z-5 z z+5 w (1) see the flip chip ball grid array package reference guide (spru811 ) for dsp device bga pad size. (2) see the ddr2 device manufacturer documenation for the ddr2 device bga pad size. (3) z is the nominal singled ended impedance selected for the pcb specified by item 12. figure 7-29 shows the required placement for the dm6467 device as well as the ddr2 devices. the dimensions for figure 7-29 are defined in table 7-36 . the placement does not restrict the side of the pcb that the devices are mounted on. the ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. for a 16 bit ddr memory systems, the high word ddr2 device is omitted from the placement. figure 7-29. dm6467 and ddr2 device placement submit documentation feedback peripheral information and electrical specifications 215 a1a1 x y offset recommended ddr2 device orientation y y offset ddr2 device ddr2 controller dm646x
7.10.2.5 ddr2 keep out region tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-36. placement specifications no. parameter min max unit 1 x (1) (2) 1660 mils 2 y (1) (2) 1280 mils 3 y offset (1) (2) (3) 650 mils 4 ddr2 keepout region (4) 5 clearance from non-ddr2 signal to ddr2 keepout region (5) 4 w (1) see figure 7-27 for dimension defintions. (2) measurements from center of dsp device to center of ddr2 device. (3) for 16 bit memory systems it is recommended that y offset be as small as possible. (4) ddr2 keepout region to encompass entire ddr2 routing area (5) non-ddr2 signals allowed within ddr2 keepout region provided they are separated from ddr2 routing layers by a ground plane. the region of the pcb used for the ddr2 circuitry must be isolated from other signals. the ddr2 keep out region is defined for this purpose and is shown in figure 7-30 . the size of this region varies with the placement and ddr routing. additional clearances required for the keep out region are shown in table 7-36 . figure 7-30. ddr2 keepout region note the region shown in figure 7-30 should encompass all the ddr2 circuitry and varies depending on placement. non-ddr2 signals should not be routed on the ddr signal layers within the ddr2 keep out region. non-ddr2 signals may be routed in the region provided they are routed on layers separated from ddr2 signal layers by a ground layer. no breaks should be allowed in the reference ground layers in this region. in addition, the 1.8-v power plane should cover the entire keep out region. peripheral information and electrical specifications 216 submit documentation feedback a1a1 ddr2 controller ddr2 device
7.10.2.6 bulk bypass capacitors 7.10.2.7 high-speed bypass capacitors 7.10.2.8 net classes tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 bulk bypass capacitors are required for moderate speed bypassing of the ddr2 and other circuitry. table 7-37 contains the minimum numbers and capacitance required for the bulk bypass capacitors. note that this table only covers the bypass needs of the dsp and ddr2 interfaces. additional bulk bypass capacitance may be needed for other circuitry. table 7-37. bulk bypass capacitors no. parameter min max unit 1 dv dd18 bulk bypass capacitor count (1) 3 devices 2 dv dd18 bulk bypass total capacitance 30 m f 3 ddr#1 bulk bypass capacitor count (1) 1 devices 4 ddr#1 bulk bypass total capacitance (1) 10 m f 5 ddr#2 bulk bypass capacitor count (2) 1 devices 6 ddr#2 bulk bypass total capacitance (1) (2) 10 m f (1) these devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed (hs) bypass caps. (2) only used on 32-bit wide ddr2 memory systems high-speed (hs) bypass capacitors are critical for proper ddr2 interface operation. it is particularly important to minimize the parasitic series inductance of the hs bypass cap, dsp/ddr power, and dsp/ddr ground connections. table 7-38 contains the specification for the hs bypass capacitors as well as for the power connections on the pcb. table 7-39 lists the clock net classes for the ddr2 interface. table 7-40 lists the signal net classes, and associated clock net classes, for the signals in the ddr2 interface. these net classes are used for the termination and routing rules that follow. table 7-38. high-speed bypass capacitors no. parameter min max unit 1 hs bypass capacitor package size (1) 0402 10 mils 2 distance from hs bypass capacitor to device being bypassed 250 mils 3 number of connection vias for each hs bypass capacitor (2) 2 vias 4 trace length from bypass capacitor contact to connection via 1 30 mils 5 number of connection vias for each dsp device power or ground balls 1 vias 6 trace length from dsp device power ball to connection via 35 mils 7 number of connection vias for each ddr2 device power or ground balls 1 vias 8 trace length from ddr2 device power ball to connection via 35 mils 9 dv dd18 hs bypass capacitor count (3) 20 devices 10 dv dd18 hs bypass capacitor total capacitance 1.2 m f 11 ddr#1 hs bypass capacitor count (3) 8 devices 12 ddr#1 hs bypass capacitor total capacitance 0.4 m f 13 ddr#2 hs bypass capacitor count (3) (4) 8 devices 14 ddr#2 hs bypass capacitor total capacitance (4) 0.4 m f (1) lxw, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor (2) an additional hs bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. (3) these devices should be placed as close as possible to the device being bypassed. (4) only used on 32-bit wide ddr2 memory systems submit documentation feedback peripheral information and electrical specifications 217
7.10.2.9 ddr2 signal termination tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-39. clock net class definitions clock net class dsp pin names ck ddr_clk/ ddr_clk dqs0 ddr_dqs0/ ddr_dqs0 dqs1 ddr_dqs1/ ddr_dqs1 dqs2 (1) ddr_dqs2/ ddr_dqs2 dqs3 (1) ddr_dqs3/ ddr_dqs3 (1) only used on 32-bit wide ddr2 memory systems. table 7-40. signal net class definitions associated clock net clock net class class dsp pin names addr_ctrl ck ddr_ba[2:0], ddr_a[14:0], ddr_cs, ddr_cas, ddr_ras, ddr_we, ddr_cke dq0 dqs0 ddr_dq[7:0], ddr_dqm0 dq1 dqs1 ddr_dq[15:8], ddr_dqm1 dq2 (1) dqs2 ddr_dq[23:16], ddr_dqm2 dq3 (1) dqs3 ddr_dq[31:24], ddr_dqm3 dqgatel ck, dqs0, dqs1 ddr_dqgate0, ddr_dqgate1 dqgateh (1) ck, dqs2, dqs3 ddr_dqgate2, ddr_dqgate3 (1) only used on 32-bit wide ddr2 memory systems. no terminations of any kind are required in order to meet signal integrity and overshoot requirements. serial terminators are permitted, if desired, to reduce emi risk; however, serial terminations are the only type permitted. table 7-41 shows the specifications for the series terminators. table 7-41. ddr2 signal terminations no. parameter min typ max unit 1 ck net class (1) 0 10 w 2 addr_ctrl net class (1) (2) (3) 0 22 zo w 3 data byte net classes (dqs0-dqs3, dq0-dq3) (1) (2) (3) (4) 0 22 zo w 4 dqgate net classes (dqgatel, dqgateh) (1) (2) (3) 0 10 zo w (1) only series termination is permitted, parallel or sst specifically disallowed. (2) terminator values larger than typical only recommended to address emi issues. (3) termination value should be uniform across net class. (4) when no termination is used on data lines (0 w s), the ddr2 devices must be programmed to operate in 60% strength mode. 218 peripheral information and electrical specifications submit documentation feedback
7.10.2.10 vref routing 7.10.2.11 ddr2 ck and addr_ctrl routing tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 vref is used as a reference by the input buffers of the ddr2 memories as well as the dm6467?s. vref is intended to be 1/2 the ddr2 power supply voltage and should be created using a resistive divider as shown in figure 7-28 . other methods of creating vref are not recommended. figure 7-31 shows the layout guidelines for vref. figure 7-31. vref routing and topology figure 7-32 shows the topology of the routing for the ck and addr_ctrl net classes. the route is a balanced t as it is intended that the length of segments b and c be equal. in addition, the length of a should be maximized. figure 7-32. ck and addr_ctrl routing and topology submit documentation feedback peripheral information and electrical specifications 219 dm646x device a1 a1 ddr2 device vref nominal minimum trace width is 20 mils vref bypass capacitor neck down to minimum in bga escape regions is acceptable. narrowing to accomodate via congestion for short distances is also acceptable. best performance is obtained if the width of vref is maximized. a1 a1 c b a t ddr2 controller dm646x
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-42. ck and addr_ctrl routing specification (1) no parameter min typ max unit 1 center to center ck- ck spacing 2w 2 ck a to b/a to c skew length mismatch (1) 25 mils 3 ck b to c skew length mismatch 25 mils 4 center to center ck to other ddr2 trace spacing (2) 4w 5 ck/addr_ctrl nominal trace length (3) caclm-50 caclm caclm+50 mils 6 addr_ctrl to ck skew length mismatch 100 mils 7 addr_ctrl to addr_ctrl skew length mismatch 100 mils 8 center to center addr_ctrl to other ddr2 trace spacing (2) 4w 9 center to center addr_ctrl to other addr_ctrl trace spacing (2) 3w 10 addr_ctrl a to b/a to c skew length mismatch (1) 100 mils 11 addr_ctrl b to c skew length mismatch 100 mils (1) series terminator, if used, should be located closest to dsp. (2) center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate bga escape and routing congestion. (3) caclm is the longest manhattan distance of the ck and addr_ctrl net classes. figure 7-33 shows the topology and routing for the dqs and dq net classes; the routes are point to point. skew matching across bytes is not needed nor recommended. figure 7-33. dqs and dq routing and toplogy peripheral information and electrical specifications 220 submit documentation feedback a1 a1 e0 t e1 t e2 dm646x e3 t ddr2 controller t
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-43. dqs and dq routing specification (1) no. parameter min typ max unit 1 center to center dqs- dqs spacing 2w 2 dqs e skew length mismatch 25 mils 3 center to center dqs to other ddr2 trace spacing (2) 4w 4 dqs/dq nominal trace length (1) (3) (4) (5) dqlm-50 dqlm dqlm+50 mils 5 dq to dqs skew length mismatch (3) (4) (5) 100 mils 6 dq to dq skew length mismatch (3) (4) (5) 100 mils 7 center to center dq to other ddr2 trace spacing (2) (6) 4w 8 center to center dq to other dq trace spacing (2) (7) (8) 3w 9 dq/dqs e skew length mismatch (3) (4) (5) 100 mils (1) series terminator, if used, should be located closest to ddr. (2) center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate bga escape and routing congestion. (3) a 16 bit ddr memory system will have two sets of data net classes, one for data byte 0, and one for data byte 1, each with an associated dqs (2 dqs's). (4) a 32 bit ddr memory system will have four sets of data net classes, one each for data bytes 0 through 3, and each associated with a dqs (4 dqs's). (5) there is no need and it is not recommended to skew match across data bytes, ie from dqs0 and data byte 0 to dqs1 and data byte 1. (6) dq's from other dqs domains are considered other ddr2 trace. (7) dq's from other data bytes are considered other ddr2 trace. (8) dqlm is the longest manhattan distance of each of the dqs and dq net classes. figure 7-34 shows the routing for the dqgate net classes. table 7-44 contains the routing specification. figure 7-34. dqgate routing submit documentation feedback peripheral information and electrical specifications 221 a1a1 tt fh fl ddr2 controller dm646x
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-44. dqgate routing specification no. parameter min typ max unit 1 dqgatel length f (1) ckb0b1 2 dqgateh length f (2) (3) ckb2b3 3 center to center dqgate to any other trace spacing 4w 4 dqs/dq nominal trace length dqlm-50 dqlm dqlm+50 mils 5 dqgatel skew (4) 100 mils 6 dqgateh skew (3) (5) 100 mils (1) ckb0b1 is the sum of the length of the ck net plus the average length of the dqs0 and dqs1 nets. (2) ckb2b3 is the sum of the length of the ck net plus the average length of the dqs2 and dqs3 nets. (3) only used in 32-bit wide ddr2 memory systems. (4) skew from ckb0b1 (5) skew from ckb2b3 peripheral information and electrical specifications 222 submit documentation feedback
7.11 video port interface (vpif) 7.11.1 vpif bus master memory map 7.11.2 vpif clock control (capture and display) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the dm6467 video port interface (vpif) allows the capture and display of digital video streams. features include: 99-mhz vpif (-594 devices only) and 108-mhz vpif (-729 devices only) up to 2 video capture channels (channel 0 and channel 1) ? two 8-bit standard-definition (sd) video with embedded timing codes (bt.656) ? single 16-bit high-definition (hd) video with embedded timing codes (bt.1120) ? single raw video (8-/10-/12-bit) up to 2 video display channels (channel 2 and channel 3) ? two 8-bit sd video display with embedded timing codes (bt.656) ? single 16-bit hd video display with embedded timing codes (bt.1120) the vpif capture channel input data format is selectable based on the settings of the specific channel control register (channels 0?3). the vpif raw video data-bus width is selectable based on the settings of the channel 0 control register. for more detailed information on these specific channel control registers, see the tms320dm646x dmsoc video port interface (vpif) user's guide (literature number spruer9 ). the vpif peripheral includes a bus master interface that accesses the dm6467 system bus to transfer video-capture and video-display data. table 7-45 shows the memory map for the vpif master interface. table 7-45. vpif master memory map start end size vpif master interface address address (bytes) 0x0000 0000 0x7fff ffff 2g reserved 0x8000 0000 0x9fff ffff 512m ddr2 memory controller 0xa000 0000 0xbfff ffff 512m reserved 0xc000 0000 0xffff ffff 1g reserved the source clocks for the vpif data channels are selectable based on the settings of the vidclkctl register (0x01c4 0038) (for the vidclkctl register details, see section 4.3.2.1 , video clock control register). the vsclkdis register (0x01c4 006c) is used to disable the clock inputs when changing the clock source to ensure glitch-free operation. (for the vsclkdis register details, see section 4.3.2.3 , video and tsif clock disable). for both the vpif dual 8-bit or 16-bit video-capture modes, channel 0 is always clocked by vp_clkin0 (see figure 7-35 ). figure 7-35. vpif capture channel 0 source clock video-capture channel 1 is clocked by the vp_clkin1 signal, when the dual 8-bit capture mode is enabled. when the 16-bit capture mode or 8-/10-/12-bit raw-capture mode is used, vp_clkin0 must be selected as the clock source (vidclkctl.vch1clk = 0) [see figure 7-36 ]. submit documentation feedback peripheral information and electrical specifications 223 vp_clkin0 vpifchannel 0 input clock source vp_clkin0 vsclkdis.vid0
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com figure 7-36. vpif capture channel 1 source clock selection for both the dual 8-bit or 16-bit display modes, the vpif display channel 2 outputs data synchronous to vp_clko2. the source clock for the vp_clko2 output is selectable from a number of external clock inputs or on-chip clock sources (see figure 7-37 ). (a) 111 = reserved. (b) for the -729 devices, use an external clock source for the 54-/74.25-/108-mhz vpif clock. figure 7-37. vpif display channel 2 source clock selection for the dual 8-bit display mode, the vpif display channel 3 outputs data synchronous to vp_clko3. the source clock for the vp_clko3 output is selectable from a number of external clock inputs or on-chip clock sources (see figure 7-38 ). when the 16-bit display mode for channel 3 is selected, the clock source must match that of channel 2 (vidclkctl.vch3clk = vch2clk). 224 peripheral information and electrical specifications submit documentation feedback vidclkctl.vch1clk vp_clkin1vp_clkin0 vpifchannel 1 input clock source vp_clkin1 vp_clkin0 10 vsclkdis.vid1 000 110 100 101 vidclkctl.vch2clk vp_clkin2 gp[4]/stc_clkin vpifchannel 2 output clock source vp_clkin2 stc_clkin vp_clkin0 crg0_vcxi urxd2/crg1_vcxi/gp[39]/crg0_vcxi 11x 10x 010 sysclk8 (b) pll controller 1 vsclkdis.vid2 pinmux0.crgmux 001 crg1_vcxi vp_clkin0 urxd2/crg1_vcxi/gp[39]/crg0_vcxi dev_mxi/dev_clkin (27 mhz) ucts2/usd2/crg0_vcxi/gp[42]/ts1_ptso 011 auxclk 111 (a)
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 (a) for the -729 devices, use an external clock source for the 54-/74.25-/108-mhz vpif clock. figure 7-38. vpif display channel 3 source clock selection submit documentation feedback peripheral information and electrical specifications 225 000 110 100 101 vidclkctl.vch3clk vp_clkin2 gp[4]/stc_clkin vpifchannel 3 output clock source vp_clkin2 stc_clkin vp_clkin0 crg0_vcxi urxd2/crg1_vcxi/gp[39]/crg0_vcxi 11x 10x 011 auxclk pll controller 1 vsclkdis.vid3 pinmux0.crgmux 001 crg1_vcxi vp_clkin0 urxd2/crg1_vcxi/gp[39]/crg0_vcxi dev_mxi/dev_clkin (27 mhz) ucts2/usd2/crg0_vcxi/gp[42]/ts1_ptso 111 vp_clkin3/ts1_clko vp_clkin3 010 sysclk8 (a)
7.11.3 vpif register descriptions tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-46 shows the vpif registers. table 7-46. video port interface (vpif) registers hex address range acronym register name 0x01c1 2000 pid peripheral identification register 0x01c1 2004 ch0_ctrl channel 0 control register 0x01c1 2008 ch1_ctrl channel 1 control register 0x01c1 200c ch2_ctrl channel 2 control register 0x01c1 2010 ch3_ctrl channel 3 control register 0x01c1 2014 - 0x01c1 201f - reserved 0x01c1 2020 inten interrupt enable 0x01c1 2024 intenset interrupt enable set 0x01c1 2028 intenclr interrupt enable clear 0x01c1 202c intstat interrupt status 0x01c1 2030 intstatclr interrupt status clear 0x01c1 2034 emu_ctrl emulation control 0x01c1 2038 dma_size dma size control 0x01c1 203c - 0x01c1 203f - reserved capture channel 0 registers 0x01c1 2040 ch0_ty_strtadr channel 0 top field luma buffer start address 0x01c1 2044 ch0_by_strtadr channel 0 bottom field luma buffer start address 0x01c1 2048 ch0_tc_strtadr channel 0 top field chroma buffer start address 0x01c1 204c ch0_bc_strtadr channel 0 bottom field chroma buffer start address 0x01c1 2050 ch0_tha_strtadr channel 0 top field horizontal ancillary data buffer start address 0x01c1 2054 ch0_bha_strtadr channel 0 bottom field horizontal ancillary data buffer start address 0x01c1 2058 ch0_tva_strtadr channel 0 top field vertical ancillary data buffer start address 0x01c1 205c ch0_bva_strtadr channel 0 bottom field vertical ancillary data buffer start address 0x01c1 2060 ch0_subpic_cfg channel 0 sub-picture configuration 0x01c1 2064 ch0_img_add_ofst channel 0 image data address offset 0x01c1 2068 ch0_ha_add_ofst channel 0 horizontal ancillary data address offset 0x01c1 206c ch0_hsize_cfg channel 0 horizontal data size configuration 0x01c1 2070 ch0_vsize_cfg0 channel 0 vertical data size configuration (0) 0x01c1 2074 ch0_vsize_cfg1 channel 0 vertical data size configuration (1) 0x01c1 2078 ch0_vsize_cfg2 channel 0 vertical data size configuration (2) 0x01c1 207c ch0_vsize channel 0 vertical image size capture channel 1 registers 0x01c1 2080 ch1_ty_strtadr channel 1 top field luma buffer start address 0x01c1 2084 ch1_by_strtadr channel 1 bottom field luma buffer start address 0x01c1 2088 ch1_tc_strtadr channel 1 top field chroma buffer start address 0x01c1 208c ch1_bc_strtadr channel 1 bottom field chroma buffer start address 0x01c1 2090 ch1_tha_strtadr channel 1 top field horizontal ancillary data buffer start address 0x01c1 2094 ch1_bha_strtadr channel 1 bottom field horizontal ancillary data buffer start address 0x01c1 2098 ch1_tva_strtadr channel 1 top field vertical ancillary data buffer start address 0x01c1 209c ch1_bva_strtadr channel 1 bottom field vertical ancillary data buffer start address 0x01c1 20a0 ch1_subpic_cfg channel 1 sub-picture configuration 0x01c1 20a4 ch1_img_add_ofst channel 1 image data address offset 0x01c1 20a8 ch1_ha_add_ofst channel 1 horizontal ancillary data address offset 0x01c1 20ac ch1_hsize_cfg channel 1 horizontal data size configuration peripheral information and electrical specifications 226 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-46. video port interface (vpif) registers (continued) hex address range acronym register name 0x01c1 20b0 ch1_vsize_cfg0 channel 1 vertical data size configuration (0) 0x01c1 20b4 ch1_vsize_cfg1 channel 1 vertical data size configuration (1) 0x01c1 20b8 ch1_vsize_cfg2 channel 1 vertical data size configuration (2) 0x01c1 20bc ch1_vsize channel 1 vertical image size display channel 2 registers 0x01c1 20c0 ch2_ty_strtadr channel 2 top field luma buffer start address 0x01c1 20c4 ch2_by_strtadr channel 2 bottom field luma buffer start address 0x01c1 20c8 ch2_tc_strtadr channel 2 top field chroma buffer start address 0x01c1 20cc ch2_bc_strtadr channel 2 bottom field chroma buffer start address 0x01c1 20d0 ch2_tha_strtadr channel 2 top field horizontal ancillary data buffer start address 0x01c1 20d4 ch2_bha_strtadr channel 2 bottom field horizontal ancillary data buffer start address 0x01c1 20d8 ch2_tva_strtadr channel 2 top field vertical ancillary data buffer start address 0x01c1 20dc ch2_bva_strtadr channel 2 bottom field vertical ancillary data buffer start address 0x01c1 20e0 ch2_subpic_cfg channel 2 sub-picture configuration 0x01c1 20e4 ch2_img_add_ofst channel 2 image data address offset 0x01c1 20e8 ch2_ha_add_ofst channel 2 horizontal ancillary data address offset 0x01c1 20ec ch2_hsize_cfg channel 2 horizontal data size configuration 0x01c1 20f0 ch2_vsize_cfg0 channel 2 vertical data size configuration (0) 0x01c1 20f4 ch2_vsize_cfg1 channel 2 vertical data size configuration (1) 0x01c1 20f8 ch2_vsize_cfg2 channel 2 vertical data size configuration (2) 0x01c1 20fc ch2_vsize channel 2 vertical image size 0x01c1 2100 ch2_tha_strtpos channel 2 top field horizontal ancillary data insertion start position 0x01c1 2104 ch2_tha_size channel 2 top field horizontal ancillary data size 0x01c1 2108 ch2_bha_strtpos channel 2 bottom field horizontal ancillary data insertion start position 0x01c1 210c ch2_bha_size channel 2 bottom field horizontal ancillary data size 0x01c1 2110 ch2_tva_strtpos channel 2 top field vertical ancillary data insertion start position 0x01c1 2114 ch2_tva_size channel 2 top field vertical ancillary data size 0x01c1 2118 ch2_bva_strtpos channel 2 bottom field vertical ancillary data insertion start position 0x01c1 211c ch2_bva_size channel 2 bottom field vertical ancillary data size 0x01c1 2120 - 0x01c1 213f - reserved display channel 3 registers 0x01c1 2140 ch3_ty_strtadr channel 3 field 0 luma buffer start address 0x01c1 2144 ch3_by_strtadr channel 3 field 1 luma buffer start address 0x01c1 2148 ch3_tc_strtadr channel 3 field 0 chroma buffer start address 0x01c1 214c ch3_bc_strtadr channel 3 field 1 chroma buffer start address 0x01c1 2150 ch3_tha_strtadr channel 3 field 0 horizontal ancillary data buffer start address 0x01c1 2154 ch3_bha_strtadr channel 3 field 1 horizontal ancillary data buffer start address 0x01c1 2158 ch3_tva_strtadr channel 3 field 0 vertical ancillary data buffer start address 0x01c1 215c ch3_bva_strtadr channel 3 field 1 vertical ancillary data buffer start address 0x01c1 2160 ch3_subpic_cfg channel 3 sub-picture configuration 0x01c1 2164 ch3_img_add_ofst channel 3 image data address offset 0x01c1 2168 ch3_ha_add_ofst channel 3 horizontal ancillary data address offset 0x01c1 216c ch3_hsize_cfg channel 3 horizontal data size configuration 0x01c1 2170 ch3_vsize_cfg0 channel 3 vertical data size configuration (0) 0x01c1 2174 ch3_vsize_cfg1 channel 3 vertical data size configuration (1) 0x01c1 2178 ch3_vsize_cfg2 channel 3 vertical data size configuration (2) 0x01c1 217c ch3_vsize channel 3 vertical image size submit documentation feedback peripheral information and electrical specifications 227
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-46. video port interface (vpif) registers (continued) hex address range acronym register name 0x01c1 2180 ch3_tha_strtpos channel 3 top field horizontal ancillary data insertion start position 0x01c1 2184 ch3_tha_size channel 3 top field horizontal ancillary data size 0x01c1 2188 ch3_bha_strtpos channel 3 bottom field horizontal ancillary data insertion start position 0x01c1 218c ch3_bha_size channel 3 bottom field horizontal ancillary data size 0x01c1 2190 ch3_tva_strtpos channel 3 top field vertical ancillary data insertion start position 0x01c1 2194 ch3_tva_size channel 3 top field vertical ancillary data size 0x01c1 2198 ch3_bva_strtpos channel 3 bottom field vertical ancillary data insertion start position 0x01c1 219c ch3_bva_size channel 3 bottom field vertical ancillary data size 0x01c1 21a0 - 0x01c1 21ff - reserved peripheral information and electrical specifications 228 submit documentation feedback
7.11.4 vpif electrical data/timing tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-47. timing requirements for vpif vp_clkinx inputs (1) (see figure 7-39 ) -594 -729 no. unit min max min max 1 t c(vki) cycle time, vp_clkin0/1/2/3 10.1 9.25 ns 2 t w(vkih) pulse duration, vp_clkinx high 0.4c 0.4c ns 3 t w(vkil) pulse duration, vp_clkinx low 0.4c 0.4c ns 4 t t(vki) transition time, vp_clkinx 5 5 ns (1) c = vp_clkinx period in ns. figure 7-39. video port capture vp_clkinx timing submit documentation feedback peripheral information and electrical specifications 229 vp_clkinx 2 3 1 4 4
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-48. timing requirements for vpif channels 0/1 video capture data and control inputs (see figure 7-40 ) -594 -729 no. unit min max min max 1 t su(vdinv-vkih) setup time, vp_dinx valid before vp_clkin0/1 high 3.3 2.55 ns 2 t h(vkih-vdinv) hold time, vp_dinx valid after vp_clkin0/1 high 0 0 ns figure 7-40. vpif channels 0/1 video capture data and control input timing table 7-49. switching characteristics over recommended operating conditions for video data shown with respect to vp_clko2/3 (1) (see figure 7-41 ) -594 -729 no. parameter unit min max min max 1 t c(vko) cycle time, vp_clko2/3 10.1 9.25 ns 2 t w(vkoh) pulse duration, vp_clko2/3 high 0.4c 0.4c ns 3 t w(vkol) pulse duration, vp_clko2/3 low 0.4c 0.4c ns 4 t t(vko) transition time, vp_clko2/3 5 5 ns t d(vkoh- 11 delay time, vp_clko2/3 high to vp_doutx valid 6.8 6.5 ns vpdoutv) t d(vclkoh- 12 delay time, vp_clko2/3 high to vp_doutx invalid 1.5 1.5 ns vpdoutiv) (1) c = vp_clko2/3 period in ns. figure 7-41. vpif channels 2/3 video display data output timing with respect to vp_clko2/3 230 peripheral information and electrical specifications submit documentation feedback vp_clkox (positive edge clocking) vp_clkox (negative edge clocking) vp_doutx 1 3 2 11 12 4 4 vp_clkin0/1 vp_dinx/field/ hsync/vsync 1 2
7.12 transport stream interface (tsif) 7.12.1 tsif bus master tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the dm6467 device includes two independent transport stream interfaces (tsif0 and tsif1) with corresponding clock reference generator (crgen) modules for system time-clock recovery. the tsif peripheral supports the following features: 1-bit serial and 8-bit parallel independent receive and transmit interfaces with both synchronous and asynchronous modes. ( tsif1 supports serial mode only.) stream input/output (i/o) speed rate configurable by the i/o clock speed ats (absolute time stamp) detection, correction, and addition modes automatically detects pat and pmt and reflects assignment to the internal packet identification (pid) table (supported for partial transfer stream [ts] mode only; stream type and pid should be one-to-one mapping) pid filter with 7 pid filter tables and stream type assignments bypass mode implemented so that not only ts data, but any other data can be received or transmitted by the tsif module ring buffer control for both writes (8 channels) and reads (1 channel) to/from memory supports ?specific packet?, indicating boundary of plural program on ts supports full-ts in only one mode?semi-automatic-a mode, allowing communication to the c64x+ cpu. supports partial-ts in these modes?semi-automatic-b mode and full-automatic mode (provided stream type and pid are one-to-one mapping) for more detailed information on the crgen peripheral, see the tms320dm646x dmsoc clock reference generator user's guide (literature number sprueq1 ). the tsif peripherals each include a bus master interface that accesses the dm646x system bus to transfer stream receive and transmit data. table 7-50 shows the memory map for the tsif master interfaces. table 7-50. tsif0/1 master memory map size start address end address tsif0/1 access (bytes) 0x0000 0000 0x0fff ffff 256m reserved 0x1000 0000 0x1000 ffff 64k reserved 0x1001 0000 0x1001 3fff 16k arm ram 0 (data) 0x1001 4000 0x1001 7fff 16k arm ram 1 (data) 0x1001 8000 0x1001 ffff 32k arm rom (data) 0x1002 0000 0x10ff ffff 16256k reserved 0x1100 0000 0x41ff ffff 784m 0x4200 0000 0x43ff ffff 32m emifa data ( cs2) 0x4400 0000 0x45ff ffff 32m emifa data ( cs3) 0x4600 0000 0x47ff ffff 32m emifa data ( cs4) 0x4800 0000 0x49ff ffff 32m emifa data ( cs5) 0x4a00 0000 0x4bff ffff 32m reserved 0x4c00 0000 0x4fff ffff 64m vlynq (remote data) 0x5000 0000 0x7fff ffff 768m reserved 0x8000 0000 0x9fff ffff 512m ddr2 memory controller 0xa000 0000 0xbfff ffff 512m reserved 0xc000 0000 0xffff ffff 1g reserved submit documentation feedback peripheral information and electrical specifications 231
7.12.2 tsif clock control tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the source clocks for the tsif counters and output channels are selectable based on the settings of the tsifctl register (0x01c4 0050). (for more detailed information on the tsifctl register, see section 4.3.2.2 , tsif control.) the vsclkdis register (0x01c4 006c) is used to disable the clock inputs when changing the clock source to ensure glitch-free operation. (for more detailed informaiton on the vsclkdis register, see section 4.3.2.3 , video and tsif clock disable.) tsif0 outputs data synchronous to ts0_clko. the source clock for the ts0_clko output is selectable from among a number of external clock inputs or on-chip clock sources (see figure 7-42 ). figure 7-42. tsif0 output clock source selection the tsif0 system time counter may be clocked from a number of external clock inputs or on-chip clock sources (see figure 7-43 ). 232 peripheral information and electrical specifications submit documentation feedback 001 tsifctl.ptso_clk tsif0output clock source stc_clkin 011 sysclkbp pll controller 1 vsclkdis.tsiftx0 100 vp_clkin0 gp[4]/stc_clkin vp_clkin0 dev_mxi/dev_clkin (27 mhz) 000 crg0_vcxi urxd2/crg1_vcxi/gp[39]/crg0_vcxi 11x 10x pinmux0.crgmux ucts2/usd2/crg0_vcxi/gp[42]/ts1_ptso 110 101 ts0_clkin vp_clkin1 ts0_clkin vp_clkin1 111 urxd2/crg1_vcxi/gp[39]/crg0_vcxi crg1_vcxi 010 sysclk5
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 figure 7-43. tsif0 counter clock selection tsif1 outputs data synchronous to ts1_clko. the source clock for the ts1_clko output is selectable from among a number of external clock inputs or on-chip clock sources (see figure 7-44 ). figure 7-44. tsif1 output clock source selection the tsif1 system time counter may be clocked from a number of external clock inputs or on-chip clock sources (see figure 7-45 ). submit documentation feedback peripheral information and electrical specifications 233 10000101 0000 0100 tsifctl.tsso_clk ts1_clkin vp_clkin0 tsif1output clock source ts1_clkin vp_clkin0 crg1_vcxi crg0_vcxi urxd2/crg1_vcxi/gp[39]/crg0_vcxi 11x 10x 0011 sysclkbp pll controller 1 vsclkdis.tsiftx1 pinmux0.crgmux 0001 stc_clkin urxd2/crg1_vcxi/gp[39]/crg0_vcxi gp[4]/stc_clkin dev_mxi/dev_clkin (27 mhz) ucts2/usd2/crg0_vcxi/gp[42]/ts1_ptso 0110 vp_clkin2 vp_clkin2 0010 sysclk6 (a) 0111, 1001C1xx1 = reserved. 001 tsifctl.tsif0_cntclk tsif0counter clock stc_clkin 010 auxclk pll controller 1 vsclkdis.tsifcnt0 gp[4]/stc_clkin dev_mxi/dev_clkin (27 mhz) 000 crg0_vcxi urxd2/crg1_vcxi/gp[39]/crg0_vcxi 11x 10x pinmux0.crgmux ucts2/usd2/crg0_vcxi/gp[42]/ts1_ptso 100 011 vp_clkin0 vp_clkin0 crg1_vcxi 101 vp_clkin1 vp_clkin1 (a) 110, 111 = reserved. urxd2/crg1_vcxi/gp[39]/crg0_vcxi
7.12.3 tsif peripheral register description(s) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com figure 7-45. tsif1 counter clock selection the tsif0 and tsif1 registers are shown in table 7-51 and table 7-52 , respectively. table 7-51. tsif0 registers hex address range acronym register name 0x01c1 3000 pid tsif0 peripheral identification (pid) register 0x01c1 3004 ctrl0 control register 0 register 0x01c1 3008 ctrl1 control register 1 register 0x01c1 300c inten interrupt enable register 0x01c1 3010 inten_set interrupt enable set register 0x01c1 3014 inten_clr interrupt enable clear register 0x01c1 3018 intstat interrupt status register 0x01c1 301c intstat_clr interrupt status clear register 0x01c1 3020 emu_ctrl emulation control register 0x01c1 3024 async_tx_wait asynchronous transmit wait time register 0x01c1 3028 pat_sen_cfg program association table (pat) sense configuration register 0x01c1 302c pat_str_addr pat store address register 0x01c1 3030 pmt_sen_cfg program map table (pmt) sense configuration register 0x01c1 3034 pmt_str_addr pmt store address register 0x01c1 3038 bsp_in boundary sensing packet (bsp) in register 0x01c1 303c bsp_store_addr bsp in store address register 0x01c1 3040 pcr_sense_cfg program clock reference (pcr) sense configuration register 0x01c1 3044 pid0_filt_cfg packet identifier (pid) 0 (pid0) filter configuration register 0x01c1 3048 pid1_filt_cfg pid1 filter configuration register 0x01c1 304c pid2_filt_cfg pid2 filter configuration register 0x01c1 3050 pid3_filt_cfg pid3 filter configuration register 0x01c1 3054 pid4_filt_cfg pid4 filter configuration register peripheral information and electrical specifications 234 submit documentation feedback 001 tsifctl.tsif1_cntclk tsif1counter clock stc_clkin 010 auxclk pll controller 1 vsclkdis.tsifcnt1 gp[4]/stc_clkin dev_mxi/dev_clkin (27 mhz) 011 crg0_vcxi urxd2/crg1_vcxi/gp[39]/crg0_vcxi 11x 10x pinmux0.crgmux ucts2/usd2/crg0_vcxi/gp[42]/ts1_ptso 100 000 vp_clkin2 vp_clkin2 crg1_vcxi 101 vp_clkin3/ts1_clko vp_clkin3 (a) 110, 111 = reserved. urxd2/crg1_vcxi/gp[39]/crg0_vcxi
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-51. tsif0 registers (continued) hex address range acronym register name 0x01c1 3058 pid5_filt_cfg pid5 filter configuration register 0x01c1 305c pid6_filt_cfg pid6 filter configuration register 0x01c1 3060 bypass_cfg bypass mode configuration register 0x01c1 3064 tx_ats_init transmit arrival time stamp (ats) initialization register 0x01c1 3068 tx_ats_mon transmit ats monitor register 0x01c1 306c ? reserved 0x01c1 3070 rx_pkt_stat receive packet status register 0x01c1 3074 - 0x01c1 307f ? reserved 0x01c1 3080 stc_init_ctrl system time clock (stc) initialization control register 0x01c1 3084 stc_init_val stc initialization value register 0x01c1 3088 stc_int0 stc interrupt entry 0 register 0x01c1 308c stc_int1 stc interrupt entry 1 register 0x01c1 3090 stc_int2 stc interrupt entry 2 register 0x01c1 3094 stc_int3 stc interrupt entry 3 register 0x01c1 3098 stc_int4 stc interrupt entry 4 register 0x01c1 309c stc_int5 stc interrupt entry 5 register 0x01c1 30a0 stc_int6 stc interrupt entry 6 register 0x01c1 30a4 stc_int7 stc interrupt entry 7 register 0x01c1 30a8 - 0x01c1 30bf ? reserved 0x01c1 30c0 wrb_ctrl write ring buffer channel control register 0x01c1 30c4 wrb0_strt_addr write ring buffer channel 0 start address register 0x01c1 30c8 wrb0_end_addr write ring buffer channel 0 end address register 0x01c1 30cc wrb0_rdptr write ring buffer channel 0 read pointer register 0x01c1 30d0 wrb0_sub write ring buffer channel 0 subtraction register 0x01c1 30d4 wrb0_wrptr write ring buffer channel 0 write pointer register 0x01c1 30d8 - 0x01c1 30df ? reserved 0x01c1 30e0 wrb1_strt_addr write ring buffer channel 1 start address register 0x01c1 30e4 wrb1_end_addr write ring buffer channel 1 end address register 0x01c1 30e8 wrb1_rdptr write ring buffer channel 1 read pointer register 0x01c1 30ec wrb1_sub write ring buffer channel 1 subtraction register 0x01c1 30f0 wrb1_wrptr write ring buffer channel 1 write pointer register 0x01c1 30f4 - 0x01c1 30ff ? reserved 0x01c1 3100 wrb2_strt_addr write ring buffer channel 2 start address register 0x01c1 3104 wrb2_end_addr write ring buffer channel 2 end address register 0x01c1 3108 wrb2_rdptr write ring buffer channel 2 read pointer register 0x01c1 310c wrb2_sub write ring buffer channel 2 subtraction register 0x01c1 3110 wrb2_wrptr write ring buffer channel 2 write pointer register 0x01c1 3114 - 0x01c1 311f ? reserved 0x01c1 3120 wrb3_strt_addr write ring buffer channel 3 start address register 0x01c1 3124 wrb3_end_addr write ring buffer channel 3 end address register 0x01c1 3128 wrb3_rdptr write ring buffer channel 3 read pointer register 0x01c1 312c wrb3_sub write ring buffer channel 3 subtraction register 0x01c1 3130 wrb3_wrptr write ring buffer channel 3 write pointer register 0x01c1 3134 - 0x01c1 313f ? reserved 0x01c1 3140 wrb4_strt_addr write ring buffer channel 4 start address register 0x01c1 3144 wrb4_end_addr write ring buffer channel 4 end address register 0x01c1 3148 wrb4_rdptr write ring buffer channel 4 read pointer register submit documentation feedback peripheral information and electrical specifications 235
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-51. tsif0 registers (continued) hex address range acronym register name 0x01c1 314c wrb4_sub write ring buffer channel 4 subtraction register 0x01c1 3150 wrb4_wrptr write ring buffer channel 4 write pointer register 0x01c1 3154 - 0x01c1 315f ? reserved 0x01c1 3160 wrb5_strt_addr write ring buffer channel 5 start address register 0x01c1 3164 wrb5_end_addr write ring buffer channel 5 end address register 0x01c1 3168 wrb5_rdptr write ring buffer channel 5 read pointer register 0x01c1 316c wrb5_sub write ring buffer channel 5 subtraction register 0x01c1 3170 wrb5_wrptr write ring buffer channel 5 write pointer register 0x01c1 3174 - 0x01c1 317f ? reserved 0x01c1 3180 wrb6_strt_addr write ring buffer channel 6 start address register 0x01c1 3184 wrb6_end_addr write ring buffer channel 6 end address register 0x01c1 3188 wrb6_rdptr write ring buffer channel 6 read pointer register 0x01c1 318c wrb6_sub write ring buffer channel 6 subtraction register 0x01c1 3190 wrb6_wrptr write ring buffer channel 6 write pointer register 0x01c1 3194 - 0x01c1 319f ? reserved 0x01c1 31a0 wrb7_strt_addr write ring buffer channel 7 start address register 0x01c1 31a4 wrb7_end_addr write ring buffer channel 7 end address register 0x01c1 31a8 wrb7_rdptr write ring buffer channel 7 read pointer register 0x01c1 31ac wrb7_sub write ring buffer channel 7 subtraction register 0x01c1 31b0 wrb7_wrptr write ring buffer channel 7 write pointer register 0x01c1 31b4 - 0x01c1 31bf ? reserved 0x01c1 31c0 rrb_ctrl read ring buffer channel control register 0x01c1 31c4 rrb_strt_addr read ring buffer channel start address register 0x01c1 31c8 rrb_end_addr read ring buffer channel end address register 0x01c1 31cc rrb_wrptr read ring buffer channel write pointer register 0x01c1 31d0 rrb_sub read ring buffer channel subtraction register 0x01c1 31d4 rrb_rdptr read ring buffer channel read pointer register 0x01c1 31d8 pkt_cnt packet counter value register 0x01c1 31dc - 0x01c1 31ff ? reserved table 7-52. tsif1 registers hex address range acronym register name 0x01c1 3400 pid tsif1 peripheral identification (pid) register 0x01c1 3404 ctrl0 control register 0 register 0x01c1 3408 ctrl1 control register 1 register 0x01c1 340c inten interrupt enable register 0x01c1 3410 inten_set interrupt enable set register 0x01c1 3414 inten_clr interrupt enable clear register 0x01c1 3418 intstat interrupt status register 0x01c1 341c intstat_clr interrupt status clear register 0x01c1 3420 emu_ctrl emulation control register 0x01c1 3424 async_tx_wait asynchronous transmit wait time register 0x01c1 3428 pat_sen_cfg program association table (pat) sense configuration register 0x01c1 342c pat_str_addr pat store address register 0x01c1 3430 pmt_sen_cfg program map table (pmt) sense configuration register 0x01c1 3434 pmt_str_addr pmt store address register peripheral information and electrical specifications 236 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-52. tsif1 registers (continued) hex address range acronym register name 0x01c1 3438 bsp_in boundary sensing packet (bsp) in register 0x01c1 343c bsp_store_addr bsp in store address register 0x01c1 3440 pcr_sense_cfg program clock reference (pcr) sense configuration register 0x01c1 3444 pid0_filt_cfg packet identifier (pid) 0 (pid0) filter configuration register 0x01c1 3448 pid1_filt_cfg pid1 filter configuration register 0x01c1 344c pid2_filt_cfg pid2 filter configuration register 0x01c1 3450 pid3_filt_cfg pid3 filter configuration register 0x01c1 3454 pid4_filt_cfg pid4 filter configuration register 0x01c1 3458 pid5_filt_cfg pid5 filter configuration register 0x01c1 345c pid6_filt_cfg pid6 filter configuration register 0x01c1 3460 bypass_cfg bypass mode configuration register 0x01c1 3064 tx_ats_init transmit arrival time stamp (ats) initialization register 0x01c1 3468 tx_ats_mon transmit ats monitor register 0x01c1 346c ? reserved 0x01c1 3470 rx_pkt_stat receive packet status register 0x01c1 3474 - 0x01c1 347f ? reserved 0x01c1 3480 stc_init_ctrl system time clock (stc) initialization control register 0x01c1 3484 stc_init_val stc initialization value register 0x01c1 3488 stc_int0 stc interrupt entry 0 register 0x01c1 348c stc_int1 stc interrupt entry 1 register 0x01c1 3490 stc_int2 stc interrupt entry 2 register 0x01c1 3494 stc_int3 stc interrupt entry 3 register 0x01c1 3498 stc_int4 stc interrupt entry 4 register 0x01c1 349c stc_int5 stc interrupt entry 5 register 0x01c1 34a0 stc_int6 stc interrupt entry 6 register 0x01c1 34a4 stc_int7 stc interrupt entry 7 register 0x01c1 34a8 - 0x01c1 34bf ? reserved 0x01c1 34c0 wrb_ctrl write ring buffer channel control register 0x01c1 34c4 wrb0_strt_addr write ring buffer channel 0 start address register 0x01c1 34c8 wrb0_end_addr write ring buffer channel 0 end address register 0x01c1 34cc wrb0_rdptr write ring buffer channel 0 read pointer register 0x01c1 34d0 wrb0_sub write ring buffer channel 0 subtraction register 0x01c1 34d4 wrb0_wrptr write ring buffer channel 0 write pointer register 0x01c1 34d8 - 0x01c1 34df ? reserved 0x01c1 34e0 wrb1_strt_addr write ring buffer channel 1 start address register 0x01c1 34e4 wrb1_end_addr write ring buffer channel 1 end address register 0x01c1 34e8 wrb1_rdptr write ring buffer channel 1 read pointer register 0x01c1 34ec wrb1_sub write ring buffer channel 1 subtraction register 0x01c1 34f0 wrb1_wrptr write ring buffer channel 1 write pointer register 0x01c1 34f4 - 0x01c1 34ff ? reserved 0x01c1 3500 wrb2_strt_addr write ring buffer channel 2 start address register 0x01c1 3504 wrb2_end_addr write ring buffer channel 2 end address register 0x01c1 3508 wrb2_rdptr write ring buffer channel 2 read pointer register 0x01c1 350c wrb2_sub write ring buffer channel 2 subtraction register 0x01c1 3510 wrb2_wrptr write ring buffer channel 2 write pointer register 0x01c1 3514 - 0x01c1 351f ? reserved 0x01c1 3520 wrb3_strt_addr write ring buffer channel 3 start address register submit documentation feedback peripheral information and electrical specifications 237
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-52. tsif1 registers (continued) hex address range acronym register name 0x01c1 3524 wrb3_end_addr write ring buffer channel 3 end address register 0x01c1 3528 wrb3_rdptr write ring buffer channel 3 read pointer register 0x01c1 352c wrb3_sub write ring buffer channel 3 subtraction register 0x01c1 3530 wrb3_wrptr write ring buffer channel 3 write pointer register 0x01c1 3534 - 0x01c1 353f ? reserved 0x01c1 3540 wrb4_strt_addr write ring buffer channel 4 start address register 0x01c1 3544 wrb4_end_addr write ring buffer channel 4 end address register 0x01c1 3548 wrb4_rdptr write ring buffer channel 4 read pointer register 0x01c1 354c wrb4_sub write ring buffer channel 4 subtraction register 0x01c1 3550 wrb4_wrptr write ring buffer channel 4 write pointer register 0x01c1 3554 - 0x01c1 355f ? reserved 0x01c1 3560 wrb5_strt_addr write ring buffer channel 5 start address register 0x01c1 3564 wrb5_end_addr write ring buffer channel 5 end address register 0x01c1 3568 wrb5_rdptr write ring buffer channel 5 read pointer register 0x01c1 356c wrb5_sub write ring buffer channel 5 subtraction register 0x01c1 3570 wrb5_wrptr write ring buffer channel 5 write pointer register 0x01c1 3574 - 0x01c1 357f ? reserved 0x01c1 3580 wrb6_strt_addr write ring buffer channel 6 start address register 0x01c1 3584 wrb6_end_addr write ring buffer channel 6 end address register 0x01c1 3588 wrb6_rdptr write ring buffer channel 6 read pointer register 0x01c1 358c wrb6_sub write ring buffer channel 6 subtraction register 0x01c1 3590 wrb6_wrptr write ring buffer channel 6 write pointer register 0x01c1 3594 - 0x01c1 359f ? reserved 0x01c1 35a0 wrb7_strt_addr write ring buffer channel 7 start address register 0x01c1 35a4 wrb7_end_addr write ring buffer channel 7 end address register 0x01c1 35a8 wrb7_rdptr write ring buffer channel 7 read pointer register 0x01c1 35ac wrb7_sub write ring buffer channel 7 subtraction register 0x01c1 35b0 wrb7_wrptr write ring buffer channel 7 write pointer register 0x01c1 35b4 - 0x01c1 35bf ? reserved 0x01c1 35c0 rrb_ctrl read ring buffer channel control register 0x01c1 35c4 rrb_strt_addr read ring buffer channel start address register 0x01c1 35c8 rrb_end_addr read ring buffer channel end address register 0x01c1 35cc rrb_wrptr read ring buffer channel write pointer register 0x01c1 35d0 rrb_sub read ring buffer channel subtraction register 0x01c1 35d4 rrb_rdptr read ring buffer channel read pointer register 0x01c1 35d8 pkt_cnt packet counter value register 0x01c1 35dc - 0x01c1 35ff ? reserved peripheral information and electrical specifications 238 submit documentation feedback
7.12.4 transport stream interface (tsif) electrical data/timing tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-53. timing requirements for tsif input (see figure 7-46 ) -594, -729 serial parallel no. unit input input (1) min max min max 1 t c(tsclkin) cycle time, tsx_clkin 10 16.7 ns 2 t w(tsclkin) pulse duration, tsx_clkin high/low (2) 0.4c 0.4c ns 3 t t(tsclkin) transition time, tsx_clkin 3 (3) 3 (3) ns all others 4 4 ns setup time, tsx_ctl/tsx_data (4) input valid 4 t su(tsdatain-tsclkinv) tsx_wait before tsx_clkin edge 13 13 ns in hold time, tsx_ctl/tsx_data (4) input valid after 5 t h(tsclkinv-tsdatain) 0 0 ns tsx_clkin edge (1) tsif1 supports serial input mode only. (2) c = tsx_clkin period (cycle time) in ns. (3) for a 4-inch transmission line with 4-pf load capacitance at the device pin. (4) tsx_ctl/tsx_data input includes: ts0_en_waito, ts0_waitin, ts0_pstin, and ts0_din[7:0] for a parallel input. for a serial input, tsx_ctl/tsx_data input includes: tsx_en_waito, tsx_waitin, tsx_pstin, and ts0_din7 or ts1_din. a. tsx_ctl/tsx_data input includes: ts0_en_waito, ts0_waitin, ts0_pstin, and ts0_din[7:0] for a parallel input. for a serial input, tsx_ctl/tsx_data input includes: tsx_en_waito, tsx_waitin, tsx_pstin, and ts0_din7 or ts1_din. figure 7-46. tsif input timing table 7-54. switching characteristics over recommended operating conditions for tsif output (see figure 7-47 ) -594, -729 serial parallel no. unit output output (1) min max min max 6 t c(tsclko) cycle time, tsx_clko 10 16.7 ns 7 t w(tsclko) pulse duration, tsx_clko high/low (2) 0.4c 0.4c ns 8 t t(tsclko) transition time, tsx_clko 3 (3) 3 (3) ns (1) tsif1 supports serial output mode only. (2) c = tsx_clko period (cycle time) in ns. (3) for a 4-inch transmission line with 4-pf load capacitance at the device pin. submit documentation feedback peripheral information and electrical specifications 239 1 4 5 tsx_clkin (positive edge clocking) tsx_ctl/ tsx_data (a) 3 3 tsx_clkin (negative edge clocking) 2 2
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-54. switching characteristics over recommended operating conditions for tsif output (see figure 7-47 ) (continued) -594, -729 serial parallel no. unit output output (1) min max min max all others 1 7.5 1 7.5 ns delay time, tsx_clko edge to 9 t d(tsclkov-tsdatao) ts0_waito, tsx_ctl/tsx_data (4) output valid 1 16.5 1 16.5 ns tsx_en_waito (4) tsx_ctl/tsx_data output includes: ts0_enao, ts0_waito, ts0_psto, and ts0_dout[7:0] for a parallel output. for a serial output, tsx_ctl/tsx_data output includes: tsx_enao, tsx_en_waito, tsx_psto, and ts0_dout7 or ts1_dout. a. tsx_ctl/tsx_data output includes: ts0_enao, ts0_waito, ts0_psto, and ts0_dout[7:0] for a parallel output. for a serial output, tsx_ctl/tsx_data output includes: tsx_enao, tsx_en_waito, tsx_psto, and ts0_dout7 or ts1_dout. figure 7-47. tsif output timing 240 peripheral information and electrical specifications submit documentation feedback 9 tsx_clko (positive edge clocking) tsx_ctl/ tsx_data (a) tsx_clko (negative edge clocking) 9 7 7 6 8 8
7.13 clock recovery generator (crgen) 7.13.1 crgen peripheral register description(s) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 each tsif module has an associated crgen module which can adjust the local system time clock based upon the received program clock reference (pcr) packets. crgen0 may only be used with tsif 0 and crgen 1 may only be used with tsif 1. each crgen module features: automatic load of received pcr packet values from associated tsif module local system time clock (stc) counter pcr/stc difference generator (subtractor) loop filter (lpf) 1-bit sigma/delta modulator digital-to-analog converter (dac) output for external vcxo control the crgen0 and crgen1 registers are shown in table 7-55 and table 7-56 , respectively. table 7-55. crgen0 registers hex address range acronym register name 0x01c2 6000 pid crgen peripheral identification register 0x01c2 6004 control crgen control register 0x01c2 6008 stc_hi system time clock (stc) current value (upper 17 bits) 0x01c2 600c stc_lo stc current value (lower 16 bits plus extension) 0x01c2 6010 stc_val_hi stc value (upper 17 bits) on tsif0 pcr packet detection stc value (lower 16 bits plus extension) on tsif0 pcr packet 0x01c2 6014 stc_val_lo detection program clock reference (pcr) value (upper 17 bits) from 0x01c2 6018 pcr_hi tsif0 receive packet pcr value (lower 16 bits plus extension) from tsif0 receive 0x01c2 601c pcr_lo packet 0x01c2 6020 pcr_pkt_stat pcr packet status 0x01c2 6024 loop_filter loop filter (lpf) interface offset value of the stc counter for the higher (upper) 17 bits. 0x01c2 6028 stc_offset_hi this value is detected in the stc counter with the first pcr loading pulse signal. offset value of the stc counter for the lower 16 bits. the role 0x01c2 602c stc_offset_lo of this register is same as the stc_lo register 0x01c2 600c. 0x01c2 6030 - 0x01c2 603f - reserved 0x01c2 6040 inten interrupt enable 0x01c2 6044 inten_set interrupt enable set 0x01c2 6048 inten_clr interrupt enable clear 0x01c2 604c intstat interrupt status 0x01c2 6050 intstat_clr interrupt status clear 0x01c2 6054 emu_ctrl emulation control 0x01c2 6058 - 0x01c2 607f - reserved submit documentation feedback peripheral information and electrical specifications 241
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-56. crgen1 registers hex address range acronym register name 0x01c2 6400 pid crgen peripheral identification register 0x01c2 6404 control crgen control register 0x01c2 6408 stc_hi system time clock (stc) current value (upper 17 bits) 0x01c2 640c stc_lo stc current value (lower 16 bits plus extension) 0x01c2 6410 stc_val_hi stc value (upper 17 bits) on tsif1 pcr packet detection stc value (lower 16 bits plus extension) on tsif1 pcr packet 0x01c2 6414 stc_val_lo detection program clock reference (pcr) value (upper 17 bits) from 0x01c2 6418 pcr_hi tsif1 receive packet pcr value (lower 16 bits plus extension) from tsif1 receive 0x01c2 641c pcr_lo packet 0x01c2 6420 pcr_pkt_stat pcr packet status 0x01c2 6424 loop_filter loop filter (lpf) interface offset value of the stc counter for the higher 17 bits. this 0x01c2 6428 stc_offset_hi value is detected in the stc counter with the first pcr loading pulse signal. offset value of the stc counter for the lower 16 bits. the role 0x01c2 642c stc_offset_lo of this register is same as the stc_lo register 0x01c2 640c. 0x01c2 6430 - 0x01c2 643f - reserved 0x01c2 6440 inten interrupt enable 0x01c2 6444 inten_set interrupt enable set 0x01c2 6448 inten_clr interrupt enable clear 0x01c2 644c intstat interrupt status 0x01c2 6450 intstat_clr interrupt status clear 0x01c2 6454 emu_ctrl emulation control 0x01c2 6458 - 0x01c2 647f - reserved peripheral information and electrical specifications 242 submit documentation feedback
7.13.2 crgen electrical data/timing tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-57. timing requirements for crgx_vcxi input (see figure 7-48 ) -594, -729 no. unit min nom max 1 t c(vcxi) cycle time, crgx_vcxi 29.63 37. 037 44.44 ns 2 t w(vcxih) pulse duration, crgx_vcxi high 0.4p ns 3 t w(vcxil) pulse duration, crgx_vcxi low 0.4p ns 4 t t(vcxi) transition time, crgx_vcxi 5 ns figure 7-48. crgx_vcxi input timing table 7-58. switching characteristics over recommended operating conditions for crgx_po output (see figure 7-49 ) -594, -729 no. parameter unit min max 1 t w(poh) pulse duration, crgx_po high 59.26 ns 2 t w(pol) pulse duration, crgx_po low 59.26 ns 3 t t(po) transition time, crgx_po 5 ns figure 7-49. crgx_po output timing submit documentation feedback peripheral information and electrical specifications 243 crgx_vcxi 2 3 1 4 4 crgx_po 1 3 3 2
7.14 video data conversion engine (vdce) 7.14.1 vdce bus master tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the dm6467 video data conversion engine (vdce) supports the following features: resize function on horizontal (hrsz) and vertical (vrsz) with ratio defined by 256/n (n is a natural number that ranges from 256 to 2048) with 4 taps interpolation. magnification ratio of horizontal resize and vertical resize can be configured separately (different value can be configured). anti-alias filter (combination of two kinds of low-pass filter) with horizontal 7 taps, and vertical direction. chrominance signal format conversion (ccv) on both directions, one is from 4:2:2 to 4:2:0 and one is from 4:2:0 to 4:2:2. this function also uses 4 taps interpolation. mpeg-1 specific format (half-pixel phased from even pixel position of luminance) is also supported. edge padding for preparation of mc with unrestricted motion vector (required by mpeg-4, h.264, vc-1). all modes (progressive, interlace frame, and interlace field) are supported (macro-block level control that is required in h.264 is not currently supported). vc-1 range mapping in advanced profile (in case of displaying decoded reference image or trans-coding from vc-1 to any other format of video codec). 2-bit hardware menu overlay with 256 steps of blending for each color. the vdce includes a bus master interface that accesses the dm646x system bus to transfer data. table 7-59 shows the memory map for the vdce interface. table 7-59. vdce master memory map size start address end address vdce access (bytes) 0x0000 0000 0x0fff ffff 256m reserved 0x1000 0000 0x1000 ffff 64k reserved 0x1001 0000 0x1001 3fff 16k arm ram 0 (data) 0x1001 4000 0x1001 7fff 16k arm ram 1 (data) 0x1001 8000 0x1001 ffff 32k arm rom (data) 0x1002 0000 0x10ff ffff 16256k reserved 0x1100 0000 0x41ff ffff 784m 0x4200 0000 0x43ff ffff 32m emifa data ( cs2) 0x4400 0000 0x45ff ffff 32m emifa data ( cs3) 0x4600 0000 0x47ff ffff 32m emifa data ( cs4) 0x4800 0000 0x49ff ffff 32m emifa data ( cs5) 0x4a00 0000 0x4bff ffff 32m reserved 0x4c00 0000 0x4fff ffff 64m vlynq (remote data) 0x5000 0000 0x7fff ffff 768m reserved 0x8000 0000 0x9fff ffff 512m ddr2 memory controller 0xa000 0000 0xbfff ffff 512m reserved 0xc000 0000 0xffff ffff 1g reserved peripheral information and electrical specifications 244 submit documentation feedback
7.14.2 vdce register description(s) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-60 shows the vdce registers. table 7-60. vdce registers hex address range acronym register name 0x01c1 2800 pid vdce peripheral identification register 0x01c1 2804 ctrl vdce control register 0x01c1 2808 inten interrupt enable register 0x01c1 280c inten_set interrupt enable set register 0x01c1 2810 inten_clr interrupt enable clear register 0x01c1 2814 intstat interrupt status register 0x01c1 2818 intstat_clr interrupt status clear register 0x01c1 281c emu_ctrl emulation control register 0x01c1 2820 srd_frmt source/result data store format register 0x01c1 2824 req_size request unit size register 0x01c1 2828 proc_size processing unit size register 0x01c1 282c - 0x01c1 283f ? reserved 0x01c1 2840 ty_srcaddr luma top field source start address register 0x01c1 2844 ty_srcspsize luma top field source sub-picture size register 0x01c1 2848 ty_srcoffset luma top field line source address offset size register 0x01c1 284c by_srcaddr luma bottom field source start address register 0x01c1 2850 by_srcspsize luma bottom field source sub-picture size register 0x01c1 2854 by_srcoffset luma bottom field line source address offset size register 0x01c1 2858 tc_srcaddr chroma top field source start address register 0x01c1 285c tc_srcspsize chroma top field source sub-picture size register 0x01c1 2860 tc_srcoffset chroma top field line source address offset size register 0x01c1 2864 bc_srcaddr chroma bottom field source start address register 0x01c1 2868 bc_srcspsize chroma bottom field source sub-picture size register 0x01c1 286c bc_srcoffset chroma bottom field line source address offset size register 0x01c1 2870 tbmp_srcaddr bitmap top field source start address register 0x01c1 2874 tbmp_srcoffset bitmap top field line source address offset register 0x01c1 2878 bbmp_srcaddr bitmap bottom field source start address register 0x01c1 287c bbmp_srcoffset bitmap bottom field line source address offset register 0x01c1 2880 ty_resaddr luma top field result start address register 0x01c1 2884 ty_resspsize luma top field result sub-picture size register 0x01c1 2888 ty_resoffset luma top field line result address offset size register 0x01c1 288c by_resaddr luma bottom field result start address register 0x01c1 2890 by_resspsize luma bottom field result sub-picture size register 0x01c1 2894 by_resoffset luma bottom field line result address offset size register 0x01c1 2898 tc_resaddr chroma top field result start address register 0x01c1 289c tc_resspsize chroma top field result sub-picture size register 0x01c1 28a0 tc_resoffset chroma top field result line address offset size register 0x01c1 28a4 bc_resaddr chroma bottom field result start address register 0x01c1 28a8 bc_resspsize chroma bottom field result sub-picture size register 0x01c1 28ac bc_resoffset chroma bottom field line result address offset size register 0x01c1 28b0 - 0x01c1 28bf ? reserved 0x01c1 28c0 img_y_srcstrtpos luminance source image start position register 0x01c1 28c4 img_y_srcsize luminance source image size register 0x01c1 28c8 img_c_srcstrtpos chrominance source image start position register submit documentation feedback peripheral information and electrical specifications 245
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-60. vdce registers (continued) hex address range acronym register name 0x01c1 28cc img_c_srcsize chrominance source image size register 0x01c1 28d0 img_bmp_srcstrtpos bitmap source image start position register 0x01c1 28d4 img_bmp_srcsize bitmap source image size register 0x01c1 28d8 - 0x01c1 28df ? reserved 0x01c1 28e0 img_y_resstrtpos luminance result image start position register 0x01c1 28e4 img_y_ressize luminance result image size register 0x01c1 28e8 img_c_resstrtpos chrominance result image start position register 0x01c1 28ec img_c_ressize chrominance result image size register 0x01c1 28f0 img_bmp_resstrtpos bitmap result image start position (location) register 0x01c1 28f4 - 0x01c1 28ff ? reserved 0x01c1 2900 rsz_mode resize mode definition register 0x01c1 2904 rsz_hmag horizontal resize magnification ratio control register 0x01c1 2908 rsz_vmag vertical resize magnification ratio control register 0x01c1 290c rsz_hphase phase of initial pixel on horizontal resize register 0x01c1 2910 rsz_vphase phase of initial pixel on vertical resize register 0x01c1 2914 rsz_afilter horizontal anti-aliasing (flicker) filter control register 0x01c1 2918 - 0x01c1 291f ? reserved 0x01c1 2920 ccv_mode chrominance conversion mode control register 0x01c1 2924 - 0x01c1 293f ? reserved 0x01c1 2940 bld_lut_00 look-up table for index 00 register 0x01c1 2944 bld_lut_01 look-up table for index 01 register 0x01c1 2948 bld_lut_02 look-up table for index 02 register 0x01c1 294c bld_lut_03 look-up table for index 03 register 0x01c1 2950 - 0x01c1 295f ? reserved 0x01c1 2960 rgmp_ctrl ramp mapping control reigster 0x01c1 2964 - 0x01c1 2983 ? reserved 0x01c1 2984 epd_luma_width edge padding width for luminance register 0x01c1 2988 epd_chroma_width edge padding width for chrominance register 0x01c1 298c - 0x01c1 291f ? reserved peripheral information and electrical specifications 246 submit documentation feedback
7.15 peripheral component interconnect (pci) 7.15.1 pci device-specific information tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the dm6467 dmsoc supports connections to pci-compliant devices via the integrated pci master/slave bus interface. the pci port interfaces to dsp internal resources via the data switched central resource. the data switched central resource is described in more detail in section 5 , system interconnect. for more detailed information on the pci port peripheral module, see the tms320dm643x dmp peripheral component interconnect (pci) user's guide (literature number spru985). the pci peripheral on the dm6467 dmsoc conforms to the pci local bus specification revision 2.3. the pci peripheral can act both as a pci bus master and as a target. it supports pci bus operation of speeds up to 33 mhz and uses a 32-bit data/address bus. on the dm6467 device, the pins of the pci peripheral are multiplexed with the pins of the emifa, gpio, hpi, and ata peripherals. for more detailed information on how to select pci, see section 4 , device configurations. the dm6467 device provides an initialization mechanism through which the default values for some of the pci configuration registers can be read from an i2c eeprom. table 7-61 shows the registers which can be initialized through the pci auto-initialization. the default value of these registers when pci auto-initialization is not used. pci auto-initialization is enabled by selecting pci boot with auto-initialization. for information on how to select pci boot with auto-initialization, see section 4.4.1 , boot modes. for more information on pci auto-initialization, see the tms320dm646x dmsoc peripheral component interconnect (pci) user's guide (literature number spruer2 ) and the using the tmis320dm646x bootloader application report (literature number spraas0 ). the pci peripheral is a master peripheral within the dm6467 dmsoc. table 7-61. default values for pci configuration registers register default value (hex) 0x01c1 a000?vendor id/device id register (pcivendev) b002 104ch device id b002h vendor id 104ch 0x01c1 a008?class code/revision id register (pciclrev) 1180 0001h class code 80h revision id 01h 0x01c1 a02c?system vendor id/subsystem id (pcisubid) 0000 0000h subsystem id 0000 system vendor id 0000 0x01c1 a03c?max latency/min grant/interrupt pin/interrupt line 0000 0100h max latency 00 min grant 00 interrupt pin 01 interrupt line 00 the on-chip bootloader supports a host boot which allows an external pci device to load application code into the dmsoc's memory space. submit documentation feedback peripheral information and electrical specifications 247
7.15.2 pci external master memory map tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the pci port includes a local dma interface that allows external pci master device intiated transfers to access the dm646x system bus. table 7-62 shows the memory map for the pci interface. table 7-62. pci dma master memory map size start address end address pci dma access (bytes) 0x0000 0000 0x01bf ffff 28m reserved 0x01c0 0000 0x0fff ffff 228m cfg bus peripherals 0x1001 0000 0x1001 3fff 16k arm ram 0 (data) 0x1001 4000 0x1001 7fff 16k arm ram 1 (data) 0x1001 8000 0x1001 ffff 32k arm rom (data) 0x1002 0000 0x10ff ffff 16256k 0x1100 0000 0x113f ffff 4m 0x1140 0000 0x114f ffff 1m 0x1150 0000 0x115f ffff 1m reserved 0x1160 0000 0x116f ffff 1m 0x1170 0000 0x117f ffff 1m 0x1180 0000 0x1180 ffff 64k 0x1181 0000 0x1181 7fff 32k 0x1181 8000 0x1183 7fff 128k c64x+ l2 ram/cache 0x1183 8000 0x118f ffff 800k reserved 0x1190 0000 0x11df ffff 5m 0x11e0 0000 0x11e0 7fff 32k c64x+ l1p ram/cache 0x11e0 8000 0x11ef ffff 992k reserved 0x11f0 0000 0x11f0 7fff 32k c64x+ l1d ram/cache 0x11f0 8000 0x11ff ffff 992k reserved 0x1200 0000 0x4bff ffff 928m 0x4c00 0000 0x4fff ffff 64m vlynq (remote data) 0x5000 0000 0x7fff ffff 768m reserved 0x8000 0000 0x9fff ffff 512m ddr2 memory controller 0xa000 0000 0xbfff ffff 512m reserved 0xc000 0000 0xffff ffff 1g reserved peripheral information and electrical specifications 248 submit documentation feedback
7.15.3 pci peripheral register description(s) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-63. pci configuration registers pci host access acronym pci host access register name hex address range 0x01c1 a000 pcivendev vendor id/device id 0x01c1 a004 pcicsr command/status 0x01c1 a008 pciclrev class code/revision id 0x01c1 a00c pcicline bist/header type/latency timer/cacheline size 0x01c1 a010 pcibar0 base address 0 0x01c1 a014 pcibar1 base address 1 0x01c1 a018 pcibar2 base address 2 0x01c1 a01c pcibar3 base address 3 0x01c1 a020 pcibar4 base address 4 0x01c1 a024 pcibar5 base address 5 0x01c1 a028 - 0x01c1 a02b ? reserved 0x01c1 a02c pcisubid subsystem vendor id/subsystem id 0x01c1 a030 ? reserved 0x01c1 a034 pcicpbptr capabilities pointer 0x01c1 a038 - 0x01c1 a03b - reserved 0x01c1 a03c pcilgint max latency/min grant/interrupt pin/interrupt line 0x01c1 a040 - 0x01c1 a07f ? reserved 0x01c1 a080 - 0x01c1 a7ff ? reserved submit documentation feedback peripheral information and electrical specifications 249
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-64. pci back end configuration registers dmsoc access acronym dmsoc access register name hex address range 01c1 a000 - 01c1 a00f - reserved 01c1 a010 pcistatset pci status set register 01c1 a014 pcistatclr pci status clear register 01c1 a018 - 01c1 a01f - reserved 01c1 a020 pcihintset pci host interrupt enable set register 01c1 a024 pcihintclr pci host interrupt enable clear register 01c1 a028 - 01c1 a02f - reserved 01c1 a030 pcibintset pci back end application interrupt enable set register 01c1 a034 pcibintclr pci back end application interrupt enable clear register 01c1 a038 - reserved 01c1 a03c - 01c1 a0ff - reserved 01c1 a100 pcivendevmir pci vendor id/device id mirror register 01c1 a104 pcicsrmir pci command/status mirror register 01c1 a108 pciclrevmir pci class code/revision id mirror register 01c1 a10c pciclinemir pci bist/header type/latency timer/cacheline size mirror register 01c1 a110 pcibar0msk pci base address mask register 0 01c1 a114 pcibar1msk pci base address mask register 1 01c1 a118 pcibar2msk pci base address mask register 2 01c1 a11c pcibar3msk pci base address mask register 3 01c1 a120 pcibar4msk pci base address mask register 4 01c1 a124 pcibar5msk pci base address mask register 5 01c1 a128 - 01c1 a12b - reserved 01c1 a12c pcisubidmir pci subsystem vendor id/subsystem id mirror register 01c1 a130 - reserved 01c1 a134 pcicpbptrmir pci capabilities pointer mirror register 01c1 a138 - 01c1 a13b - reserved 01c1 a13c pcilgintmir pci max latency/min grant/interrupt pin/interrupt line mirror register 01c1 a140 - 01c1 a17f - reserved 01c1 a180 pcislvcntl pci slave control register 01c1 a184 - 01c1 a1bf - reserved 01c1 a1c0 pcibar0trl pci slave base address 0 translation register 01c1 a1c4 pcibar1trl pci slave base address 1 translation register 01c1 a1c8 pcibar2trl pci slave base address 2 translation register 01c1 a1cc pcibar3trl pci slave base address 3 translation register 01c1 a1d0 pcibar4trl pci slave base address 4 translation register 01c1 a1d4 pcibar5trl pci slave base address 5 translation register 01c1 a1d8 - 01c1 a1df - reserved 01c1 a1e0 pcibar0mir pci base address register 0 mirror register 01c1 a1e4 pcibar1mir pci base address register 1 mirror register 01c1 a1e8 pcibar2mir pci base address register 2 mirror register 01c1 a1ec pcibar3mir pci base address register 3 mirror register 01c1 a1f0 pcibar4mir pci base address register 4 mirror register 01c1 a1f4 pcibar5mir pci base address register 5 mirror register 01c1 a1f8 - 01c1 a2ff - reserved 01c1 a300 pcimcfgdat pci master configuration/io access data register 01c1 a304 pcimcfgadr pci master configuration/io access address register peripheral information and electrical specifications 250 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-64. pci back end configuration registers (continued) dmsoc access acronym dmsoc access register name hex address range 01c1 a308 pcimcfgcmd pci master configuration/io access command register 01c1 a30c - 01c1 a30f - reserved 01c1 a310 pcimstcfg pci master configuration register table 7-65. dmsoc-to-pci address translation registers dmsoc access acronym dmsoc access register name hex address range 01c1 a314 pciaddsub0 pci address substitute 0 register 01c1 a318 pciaddsub1 pci address substitute 1 register 01c1 a31c pciaddsub2 pci address substitute 2 register 01c1 a320 pciaddsub3 pci address substitute 3 register 01c1 a324 pciaddsub4 pci address substitute 4 register 01c1 a328 pciaddsub5 pci address substitute 5 register 01c1 a32c pciaddsub6 pci address substitute 6 register 01c1 a330 pciaddsub7 pci address substitute 7 register 01c1 a334 pciaddsub8 pci address substitute 8 register 01c1 a338 pciaddsub9 pci address substitute 9 register 01c1 a33c pciaddsub10 pci address substitute 10 register 01c1 a340 pciaddsub11 pci address substitute 11 register 01c1 a344 pciaddsub12 pci address substitute 12 register 01c1 a348 pciaddsub13 pci address substitute 13 register 01c1 a34c pciaddsub14 pci address substitute 14 register 01c1 a350 pciaddsub15 pci address substitute 15 register 01c1 a354 pciaddsub16 pci address substitute 16 register 01c1 a358 pciaddsub17 pci address substitute 17 register 01c1 a35c pciaddsub18 pci address substitute 18 register 01c1 a360 pciaddsub19 pci address substitute 19 register 01c1 a364 pciaddsub20 pci address substitute 20 register 01c1 a368 pciaddsub21 pci address substitute 21 register 01c1 a36c pciaddsub22 pci address substitute 22 register 01c1 a370 pciaddsub23 pci address substitute 23 register 01c1 a374 pciaddsub24 pci address substitute 24 register 01c1 a378 pciaddsub25 pci address substitute 25 register 01c1 a37c pciaddsub26 pci address substitute 26 register 01c1 a380 pciaddsub27 pci address substitute 27 register 01c1 a384 pciaddsub28 pci address substitute 28 register 01c1 a388 pciaddsub29 pci address substitute 29 register 01c1 a38c pciaddsub30 pci address substitute 30 register 01c1 a390 pciaddsub31 pci address substitute 31 register submit documentation feedback peripheral information and electrical specifications 251
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-66. pci hook configuration registers dmsoc access acronym dmsoc access register name hex address range 01c1 a394 pcivendevprg pci vendor id and device id program register 01c1 a398 ? reserved 01c1 a39c pciclrevprg pci class code and revision id program register 01c1 a3a0 pcisubidprg pci subsystem vendor id and subsystem id program register 01c1 a3a4 pcimaxlgprg pci max latency and min grant program register 01c1 a3a8 ? reserved 01c1 a3ac pcicfgdone pci configuration done register 01c1 a3b0 - 01c1 a3fb ? reserved 01c1 a3fc - 01c1 a3ff ? reserved 01c1 a400 - 01c1 a7ff ? reserved table 7-67. pci external memory space dmsoc hex address acronym description range 3000 0000 - 307f ffff ? pci master window 0 3080 0000 - 30ff ffff ? pci master window 1 3100 0000 - 317f ffff ? pci master window 2 3180 0000 - 31ff ffff ? pci master window 3 3200 0000 - 327f ffff ? pci master window 4 3280 0000 - 32ff ffff ? pci master window 5 3300 0000 - 337f ffff ? pci master window 6 3380 0000 - 33ff ffff ? pci master window 7 3400 0000 - 347f ffff ? pci master window 8 3480 0000 - 34ff ffff ? pci master window 9 3500 0000 - 357f ffff ? pci master window 10 3580 0000 - 35ff ffff ? pci master window 11 3600 0000 - 367f ffff ? pci master window 12 3680 0000 - 36ff ffff ? pci master window 13 3700 0000 - 377f ffff ? pci master window 14 3780 0000 - 37ff ffff ? pci master window 15 3800 0000 - 387f ffff ? pci master window 16 3880 0000 - 38ff ffff ? pci master window 17 3900 0000 - 397f ffff ? pci master window 18 3980 0000 - 39ff ffff ? pci master window 19 3a00 0000 - 3a7f ffff ? pci master window 20 3a80 0000 - 3aff ffff ? pci master window 21 3b00 0000 - 3b7f ffff ? pci master window 22 3b80 0000 - 3bff ffff ? pci master window 23 3c00 0000 - 3c7f ffff ? pci master window 24 3c80 0000 - 3cff ffff ? pci master window 25 3d00 0000 - 3d7f ffff ? pci master window 26 3d80 0000 - 3dff ffff ? pci master window 27 3e00 0000 - 3e7f ffff ? pci master window 28 3e80 0000 - 3eff ffff ? pci master window 29 3f00 0000 - 3f7f ffff ? pci master window 30 3f80 0000 - 3fff ffff ? pci master window 31 peripheral information and electrical specifications 252 submit documentation feedback
7.15.4 pci electrical data/timing tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 texas instruments (ti) has performed the simulation and system characterization to ensure that the pci peripheral meets all ac timing specifications as required by the pci local bus specification revision 2.3. therefore, the ac timing specifications are not reproduced here. for more information on the ac timing specifications, see section 4.2.3, timing specification (33-mhz timing) of the pci local bus specification revision 2.3. note: the dm6467 pci peripheral only supports 3.3-v signaling and 33-mhz operation. submit documentation feedback peripheral information and electrical specifications 253
7.16 ethernet mac (emac) 7.16.1 emac device-specific information tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the ethernet media access controller (emac) module provides an efficient interface between the dm6467 and the networked community. the emac supports 10base-t (10 mbits/second [mbps]), and 100basetx (100 mbps), in either half- or full-duplex mode, and 1000baset (1000 mbps) in full-duplex mode, with hardware flow control and quality-of-service (qos) support. the emac controls the flow of packet data from the dm6467 device to the phy. the mdio module controls the phy configuration and status monitoring. the emac module conforms to the ieee 802.3-2002 standard, describing the ?carrier sense multiple access with collision detection (csma/cd) access method and physical layer? specifications. the ieee 802.3 standard has also been adopted by iso/iec and re-designated as iso/iec 8802-3:2000(e). deviating from this standard, the emac module does not use the transmit coding error signal mtxer. instead of driving the error pin when an underflow condition occurs on a transmitted frame, the emac will intentionally generate an incorrect checksum by inverting the frame crc, so that the transmitted frame will be detected as an error by the network. in addition, the emac i/os operate at 3.3 v and are not compatible with 2.5-v i/o signaling. therefore, only ethernet phys with 3.3-v i/o interface should be used. both the emac and mdio modules interface to the dm6467 device through a custom interface that allows efficient data transmission and reception. this custom interface is referred to as the emac control module. the emac control module contains the necessary components to allow the emac to make efficient use of device memory, plus it controls device interrupts. the emac control module incorporates 8k bytes of internal ram to hold emac buffer descriptors. for more detailed information on the emac, see the tms320dm646x dmsoc ethernet media access controller (emac)/management data input/output (mdio) module user's guide (literature number sprueq6 ). the emac module on the dm6467 supports two interface modes: media independent interface (mii) and gigabit media independent interface (gmii). the mii and gmii interface modes are defined in the ieee 802.3-2002 standard. the dm6467 emac uses the same pins for the mii and gmii modes of operation. only one mode can be used at a time. the mode used is selected at device reset based on the gmiien bit in the maccontrol register. for more detailed information on the emac gmiien bit, see the tms320dm646x dmsoc ethernet media access controller (emac)/management data input/output (mdio) module user's guide (literature number sprueq6 ). the mii and gmii modes-of-operation pins are as follows: mii: mtclk, mrclk, mtxd[3:0], mrxd[3:0], mtxen, mrxdv, mrxer, mcol, mcrs, mdclk, and mdio. gmii: rftclk, gmtclk, mtclk, mrclk, mtxd[7:0], mrxd[7:0], mtxen, mrxdv, mrxer, mcol, mcrs, mdclk, and mdio. 254 peripheral information and electrical specifications submit documentation feedback
7.16.2 emac bus master memory map tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the emac control module includes a multi-channel dma engine which is used to transfer receive and transmit packets between the emac and dm6467 memory. table 7-68 shows the memory map for the emac dma. table 7-68. emac dma master memory map size start address end address emac dma access (bytes) 0x0000 0000 0x3fff ffff 1g reserved 0x4000 0000 0x4bff ffff 192m reserved 0x4c00 0000 0x4fff ffff 64m vlynq (remote data) 0x5000 0000 0x7fff ffff 768m reserved 0x8000 0000 0x9fff ffff 512m ddr2 memory controller 0xa000 0000 0xbfff ffff 512m reserved 0xc000 0000 0xffff ffff 1g reserved submit documentation feedback peripheral information and electrical specifications 255
7.16.3 emac peripheral register description(s) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-69. ethernet mac (emac) control registers hex address range acronym register name 0x01c8 0000 txidver transmit identification and version register 0x01c8 0004 txcontrol transmit control register 0x01c8 0008 txteardown transmit teardown register 0x01c8 000c - 0x01c8 000f ? reserved 0x01c8 0010 rxidver receive identification and version register 0x01c8 0014 rxcontrol receive control register 0x01c8 0018 rxteardown receive teardown register 0x01c8 001c - 0x01c8 007f ? reserved 0x01c8 0080 txintstatraw transmit interrupt status (unmasked) register 0x01c8 0084 txintstatmasked transmit interrupt status (masked) register 0x01c8 0088 txintmaskset transmit interrupt mask set register 0x01c8 008c txintmaskclear transmit interrupt mask clear register 0x01c8 0090 macinvector mac input vector register 0x01c8 0094 maceoivector mac end of interrupt vector register 0x01c8 0098 - 0x01c8 009f ? reserved 0x01c8 00a0 rxintstatraw receive interrupt status (unmasked) register 0x01c8 00a4 rxintstatmasked receive interrupt status (masked) register 0x01c8 00a8 rxintmaskset receive interrupt mask set register 0x01c8 00ac rxintmaskclear receive interrupt mask clear register 0x01c8 00b0 macintstatraw mac interrupt status (unmasked) register 0x01c8 00b4 macintstatmasked mac interrupt status (masked) register 0x01c8 00b8 macintmaskset mac interrupt mask set register 0x01c8 00bc macintmaskclear mac interrupt mask clear register 0x01c8 00c0 - 0x01c8 00ff ? reserved 0x01c8 0100 rxmbpenable receive multicast/broadcast/promiscuous channel enable register 0x01c8 0104 rxunicastset receive unicast enable set register 0x01c8 0108 rxunicastclear receive unicast clear register 0x01c8 010c rxmaxlen receive maximum length register 0x01c8 0110 rxbufferoffset receive buffer offset register 0x01c8 0114 rxfilterlowthresh receive filter low priority frame threshold register 0x01c8 0118 - 0x01c8 011f ? reserved 0x01c8 0120 rx0flowthresh receive channel 0 flow control threshold register 0x01c8 0124 rx1flowthresh receive channel 1 flow control threshold register 0x01c8 0128 rx2flowthresh receive channel 2 flow control threshold register 0x01c8 012c rx3flowthresh receive channel 3 flow control threshold register 0x01c8 0130 rx4flowthresh receive channel 4 flow control threshold register 0x01c8 0134 rx5flowthresh receive channel 5 flow control threshold register 0x01c8 0138 rx6flowthresh receive channel 6 flow control threshold register 0x01c8 013c rx7flowthresh receive channel 7 flow control threshold register 0x01c8 0140 rx0freebuffer receive channel 0 free buffer count register 0x01c8 0144 rx1freebuffer receive channel 1 free buffer count register 0x01c8 0148 rx2freebuffer receive channel 2 free buffer count register 0x01c8 014c rx3freebuffer receive channel 3 free buffer count register 0x01c8 0150 rx4freebuffer receive channel 4 free buffer count register 0x01c8 0154 rx5freebuffer receive channel 5 free buffer count register peripheral information and electrical specifications 256 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-69. ethernet mac (emac) control registers (continued) hex address range acronym register name 0x01c8 0158 rx6freebuffer receive channel 6 free buffer count register 0x01c8 015c rx7freebuffer receive channel 7 free buffer count register 0x01c8 0160 maccontrol mac control register 0x01c8 0164 macstatus mac status register 0x01c8 0168 emcontrol emulation control register 0x01c8 016c fifocontrol fifo control register (transmit and receive) 0x01c8 0170 macconfig mac configuration register 0x01c8 0174 softreset soft reset register 0x01c8 0178 - 0x01c8 01cf ? reserved 0x01c8 01d0 macsrcaddrlo mac source address low bytes register (lower 16-bits) 0x01c8 01d4 macsrcaddrhi mac source address high bytes register (upper 32-bits) 0x01c8 01d8 machash1 mac hash address register 1 0x01c8 01dc machash2 mac hash address register 2 0x01c8 01e0 bofftest back off test register 0x01c8 01e4 tpacetest transmit pacing algorithm test register 0x01c8 01e8 rxpause receive pause timer register 0x01c8 01ec txpause transmit pause timer register 0x01c8 01f0 - 0x01c8 01ff ? reserved 0x01c8 0200 - 0x01c8 02ff (see table 7-70 ) emac statistics registers 0x01c8 0300 - 0x01c8 04ff ? reserved 0x01c8 0500 macaddrlo mac address low bytes register (used in receive address matching) 0x01c8 0504 macaddrhi mac address high bytes register (used in receive address matching) 0x01c8 0508 macindex mac index register 0x01c8 050c - 0x01c8 05ff ? reserved 0x01c8 0600 tx0hdp transmit channel 0 dma head descriptor pointer register 0x01c8 0604 tx1hdp transmit channel 1 dma head descriptor pointer register 0x01c8 0608 tx2hdp transmit channel 2 dma head descriptor pointer register 0x01c8 060c tx3hdp transmit channel 3 dma head descriptor pointer register 0x01c8 0610 tx4hdp transmit channel 4 dma head descriptor pointer register 0x01c8 0614 tx5hdp transmit channel 5 dma head descriptor pointer register 0x01c8 0618 tx6hdp transmit channel 6 dma head descriptor pointer register 0x01c8 061c tx7hdp transmit channel 7 dma head descriptor pointer register 0x01c8 0620 rx0hdp receive channel 0 dma head descriptor pointer register 0x01c8 0624 rx1hdp receive channel 1 dma head descriptor pointer register 0x01c8 0628 rx2hdp receive channel 2 dma head descriptor pointer register 0x01c8 062c rx3hdp receive channel 3 dma head descriptor pointer register 0x01c8 0630 rx4hdp receive channel 4 dma head descriptor pointer register 0x01c8 0634 rx5hdp receive channel 5 dma head descriptor pointer register 0x01c8 0638 rx6hdp receive channel 6 dma head descriptor pointer register 0x01c8 063c rx7hdp receive channel 7 dma head descriptor pointer register transmit channel 0 completion pointer (interrupt acknowledge) 0x01c8 0640 tx0cp register transmit channel 1 completion pointer (interrupt acknowledge) 0x01c8 0644 tx1cp register transmit channel 2 completion pointer (interrupt acknowledge) 0x01c8 0648 tx2cp register transmit channel 3 completion pointer (interrupt acknowledge) 0x01c8 064c tx3cp register submit documentation feedback peripheral information and electrical specifications 257
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-69. ethernet mac (emac) control registers (continued) hex address range acronym register name transmit channel 4 completion pointer (interrupt acknowledge) 0x01c8 0650 tx4cp register transmit channel 5 completion pointer (interrupt acknowledge) 0x01c8 0654 tx5cp register transmit channel 6 completion pointer (interrupt acknowledge) 0x01c8 0658 tx6cp register transmit channel 7 completion pointer (interrupt acknowledge) 0x01c8 065c tx7cp register receive channel 0 completion pointer (interrupt acknowledge) 0x01c8 0660 rx0cp register receive channel 1 completion pointer (interrupt acknowledge) 0x01c8 0664 rx1cp register receive channel 2 completion pointer (interrupt acknowledge) 0x01c8 0668 rx2cp register receive channel 3 completion pointer (interrupt acknowledge) 0x01c8 066c rx3cp register receive channel 4 completion pointer (interrupt acknowledge) 0x01c8 0670 rx4cp register receive channel 5 completion pointer (interrupt acknowledge) 0x01c8 0674 rx5cp register receive channel 6 completion pointer (interrupt acknowledge) 0x01c8 0678 rx6cp register receive channel 7 completion pointer (interrupt acknowledge) 0x01c8 067c rx7cp register 0x01c8 0680 - 0x01c8 07ff ? reserved table 7-70. emac statistics registers hex address range acronym register name 0x01c8 0200 rxgoodframes good receive frames register broadcast receive frames register 0x01c8 0204 rxbcastframes (total number of good broadcast frames received) multicast receive frames register 0x01c8 0208 rxmcastframes (total number of good multicast frames received) 0x01c8 020c rxpauseframes pause receive frames register receive crc errors register 0x01c8 0210 rxcrcerrors (total number of frames received with crc errors) receive alignment/code errors register 0x01c8 0214 rxaligncodeerrors (total number of frames received with alignment/code errors) receive oversized frames register 0x01c8 0218 rxoversized (total number of oversized frames received) receive jabber frames register 0x01c8 021c rxjabber (total number of jabber frames received) receive undersized frames register 0x01c8 0220 rxundersized (total number of undersized frames received) 0x01c8 0224 rxfragments receive frame fragments register 0x01c8 0228 rxfiltered filtered receive frames register 0x01c8 022c rxqosfiltered received qos filtered frames register receive octet frames register 0x01c8 0230 rxoctets (total number of received bytes in good frames) good transmit frames register 0x01c8 0234 txgoodframes (total number of good frames transmitted) 0x01c8 0238 txbcastframes broadcast transmit frames register 0x01c8 023c txmcastframes multicast transmit frames register peripheral information and electrical specifications 258 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-70. emac statistics registers (continued) hex address range acronym register name 0x01c8 0240 txpauseframes pause transmit frames register 0x01c8 0244 txdeferred deferred transmit frames register 0x01c8 0248 txcollision transmit collision frames register 0x01c8 024c txsinglecoll transmit single collision frames register 0x01c8 0250 txmulticoll transmit multiple collision frames register 0x01c8 0254 txexcessivecoll transmit excessive collision frames register 0x01c8 0258 txlatecoll transmit late collision frames register 0x01c8 025c txunderrun transmit underrun error register 0x01c8 0260 txcarriersense transmit carrier sense errors register 0x01c8 0264 txoctets transmit octet frames register 0x01c8 0268 frame64 transmit and receive 64 octet frames register 0x01c8 026c frame65t127 transmit and receive 65 to 127 octet frames register 0x01c8 0270 frame128t255 transmit and receive 128 to 255 octet frames register 0x01c8 0274 frame256t511 transmit and receive 256 to 511 octet frames register 0x01c8 0278 frame512t1023 transmit and receive 512 to 1023 octet frames register 0x01c8 027c frame1024tup transmit and receive 1024 to 1518 octet frames register 0x01c8 0280 netoctets network octet frames register 0x01c8 0284 rxsofoverruns receive fifo or dma start of frame overruns register 0x01c8 0288 rxmofoverruns receive fifo or dma middle of frame overruns register 0x01c8 028c rxdmaoverruns receive dma start of frame and middle of frame overruns register 0x01c8 0290 - 0x01c8 02ff ? reserved table 7-71. emac control module registers hex address range acronym register name 0x01c8 1000 cmidver identification and version register 0x01c8 1004 cmsoftreset software reset register 0x01c8 1008 cmemcontrol emulation control register 0x01c8 100c cmintctrl interrupt control register 0x01c8 1010 cmrxthreshinten receive threshold interrupt enable register 0x01c8 1014 cmrxinten receive interrupt enable register 0x01c8 1018 cmtxinten transmit interrupt enable register 0x01c8 101c cmmiscinten miscellaneous interrupt enable register 0x01c8 1020 - 0x01c8 103f ? reserved 0x01c8 1040 cmrxthreshintstat receive threshold interrupt status register 0x01c8 1044 cmrxintstat receive interrupt status register 0x01c8 1048 cmtxintstat transmit interrupt status register 0x01c8 104c cmmiscintstat miscellaneous interrupt status register 0x01c8 1050 - 0x01c8 106f ? reserved 0x01c8 1070 cmrxintmax receive interrupts per millisecond register 0x01c8 1074 cmtxintmax transmit interrupts per millisecond register 0x01c8 1078 - 0x01c8 10ff ? reserved 0x01c8 1100 - 0x01c8 1fff ? reserved table 7-72. emac descriptor memory hex address range acronym description 0x01c8 2000 - 0x01c8 3fff ? emac control module descriptor memory submit documentation feedback peripheral information and electrical specifications 259
7.16.4 emac electrical data/timing tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-73. timing requirements for mrclk - mii and gmii operation (see figure 7-50 ) -594, -729 1000 mbps no. 100 mbps 10 mbps unit (gmii only) min max min max min max 1 t c(mrclk) cycle time, mrclk 8 40 400 ns 2 t w(mrclkh) pulse duration, mrclk high 2.8 14 140 ns 3 t w(mrclkl) pulse duration, mrclk low 2.8 14 140 ns 4 t t(mrclk) transition time, mrclk 1 3 3 ns figure 7-50. mrclk timing (emac ? receive) [mii and gmii operation] table 7-74. timing requirements for mtclk - mii and gmii operation (see figure 7-51 ) -594, -729 no. 100 mbps 10 mbps unit min max min max 1 t c(mtclk) cycle time, mtclk 40 400 ns 2 t w(mtclkh) pulse duration, mtclk high 14 140 ns 3 t w(mtclkl) pulse duration, mtclk low 14 140 ns 4 t t(mtclk) transition time, mtclk 3 3 ns figure 7-51. mtclk timing (emac ? transmit) [mii and gmii operation] table 7-75. timing requirements for rftclk - gmii operation (see figure 7-52 ) -594, -729 no. 1000 mbps unit min max 1 t c(rftclk) cycle time, rftclk 8 ns 2 t w(rftclkh) pulse duration, rftclk high 2.8 ns 3 t w(rftclkl) pulse duration, rftclk low 2.8 ns 4 t t(rftclk) transition time, rftclk 1 ns peripheral information and electrical specifications 260 submit documentation feedback mrclk (input) 2 3 1 4 4 mtclk (input) 2 3 1 4 4
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 figure 7-52. rftclk timing [gmii operation] submit documentation feedback peripheral information and electrical specifications 261 rftclk (input) 2 3 1 4 4
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-76. switching characteristics over recommended operating conditions for gmtclk - gmii operation (see figure 7-53 ) -594, -729 no. parameter 1000 mbps unit min max 1 t c(gmtclk) cycle time, gmtclk 8 ns 2 t w(gmtclkh) pulse duration, gmtclk high 2.8 ns 3 t w(gmtclkl) pulse duration, gmtclk low 2.8 ns 4 t t(gmtclk) transition time, gmtclk 1 ns figure 7-53. gmtclk timing (emac ? transmit) [gmii operation] table 7-77. timing requirements for emac mii and gmii receive 10/100/1000 mbit/s (1) (see figure 7-54 ) -594, -729 no. 1000 mbps 100/10 mbps unit min max min max setup time, receive selected signals valid before 1 t su(mrxd-mrclkh) 2 8 ns mrclk high hold time, receive selected signals valid after 2 t h(mrclkh-mrxd) 0 8 ns mrclk high (1) for mii, receive selected signals include: mrxd[3:0], mrxdv, and mrxer. for gmii, receive selected signals include: mrxd[7:0], mrxdv, and mrxer. figure 7-54. emac receive interface timing [mii and gmii operation] 262 peripheral information and electrical specifications submit documentation feedback mrclk (input) 1 2 mrxd7?mrxd4(gmii only), mrxd3?mrxd0, mrxdv , mrxer (inputs) gmtclk(output) 2 3 1 4 4
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-78. switching characteristics over recommended operating conditions for emac mii and gmii transmit 10/100 mbit/s (1) (see figure 7-55 ) -594, -729 no. parameter 100/10 mbps unit min max 1 t d(mtclkh-mtxd) delay time, mtclk high to transmit selected signals valid 5 25 ns (1) for mii, transmit selected signals include: mtxd[3:0] and mtxen. for gmii, transmit selected signals include: mtxd[7:0] and mtxen. figure 7-55. emac transmit interface timing [mii and gmii operation] table 7-79. switching characteristics over recommended operating conditions for emac gmii transmit 1000 mbit/s (1) (see figure 7-56 ) -594, -729 no. parameter 1000 mbps unit min max 1 t d(gmtclkh-mtxd) delay time, gmtclk high to transmit selected signals valid 0.5 5 ns (1) for gmii, transmit selected signals include: mtxd[7:0] and mtxen. figure 7-56. emac transmit interface timing [gmii operation] submit documentation feedback peripheral information and electrical specifications 263 1 mtclk (input) mtxd7?mtxd4(gmii only), mtxd3?mtxd0, mtxen (outputs) 1 gmtclk (output) mtxd7?mtxd0, mtxen (outputs)
7.17 management data input/output (mdio) 7.17.1 mdio peripheral register description(s) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the management data input/output (mdio) module continuously polls all 32 mdio addresses in order to enumerate all phy devices in the system. the management data input/output (mdio) module implements the 802.3 serial management interface to interrogate and control ethernet phy(s) using a shared two-wire bus. host software uses the mdio module to configure the auto-negotiation parameters of each phy attached to the emac, retrieve the negotiation results, and configure required parameters in the emac module for correct operation. the module is designed to allow almost transparent operation of the mdio interface, with very little maintenance from the core processor. only one phy may be connected at any given time. for more detailed information on the mdio peripheral, see the tms320dm646x dmsoc ethernet media access controller (emac)/management data input/output (mdio) module user's guide (literature number sprueq6 ) . for a list of supported registers and register fields, see table 7-80 , mdio registers in this data manual. table 7-80. mdio registers hex address range acronym register name 0x01c8 4000 version mdio version register 0x01c8 4004 control mdio control register 0x01c8 4008 alive mdio phy alive status register 0x01c8 400c link mdio phy link status register 0x01c8 4010 linkintraw mdio link status change interrupt (unmasked) register 0x01c8 4014 linkintmasked mdio link status change interrupt (masked) register 0x01c8 4018 - 0x01c8 401f ? reserved 0x01c8 4020 userintraw mdio user command complete interrupt (unmasked) register 0x01c8 4024 userintmasked mdio user command complete interrupt (masked) register 0x01c8 4028 userintmaskset mdio user command complete interrupt mask set register 0x01c8 402c userintmaskclear mdio user command complete interrupt mask clear register 0x01c8 4030 - 0x01c8 407f ? reserved 0x01c8 4080 useraccess0 mdio user access register 0 0x01c8 4084 userphysel0 mdio user phy select register 0 0x01c8 4088 useraccess1 mdio user access register 1 0x01c8 408c userphysel1 mdio user phy select register 1 0x01c8 4090 - 0x01c8 47ff ? reserved peripheral information and electrical specifications 264 submit documentation feedback
7.17.2 management data input/output (mdio) electrical data/timing tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-81. timing requirements for mdio input (see figure 7-57 and figure 7-58 ) -594, -729 no. unit min max 1 t c(mdclk) cycle time, mdclk 400 ns 2 t w(mdclk) pulse duration, mdclk high/low 180 ns 3 t t(mdclk) transition time, mdclk 5 ns 4 t su(mdio-mdclkh) setup time, mdio data input valid before mdclk high 10 ns 5 t h(mdclkh-mdio) hold time, mdio data input valid after mdclk high 10 ns figure 7-57. mdio input timing table 7-82. switching characteristics over recommended operating conditions for mdio output (see figure 7-58 ) -594, -729 no. parameter unit min max 7 t d(mdclkl-mdio) delay time, mdclk low to mdio data output valid 100 ns figure 7-58. mdio output timing submit documentation feedback peripheral information and electrical specifications 265 1 4 5 mdclk mdio (input) 3 3 1 7 mdclk mdio (output)
7.18 host-port interface (hpi) peripheral 7.18.1 hpi device-specific information 7.18.2 hpi bus master tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the hpi is a parallel port through which a host processor can directly access the cpu memory space. the host device functions as a master to the interface, which increases ease of access. the host and cpu can exchange information via internal or external memory. the host also has direct access to memory-mapped peripherals. connectivity to the cpu memory space is provided through the edma3 controller. the dm6467 device includes a user-configurable 32- or 16-bit host-port interface (hpi32/hpi16). multiplexed (address/data) operation configurable single full-word cycle and dual half-word cycle access modes bursting available utilizing 8-word read and write fifos hpia register supports auto-incrementing hpid register/fifos providing data-path between external host interface and system bus multiple strobes and control signals to allow flexible host connection configurable asynchronous hrdy output to allow hpi to insert wait states to the host [system module register hpictl.hrdymode] software control of data prefetching to the hpid/fifos dmsoc-to-host interrupt output signal controlled by hpic accesses host-to-dmsoc interrupt controlled by hpic accesses note: the dm6467 hpi does not support the has feature. for proper hpi operation if the has pin (d4) is routed out, the has pin must be pulled up via an external resistor. the dm6467 hpictl register (0x01c4 0030) is part of the system module registers. the hpictl register controls write access to the hpi peripheral control and address registers as well as determines the host time-out value. the hpictl system module register also determines the operation of the hrdy output which allows the hpi to insert wait states to the host. for more detailed information on the hpictl system module register, see section 4.6.2 , peripheral selection after device reset. for more detailed information on the hpi peripheral, see the tms320dm646x dmsoc host port interface (hpi) user's guide (literature number sprues1 ). the hpi peripheral includes a bus master interface that allows external device initiated transfers to access the dm6467 system bus. table 7-83 shows the memory map for the hpi master interface. table 7-83. hpi master memory map size start address end address hpi access (bytes) 0x0000 0000 0x01bf ffff 28m reserved 0x01c0 0000 0x0fff ffff 228m cfg bus peripherals 0x1000 0000 0x1000 ffff 64k reserved 0x1001 0000 0x1001 3fff 16k arm ram 0 (data) 0x1001 4000 0x1001 7fff 16k arm ram 1 (data) 0x1001 8000 0x1001 ffff 32k arm rom (data) 266 peripheral information and electrical specifications submit documentation feedback
7.18.3 hpi peripheral register description(s) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-83. hpi master memory map (continued) size start address end address hpi access (bytes) 0x1002 0000 0x10ff ffff 16256k 0x1100 0000 0x113f ffff 4m 0x1140 0000 0x114f ffff 1m 0x1150 0000 0x115f ffff 1m reserved 0x1160 0000 0x116f ffff 1m 0x1170 0000 0x117f ffff 1m 0x1180 0000 0x1180 ffff 64k 0x1181 0000 0x1181 7fff 32k 0x1181 8000 0x1183 7fff 128k c64x+ l2 ram/cache 0x1183 8000 0x118f ffff 800k reserved 0x1190 0000 0x11df ffff 5m 0x11e0 0000 0x11e0 7fff 32k c64x+ l1p ram/cache 0x11e0 8000 0x11ef ffff 992k reserved 0x11f0 0000 0x11f0 7fff 32k c64x+ l1d ram/cache 0x11f0 8000 0x11ff ffff 992k reserved 0x1200 0000 0x4bff ffff 928m 0x4c00 0000 0x4fff ffff 64m vlynq (remote data) 0x5000 0000 0x7fff ffff 768m reserved 0x8000 0000 0x9fff ffff 512m ddr2 memory controller 0xa000 0000 0xbfff ffff 512m reserved 0xc000 0000 0xffff ffff 1g reserved table 7-84. hpi control registers hex address range acronym register name comments 01c6 7800 pid peripheral identification register the arm/c64x+ has 01c6 7804 pwremu_mgmt hpi power and emulation management register read/write access to the pwremu_mgmt register. 01c6 7808 - 01c6 782f - reserved the host and the arm/c64x+ both have 01c6 7830 hpic hpi control register read/write access to the hpic register. hpia hpi address register the host has read/write 01c6 7834 (hpiaw) (1) (write) access to the hpia registers. the arm/c64x+ has only hpia hpi address register read access to the hpia 01c6 7838 (hpiar) (1) (read) registers. 01c6 783c - 01c6 7fff - reserved (1) there are two 32-bit hpia registers: hpiar for read operations and hpiaw for write operations. the hpi can be configured such that hpiar and hpiaw act as a single 32-bit hpia (single-hpia mode) or as two separate 32-bit hpias (dual-hpia mode) from the perspective of the host. the arm/c64x+ can access hpiaw and hpiar independently. for more details about the hpia registers and their modes, see the tms320dm646x dmsoc host port interface (hpi) user's guide (literature number sprues1 ). submit documentation feedback peripheral information and electrical specifications 267
7.18.4 hpi electrical data/timing tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-85. timing requirements for host-port interface cycles (1) (2) (see figure 7-59 through figure 7-62 ) -594, -729 no. unit min max 1 t su(selv-hstbl) setup time, select signals (3) valid before hstrobe low 5 ns 2 t h(hstbl-selv) hold time, select signals (3) valid after hstrobe low 2 ns 3 t w(hstbl) pulse duration, hstrobe active low 15 ns 4 t w(hstbh) pulse duration, hstrobe inactive high between consecutive accesses 2m ns 11 t su(hdv-hstbh) setup time, host data valid before hstrobe high 5 ns 12 t h(hstbh-hdv) hold time, host data valid after hstrobe high 0.15 ns hold time, hstrobe low after hrdy low. hstrobe should not be 13 t h(hrdyl-hstbl) inactivated until hrdy is active (low); otherwise, hpi writes will not 0 ns complete properly. (1) hstrobe refers to the following logical operation on hcs, hds1, and hds2: [not( hds1 xor hds2)] or hcs. (2) m = sysclk3 period = (cpu clock frequency)/4 in ns. for example, when running parts at 594 mhz, use m = m = 1.68 ns. (3) select signals include: hcntl[1:0], hr/ w. for hpi16 mode only, select signals also includes hhwil. peripheral information and electrical specifications 268 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-86. switching characteristics for host-port interface cycles (1) (2) (3) (see figure 7-59 through figure 7-62 ) -594, -729 no. parameter unit min max for hpi write, hrdy can go high ( not ready) for these hpi write conditions; otherwise, hrdy stays low ( ready): case 1: back-to-back hpia writes (can be either first or second half-word) case 2: hpia write following a prefetch command (can be either first or second half-word) case 3: hpid write when fifo is full or flushing (can be either first or second half-word) case 4: hpia write and write fifo not empty for hpi read, hrdy can go high ( not ready) for these hpi read conditions: case 1: hpid read (with delay time, hstrobe low to 5 t d(hstbl-hrdyv) 12 ns auto-increment) and data not in read hrdy valid fifo (can only happen to first half-word of hpid access) case 2: first half-word access of hpid read without auto-increment for hpi read, hrdy stays low ( ready) for these hpi read conditions: case 1: hpid read with auto-increment and data is already in read fifo (applies to either half-word of hpid access) case 2: hpid read without auto-increment and data is already in read fifo (always applies to second half-word of hpid access) case 3: hpic or hpia read (applies to either half-word access) 6 t en(hstbl-hd) enable time, hd driven from hstrobe low 2 ns 7 t d(hrdyl-hdv) delay time, hrdy low to hd valid 0 ns 8 t oh(hstbh-hdv) output hold time, hd valid after hstrobe high 1.5 ns 14 t dis(hstbh-hdv) disable time, hd high-impedance from hstrobe high 12 ns for hpi read. applies to conditions where data is already residing in hpid/fifo: case 1: hpic or hpia read delay time, hstrobe low to 15 t d(hstbl-hdv) case 2: first half-word of hpid read 12 ns hd valid with auto-increment and data is already in read fifo case 3: second half-word of hpid read with or without auto-increment (1) m = sysclk3 period = (cpu clock frequency)/4 in ns. for example, when running parts at 594 mhz, use m = 1.68 ns. (2) hstrobe refers to the following logical operation on hcs, hds1, and hds2: [not( hds1 xor hds2)] or hcs. (3) by design, whenever hcs is driven inactive (high), hpi will drive hrdy active (low). submit documentation feedback peripheral information and electrical specifications 269
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com figure 7-59. hpi16 read timing ( has not used, tied high) 270 peripheral information and electrical specifications submit documentation feedback hcs has (d) hcntl[1:0] hr/w hhwil hstrobe (a)(c) hd[15:0] (output) hrdy (b) 1 2 1 2 1 2 5 6 3 4 3 1 2 1 2 1 2 8 14 15 14 8 7 1st half-w ord 2nd half-w ord 6 13 15 a. hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . b. depending on the type of write or read operation (hpid without auto-incrementing; hpia, hpic, or hpid with auto-incrementing) and the state of the fifo, transitions on hrdy may or may not occur . for more detailed information on the hpi peripheral, see the tms320dm646x dmsoc host port interface (hpi) user 's guide (literature number sprues1). c. hcs reflects typical hcs behavior when hstrobe assertion is caused by hds1 or hds2 . hcs timing requirements are reflected by parameters for hstrobe . d. for proper hpi operation, has must be pulled up via an external resistor .
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 figure 7-60. hpi16 write timing ( has not used, tied high) submit documentation feedback peripheral information and electrical specifications 271 has (d) hcntl[1:0] hr/w hhwil hstrobe (a)(c) hcs hd[15:0] (input) hrdy (b) 2 1 2 1 1 22 1 2 1 1 2 3 4 3 11 12 13 5 5 11 12 13 2nd half-w ord 1st half-w ord a. hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . b. depending on the type of write or read operation (hpid without auto-incrementing; hpia, hpic, or hpid with auto-incrementing) and the state of the fifo, transitions on hrdy may or may not occur . for more detailed information on the hpi peripheral, see the tms320dm646x dmsoc host port interface (hpi) user ' s guide (literature number sprues1). c. hcs reflects typical hcs behavior when hstrobe assertion is caused by hds1 or hds2 . hcs timing requirements are reflected by parameters for hstrobe . d. for proper hpi operation, has must be pulled up via an external resistor .
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com figure 7-61. hpi32 read timing ( has not used, tied high) 272 peripheral information and electrical specifications submit documentation feedback 1 2 6 8 5 15 13 3 7 hcs (input) has (d) (input) hstrobe (a)(c) (input) hr/ (input) w hrdy (b) (output) hd[31:0] (output) hcntl[1:0] (input) 14 a. refers to the following logical operation on , , and : [not( xor )] or . hstrobe hcs hds1 hds2 hds1 hds2 hcs b. depending on the type of write or read operation (hpid without auto-incrementing; hpia, hpic, or hpid with auto- incrementing) and the state of the fifo, transitions on may or may not occur. for more detailed information on the hpi peripheral, see the user's guide (literature number sprues1). c. reflects typical behavior when assertion is caused by or . timing requirements are reflected by parameters for . d. for proper hpi operation, be pulled up via an external resistor. hrdy hcs hcs hstrobe hds1 hds2 hcs hstrobe has tms320dm646x dmsoc host port interface (hpi) must
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 figure 7-62. hpi32 write timing ( has not used, tied high) submit documentation feedback peripheral information and electrical specifications 273 11 1 13 2 3 12 5 hcs (input) has (d) (input) hstrobe (a)(c) (input) hr/w (input) hrdy (b) (output) hd[31:0] (input) hcntl[1:0] (input) a. hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . b. depending on the type of write or read operation (hpid without auto-incrementing; hpia, hpic, or hpid with auto-incrementing) and the state of the fifo, transitions on hrdy may or may not occur . for more detailed information on the hpi peripheral, see the tms320dm646x dmsoc host port interface (hpi) user ' s guide (literature number sprues1). c. hcs reflects typical hcs behavior when hstrobe assertion is caused by hds1 or hds2 . hcs timing requirements are reflected by parameters for hstrobe . d. for proper hpi operation, has must be pulled up via an external resistor .
7.19 usb 2.0 7.19.1 usb dma master tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the dm6467 usb2.0 peripheral supports the following features: usb 2.0 peripheral at speeds high speed (hs: 480 mb/s) and full speed (fs: 12 mb/s) usb 2.0 host at speeds hs, fs, and low speed (ls: 1.5 mb/s) each endpoint (other than endpoint 0) can support all transfer modes (control, bulk, interrupt, and isochronous) 4 transmit (tx) and 4 receive (rx) endpoints in addition to endpoint 0 fifo ram ? 4k endpoint ? programmable size connects to a standard utmi+ phy with a 60-mhz, 8-bit interface external 5-v power supply for vbus, when operating as host, enabled directly by the usb controller via a dedicated signal rndis mode for accelerating rndis type protocols using short packet termination over usb the usb2.0 peripheral interface includes a master dma engine that allows the usb to access the dm6467 system bus. table 7-87 shows the memory map for the usb2.0 dma engine. table 7-87. usb2.0 dma master memory map size start address end address usb2.0 dma access (bytes) 0x0000 0000 0x0fff ffff 256m reserved 0x1000 0000 0x1000 ffff 64k reserved 0x1001 0000 0x1001 3fff 16k arm ram 0 (data) 0x1001 4000 0x1001 7fff 16k arm ram 1 (data) 0x1001 8000 0x1001 ffff 32k arm rom (data) 0x1002 0000 0x10ff ffff 16256k 0x1100 0000 0x113f ffff 4m 0x1140 0000 0x114f ffff 1m 0x1150 0000 0x115f ffff 1m reserved 0x1160 0000 0x116f ffff 1m 0x1170 0000 0x117f ffff 1m 0x1180 0000 0x1180 ffff 64k 0x1181 0000 0x1181 7fff 32k 0x1181 8000 0x1183 7fff 128k c64x+ l2 ram/cache 0x1183 8000 0x118f ffff 800k reserved 0x1190 0000 0x11df ffff 5m 0x11e0 0000 0x11e0 7fff 32k c64x+ l1p ram/cache 0x11e0 8000 0x11ef ffff 992k reserved 0x11f0 0000 0x11f0 7fff 32k c64x+ l1d ram/cache 0x11f0 8000 0x11ff ffff 992k reserved 0x1200 0000 0x4bff ffff 928m 0x4c00 0000 0x4fff ffff 64m vlynq (remote data) 0x5000 0000 0x7fff ffff 768m reserved 0x8000 0000 0x9fff ffff 512m ddr2 memory controller 0xa000 0000 0xbfff ffff 512m reserved 0xc000 0000 0xffff ffff 1g reserved peripheral information and electrical specifications 274 submit documentation feedback
7.19.2 usb2.0 device-specific information tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the dm6467 usbctl register (0x01c4 00034) is part of the system module registers. the usbctl register controls the usb data polarity, host/peripheral mode, and vbus sense, along with the phy power and clock good, phy pll suspend override, and phy power down. for more detailed information on the usbctl system module register, see section 4.6.2 , peripheral selection after device reset for more detailed information on the usb2.0 peripheral, see the tms320dm646x dmsoc universal serial bus (usb) controller user's guide (literature number spruer7 ). submit documentation feedback peripheral information and electrical specifications 275
7.19.3 usb2.0 peripheral register description(s) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-88 shows the usb perripheral register memory mapping. table 7-88. usb2.0 registers hex address acronym register name range 0x01c6 4000 revr revision register 0x01c6 4004 ctrlr control register 0x01c6 4008 statr status register 0x01c6 400c - reserved ? 0x01c6 400f 0x01c6 4010 rndisr rndis register 0x01c6 4014 autoreq auto request register 0x01c6 4018 - reserved ? 0x01c6 401f 0x01c6 4020 intsrcr usb interrupt source register 0x01c6 4024 intsetr usb interrupt source set register 0x01c6 4028 intclrr usb interrupt source clear register 0x01c6 402c intmskr usb interrupt mask register 0x01c6 4030 intmsksetr usb interrupt mask set register 0x01c6 4034 intmskclrr usb interrupt mask clear register 0x01c6 4038 intmaskedr usb interrupt source masked register 0x01c6 403c eoir usb end of interrupt register 0x01c6 4040 intvectr usb interrupt vector register 0x01c6 4044 - reserved ? 0x01c6 407f 0x01c6 4080 tcppicr tx cppi control register 0x01c6 4084 tcppitdr tx cppi teardown register 0x01c6 4088 tcppieoir tx cppi dma controller end of interrupt register 0x01c6 408c tcppiivectr tx cppi dma controller interrupt vector register 0x01c6 4090 tcppimsksr tx cppi masked status register 0x01c6 4094 tcppirawsr tx cppi raw status register 0x01c6 4098 tcppiiensetr tx cppi interrupt enable set register 0x01c6 409c tcppiienclrr tx cppi interrupt enable clear register 0x01c6 40a0 - reserved ? 0x01c6 40bf 0x01c6 40c0 rcppicr rx cppi control register 0x01c6 40c4 - reserved ? 0x01c6 40cf 0x01c6 40d0 rcppimsksr rx cppi masked status register 0x01c6 40d4 rcppirawsr rx cppi raw status register 0x01c6 40d8 rcppiensetr rx cppi interrupt enable set register 0x01c6 40dc rcppiienclrr rx cppi interrupt enable clear register 0x01c6 40e0 rbufcnt0 rx buffer count 0 register 0x01c6 40e4 rbufcnt1 rx buffer count 1 register 0x01c6 40e8 rbufcnt2 rx buffer count 2 register 0x01c6 40ec rbufcnt3 rx buffer count 3 register 0x01c6 40f0 - reserved ? 0x01c6 40ff tx/rx ccpi channel 0 state block 0x01c6 4100 tcppidmastatew0 tx cppi dma state word 0 peripheral information and electrical specifications 276 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-88. usb2.0 registers (continued) hex address acronym register name range 0x01c6 4104 tcppidmastatew1 tx cppi dma state word 1 0x01c6 4108 tcppidmastatew2 tx cppi dma state word 2 0x01c6 410c tcppidmastatew3 tx cppi dma state word 3 0x01c6 4110 tcppidmastatew4 tx cppi dma state word 4 0x01c6 4114 tcppidmastatew5 tx cppi dma state word 5 0x01c6 4118 ? reserved 0x01c6 411c tcppicompptr tx cppi completion pointer 0x01c6 4120 rcppidmastatew0 rx cppi dma state word 0 0x01c6 4124 rcppidmastatew1 rx cppi dma state word 1 0x01c6 4128 rcppidmastatew2 rx cppi dma state word 2 0x01c6 412c rcppidmastatew3 rx cppi dma state word 3 0x01c6 4130 rcppidmastatew4 rx cppi dma state word 4 0x01c6 4134 rcppidmastatew5 rx cppi dma state word 5 0x01c6 4138 rcppidmastatew6 rx cppi dma state word 6 0x01c6 413c rcppicompptr rx cppi completion pointer tx/rx ccpi channel 1 state block 0x01c6 4140 tcppidmastatew0 tx cppi dma state word 0 0x01c6 4144 tcppidmastatew1 tx cppi dma state word 1 0x01c6 4148 tcppidmastatew2 tx cppi dma state word 2 0x01c6 414c tcppidmastatew3 tx cppi dma state word 3 0x01c6 4150 tcppidmastatew4 tx cppi dma state word 4 0x01c6 4154 tcppidmastatew5 tx cppi dma state word 5 0x01c6 4158 ? reserved 0x01c6 415c tcppicompptr tx cppi completion pointer 0x01c6 4160 rcppidmastatew0 rx cppi dma state word 0 0x01c6 4164 rcppidmastatew1 rx cppi dma state word 1 0x01c6 4168 rcppidmastatew2 rx cppi dma state word 2 0x01c6 416c rcppidmastatew3 rx cppi dma state word 3 0x01c6 4170 rcppidmastatew4 rx cppi dma state word 4 0x01c6 4174 rcppidmastatew5 rx cppi dma state word 5 0x01c6 4178 rcppidmastatew6 rx cppi dma state word 6 0x01c6 417c rcppicompptr rx cppi completion pointer tx/rx ccpi channel 2 state block 0x01c6 4180 tcppidmastatew0 tx cppi dma state word 0 0x01c6 4184 tcppidmastatew1 tx cppi dma state word 1 0x01c6 4188 tcppidmastatew2 tx cppi dma state word 2 0x01c6 418c tcppidmastatew3 tx cppi dma state word 3 0x01c6 4190 tcppidmastatew4 tx cppi dma state word 4 0x01c6 4194 tcppidmastatew5 tx cppi dma state word 5 0x01c6 4198 ? rserved 0x01c6 419c tcppicompptr tx cppi completion pointer 0x01c6 41a0 rcppidmastatew0 rx cppi dma state word 0 0x01c6 41a4 rcppidmastatew1 rx cppi dma state word 1 0x01c6 41a8 rcppidmastatew2 rx cppi dma state word 2 0x01c6 41ac rcppidmastatew3 rx cppi dma state word 3 0x01c6 41b0 rcppidmastatew4 rx cppi dma state word 4 submit documentation feedback peripheral information and electrical specifications 277
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-88. usb2.0 registers (continued) hex address acronym register name range 0x01c6 41b4 rcppidmastatew5 rx cppi dma state word 5 0x01c6 41b8 rcppidmastatew6 rx cppi dma state word 6 0x01c6 41bc rcppicompptr rx cppi completion pointer tx/rx ccpi channel 3 state block 0x01c6 41c0 tcppidmastatew0 tx cppi dma state word 0 0x01c6 41c4 tcppidmastatew1 tx cppi dma state word 1 0x01c6 41c8 tcppidmastatew2 tx cppi dma state word 2 0x01c6 41cc tcppidmastatew3 tx cppi dma state word 3 0x01c6 41d0 tcppidmastatew4 tx cppi dma state word 4 0x01c6 41d4 tcppidmastatew5 tx cppi dma state word 5 0x01c6 41d8 ? rserved 0x01c6 41dc tcppicompptr tx cppi completion pointer 0x01c6 41e0 rcppidmastatew0 rx cppi dma state word 0 0x01c6 41e4 rcppidmastatew1 rx cppi dma state word 1 0x01c6 41e8 rcppidmastatew2 rx cppi dma state word 2 0x01c6 41ec rcppidmastatew3 rx cppi dma state word 3 0x01c6 41f0 rcppidmastatew4 rx cppi dma state word 4 0x01c6 41f4 rcppidmastatew5 rx cppi dma state word 5 0x01c6 41f8 rcppidmastatew6 rx cppi dma state word 6 0x01c6 41fc rcppicompptr rx cppi completion pointer 0x01c6 4200 - reserved ? 0x01c6 43ff core registers 0x01c6 4400 faddr function address register 0x01c6 4401 power power management register 0x01c6 4402 intrtx interrupt register for endpoint 0 plus tx endpoints 1 to 4 0x01c6 4404 intrrx interrupt register for rx endpoints 1 to 4 0x01c6 4406 intrtxe interrupt enable register for intrtx 0x01c6 4408 intrrxe interrupt enable register for intrrx 0x01c6 440a intrusb interrupt register for common usb interrupts 0x01c6 440b intrusbe interrupt enable register for intrusb 0x01c6 440c frame frame number register 0x01c6 440e index index register for selecting the endpoint status and control registers 0x01c6 440f testmode register to enable the usb 2.0 test modes maximum packet size for peripheral/host tx endpoint (index register set to select 0x01c6 4410 txmaxp endpoints 1 - 4 only) control status register for endpoint 0 in peripheral mode. (index register set to peri_csr0 select endpoint 0) control status register for endpoint 0 in host mode. (index register set to select host_csr0 endpoint 0) 0x01c6 4412 control status register for peripheral tx endpoint. (index register set to select peri_txcsr endpoints 1 - 4) control status register for host tx endpoint. (index register set to select host_txcsr endpoints 1 - 4) maximum packet size for peripheral/host rx endpoint (index register set to select 0x01c6 4414 rxmaxp endpoints 1 - 4 only) peripheral information and electrical specifications 278 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-88. usb2.0 registers (continued) hex address acronym register name range control status register for peripheral rx endpoint. (index register set to select peri_rxcsr endpoints 1 - 4) 0x01c6 4416 control status register for host rx endpoint. (index register set to select host_rxcsr endpoints 1 - 4) number of received bytes in endpoint 0 fifo. (index register set to select count0 endpoint 0) 0x01c6 4418 number of bytes in host rx endpoint fifo. (index register set to select rxcount endpoints 1 - 4) 0x01c6 441a host_type0 defines the speed of endpoint 0 sets the operating speed, transaction protocol and peripheral endpoint number 0x01c6 441a host_txtype for the host tx endpoint. (index register set to select endpoints 1 - 4 only) sets the nak response timeout on endpoint 0. (index register set to select 0x01c6 441b host_naklimit0 endpoint 0) sets the polling interval for interrupt/isoc transactions or the nak response 0x01c6 441b host_txinterval timeout on bulk transactions for host tx endpoint. (index register set to select endpoints 1 - 4 only) sets the operating speed, transaction protocol and peripheral endpoint number 0x01c6 441c host_rxtype for the host rx endpoint. (index register set to select endpoints 1 - 4 only) sets the polling interval for interrupt/isoc transactions or the nak response 0x01c6 441d host_rxinterval timeout on bulk transactions for host rx endpoint. (index register set to select endpoints 1 - 4 only) 0x01c6 441f configdata returns details of core configuration (index register set to select endpoint 0) 0x01c6 4420 fifo0 tx and rx fifo register for endpoint 0 0x01c6 4424 fifo1 tx and rx fifo register for endpoint 1 0x01c6 4428 fifo2 tx and rx fifo register for endpoint 2 0x01c6 442c fifo3 tx and rx fifo register for endpoint 3 0x01c6 4430 fifo4 tx and rx fifo register for endpoint 4 0x01c6 4460 devctl device control register 0x01c6 4462 txfifosz tx endpoint fifo size (index register set to select endpoints 0 - 4 only) 0x01c6 4463 rxfifosz rx endpoint fifo size (index register set to select endpoints 0 - 4 only) 0x01c6 4464 txfifoaddr tx endpoint fifo address (index register set to select endpoints 0 - 4 only) 0x01c6 4466 rxfifoaddr rx endpoint fifo address (index register set to select endpoints 0 - 4 only) target endpoint control registers (valid only in host mode) - eptrg0 address of the target function that has to be accessed through the associated tx 0x01c6 4480 txfuncaddr endpoint address of the hub that has to be accessed through the associated tx endpoint. 0x01c6 4482 txhubaddr this is used only when full-speed or low-speed device is connected via a usb2.0 high-speed hub. port of the hub that has to be accessed through the associated tx endpoint. this 0x01c6 4483 txhubport is used only when full-speed or low-speed device is connected via a usb2.0 high-speed hub. address of the target function that has to be accessed through the associated rx 0x01c6 4484 rxfuncaddr endpoint address of the hub that has to be accessed through the associated rx endpoint. 0x01c6 4486 rxhubaddr this is used only when full-speed or low-speed device is connected via a usb2.0 high-speed hub. port of the hub that has to be accessed through the associated rx endpoint. 0x01c6 4487 rxhubport this is used only when full speed or low speed device is connected via a usb2.0 high speed hub target endpoint control registers (valid only in host mode) - eptrg1 address of the target function that has to be accessed through the associated tx 0x01c6 4488 txfuncaddr endpoint submit documentation feedback peripheral information and electrical specifications 279
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-88. usb2.0 registers (continued) hex address acronym register name range address of the hub that has to be accessed through the associated tx endpoint. 0x01c6 448a txhubaddr this is used only when full-speed or low-speed device is connected via a usb2.0 high-speed hub. port of the hub that has to be accessed through the associated tx endpoint. this 0x01c6 448b txhubport is used only when full-speed or low-speed device is connected via a usb2.0 high-speed hub. address of the target function that has to be accessed through the associated rx 0x01c6 448c rxfuncaddr endpoint address of the hub that has to be accessed through the associated rx endpoint. 0x01c6 448e rxhubaddr this is used only when full-speed or low-speed device is connected via a usb2.0 high speed hub port of the hub that has to be accessed through the associated rx endpoint. 0x01c6 448f rxhubport this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. target endpoint control registers (valid only in host mode) - eptrg2 address of the target function that has to be accessed through the associated tx 0x01c6 4490 txfuncaddr endpoint address of the hub that has to be accessed through the associated tx endpoint. 0x01c6 4492 txhubaddr this is used only when full-speed or low-speed device is connected via a usb2.0 high-speed hub. port of the hub that has to be accessed through the associated tx endpoint. this 0x01c6 4493 txhubport is used only when full-speed or low-speed device is connected via a usb2.0 high-speed hub. address of the target function that has to be accessed through the associated rx 0x01c6 4494 rxfuncaddr endpoint address of the hub that has to be accessed through the associated rx endpoint. 0x01c6 4496 rxhubaddr this is used only when full-speed or low-speed device is connected via a usb2.0 high-speed hub. port of the hub that has to be accessed through the associated rx endpoint. 0x01c6 4497 rxhubport this is used only when full-speed or low-speed device is connected via a usb2.0 high-speed hub. target endpoint control registers (valid only in host mode) - eptrg3 address of the target function that has to be accessed through the associated tx 0x01c6 4498 txfuncaddr endpoint address of the hub that has to be accessed through the associated tx endpoint. 0x01c6 449a txhubaddr this is used only when full-speed or low-speed device is connected via a usb2.0 high-speed hub. port of the hub that has to be accessed through the associated tx endpoint. this 0x01c6 449b txhubport is used only when full -peed or low-speed device is connected via a usb2.0 high-speed hub. address of the target function that has to be accessed through the associated rx 0x01c6 449c rxfuncaddr endpoint address of the hub that has to be accessed through the associated rx endpoint. 0x01c6 449e rxhubaddr this is used only when full-speed or low-speed device is connected via a usb2.0 high-speed hub. port of the hub that has to be accessed through the associated rx endpoint. 0x01c6 449f rxhubport this is used only when full-speed or low-speed device is connected via a usb2.0 high-speed hub. target endpoint control registers (valid only in host mode) - eptrg4 address of the target function that has to be accessed through the associated tx 0x01c6 44a0 txfuncaddr endpoint address of the hub that has to be accessed through the associated tx endpoint. 0x01c6 44a2 txhubaddr this is used only when full-speed or low-speed device is connected via a usb2.0 high-speed hub. port of the hub that has to be accessed through the associated tx endpoint. this 0x01c6 44a3 txhubport is used only when full-speed or low-speed device is connected via a usb2.0 high-speed hub. peripheral information and electrical specifications 280 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-88. usb2.0 registers (continued) hex address acronym register name range address of the target function that has to be accessed through the associated rx 0x01c6 44a4 rxfuncaddr endpoint address of the hub that has to be accessed through the associated rx endpoint. 0x01c6 44a6 rxhubaddr this is used only when full-speed or low-speed device is connected via a usb2.0 high-speed hub. port of the hub that has to be accessed through the associated rx endpoint. 0x01c6 44a7 rxhubport this is used only when full-speed or low-speed device is connected via a usb2.0 high-speed hub. control and status register for endpoint 0 - eocsr0 peri_csr0 control status register for endpoint 0 in peripheral mode 0x01c6 4502 host_csr0 control status register for endpoint 0 in host mode 0x01c6 4508 count0 number of received bytes in endpoint 0 fifo 0x01c6 450a host_type0 defines the speed of endpoint 0 0x01c6 450b host_naklimit0 sets the nak response timeout on endpoint 0. 0x01c6 450f configdata returns details of core configuration control and status register for endpoint 1 - eocsr1 0x01c6 4510 txmaxp maximum packet size for peripheral/host tx endpoint peri_txcsr control status register for peripheral tx endpoint 0x01c6 4512 host_txcsr control status register for host tx endpoint 0x01c6 4514 rxmaxp maximum packet size for peripheral/host rx endpoint peri_rxcsr control status register for peripheral rx endpoint 0x01c6 4516 host_rxcsr control status register for host rx endpoint 0x01c6 4518 rxcount number of bytes in host rx endpoint fifo sets the operating speed, transaction protocol and peripheral endpoint number 0x01c6 451a host_txtype for the host tx endpoint. sets the polling interval for interrupt/isoc transactions or the nak response 0x01c6 451b host_txinterval timeout on bulk transactions for host tx endpoint. sets the operating speed, transaction protocol and peripheral endpoint number 0x01c6 451c host_rxtype for the host rx endpoint. sets the polling interval for interrupt/isoc transactions or the nak response 0x01c6 451d host_rxinterval timeout on bulk transactions for host rx endpoint. control and status register for endpoint 2 - eocsr2 0x01c6 4520 txmaxp maximum packet size for peripheral/host tx endpoint peri_txcsr control status register for peripheral tx endpoint 0x01c6 4522 host_txcsr control status register for host tx endpoint 0x01c6 4524 rxmaxp maximum packet size for peripheral/host rx endpoint peri_rxcsr control status register for peripheral rx endpoint 0x01c6 4526 host_rxcsr control status register for host rx endpoint 0x01c6 4528 rxcount number of bytes in host rx endpoint fifo sets the operating speed, transaction protocol and peripheral endpoint number 0x01c6 452a host_txtype for the host tx endpoint. sets the polling interval for interrupt/isoc transactions or the nak response 0x01c6 452b host_txinterval timeout on bulk transactions for host tx endpoint. sets the operating speed, transaction protocol and peripheral endpoint number 0x01c6 452c host_rxtype for the host rx endpoint. sets the polling interval for interrupt/isoc transactions or the nak response 0x01c6 452d host_rxinterval timeout on bulk transactions for host rx endpoint. control and status register for endpoint 3 - eocsr3 0x01c6 4530 txmaxp maximum packet size for peripheral/host tx endpoint submit documentation feedback peripheral information and electrical specifications 281
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-88. usb2.0 registers (continued) hex address acronym register name range peri_txcsr control status register for peripheral tx endpoint 0x01c6 4532 host_txcsr control status register for host tx endpoint 0x01c6 4534 rxmaxp maximum packet size for peripheral/host rx endpoint peri_rxcsr control status register for peripheral rx endpoint 0x01c6 4536 host_rxcsr control status register for host rx endpoint 0x01c6 4538 rxcount number of bytes in host rx endpoint fifo sets the operating speed, transaction protocol and peripheral endpoint number 0x01c6 453a host_txtype for the host tx endpoint. sets the polling interval for interrupt/isoc transactions or the nak response 0x01c6 453b host_txinterval timeout on bulk transactions for host tx endpoint. sets the operating speed, transaction protocol and peripheral endpoint number 0x01c6 453c host_rxtype for the host rx endpoint. sets the polling interval for interrupt/isoc transactions or the nak response 0x01c6 453d host_rxinterval timeout on bulk transactions for host rx endpoint. control and status register for endpoint 4 - eocsr4 0x01c6 4540 txmaxp maximum packet size for peripheral/host tx endpoint peri_txcsr control status register for peripheral tx endpoint 0x01c6 4542 host_txcsr control status register for host tx endpoint 0x01c6 4544 rxmaxp maximum packet size for peripheral/host rx endpoint peri_rxcsr control status register for peripheral rx endpoint 0x01c6 4546 host_rxcsr control status register for host rx endpoint 0x01c6 4548 rxcount number of bytes in host rx endpoint fifo sets the operating speed, transaction protocol and peripheral endpoint number 0x01c6 454a host_txtype for the host tx endpoint. sets the polling interval for interrupt/isoc transactions or the nak response 0x01c6 454b host_txinterval timeout on bulk transactions for host tx endpoint. sets the operating speed, transaction protocol and peripheral endpoint number 0x01c6 454c host_rxtype for the host rx endpoint. sets the polling interval for interrupt/isoc transactions or the nak response 0x01c6 454d host_rxinterval timeout on bulk transactions for host rx endpoint. peripheral information and electrical specifications 282 submit documentation feedback
7.19.4 usb2.0 electrical data/timing tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-89. switching characteristics over recommended operating conditions for usb2.0 (see figure 7-63 ) -594, -729 low speed full speed high speed no. parameter unit 1.5 mbps 12 mbps 480 mbps min max min max min max 1 t r(d) rise time, usb_dp and usb_dn signals (1) 75 300 4 20 0.5 ns 2 t f(d) fall time, usb_dp and usb_dn signals (1) 75 300 4 20 0.5 ns 3 t rfm rise/fall time, matching (2) 80 125 90 111.11 ? ? % 4 v crs output signal cross-over voltage (1) 1.3 2 1.3 2 ? ? v 5 t jr(source)nt source (host) driver jitter, next transition 2 2 (3) ns t jr(func)nt function driver jitter, next transition 25 2 (3) ns 6 t jr(source)pt source (host) driver jitter, paired transition (4) 1 1 (3) ns t jr(func)pt function driver jitter, paired transition 10 1 (3) ns 7 t w(eopt) pulse duration, eop transmitter 1250 1500 160 175 ? ? ns 8 t w(eopr) pulse duration, eop receiver 670 82 ? ns 9 t (drate) data rate 1.5 12 480 mb/s 10 z drv driver output resistance ? ? 28 49.5 40.5 49.5 w 11 usb_r1 usb reference resistor 9.9 10.1 9.9 10.1 9.9 10.1 k w (1) low speed: c l = 200 pf, full speed: c l = 50 pf, high speed: c l = 50 pf (2) t rfm = (t r /t f ) x 100. [excluding the first transaction from the idle state.] (3) for more detailed information, see the universal serial bus specification revision 2.0, chapter 7. electrical. (4) t jr = t px(1) - t px(0) figure 7-63. usb2.0 integrated transceiver interface timing figure 7-64. usb reference resistor routing submit documentation feedback peripheral information and electrical specifications 283 usb_v ssref usb_r1 usb 10k 1% (a) a.placethe10k 1%asclosetothedeviceaspossible. t r t f v crs 90% v oh 10% v ol usb_dn usb_dp t per ? t jr
7.20 ata controller 7.20.1 ata bus master memory map tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the ata peripheral supports the following features: pio, multiword dma, and ultra ata 33/66/100 up to mode 4 timings on pio mode up to mode 2 timings on multiword dma up to mode 5 timings on ultra ata programmable timing parameters supports trueide mode for compact flash the ata controller supports multiword dma transfers between external ide/atapi devices and a system memory bus interface. table 7-90 shows the memory map for the ata dma engine. table 7-90. ata dma master memory map size start address end address ata dma access (bytes) 0x0000 0000 0x0fff ffff 256m reserved 0x1000 0000 0x1000 ffff 64k reserved 0x1001 0000 0x1001 3fff 16k arm ram 0 (data) 0x1001 4000 0x1001 7fff 16k arm ram 1 (data) 0x1001 8000 0x1001 ffff 32k arm rom (data) 0x1002 0000 0x10ff ffff 16256k 0x1100 0000 0x113f ffff 4m 0x1140 0000 0x114f ffff 1m 0x1150 0000 0x115f ffff 1m reserved 0x1160 0000 0x116f ffff 1m 0x1170 0000 0x117f ffff 1m 0x1180 0000 0x1180 ffff 64k 0x1181 0000 0x1181 7fff 32k 0x1181 8000 0x1183 7fff 128k c64x+ l2 ram/cache 0x1183 8000 0x118f ffff 800k reserved 0x1190 0000 0x11df ffff 5m 0x11e0 0000 0x11e0 7fff 32k c64x+ l1p ram/cache 0x11e0 8000 0x11ef ffff 992k reserved 0x11f0 0000 0x11f0 7fff 32k c64x+ l1d ram/cache 0x11f0 8000 0x11ff ffff 992k reserved 0x1200 0000 0x4bff ffff 928m 0x4c00 0000 0x4fff ffff 64m vlynq (remote data) 0x5000 0000 0x7fff ffff 768m reserved 0x8000 0000 0x9fff ffff 512m ddr2 memory controller 0xa000 0000 0xbfff ffff 512m reserved 0xc000 0000 0xffff ffff 1g reserved peripheral information and electrical specifications 284 submit documentation feedback
7.20.2 ata peripheral register description(s) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-91 shows the ata registers. table 7-91. ata register memory map hex address range acronym register name ata bus master interface dma engine registers 0x01c6 6000 bmicp primary ide channel dma control register 0x01c6 6002 bmisp primary ide channel dma status register 0x01c6 6004 bmidtp primary ide channel dma descriptor table pointer register 0x01c6 6008 - 0x01c6 603f ? reserved ata configuration registers 0x01c6 6040 idetimp primary ide channel timing register 0x01c6 6042 - 0x01c6 6046 ? reserved 0x01c6 6047 idestat ide controller status register 0x01c6 6048 udmactl ultra-dma control register 0x01c6 604a ? reserved 0x01c6 6050 miscctl miscellaneous control register 0x01c6 6054 regstb task file register strobe timing register 0x01c6 6058 regrcvr task file register recovery timing register 0x01c6 605c datstb data register access pio strobe timing register 0x01c6 6060 datrcvr data register access pio recovery timing register 0x01c6 6064 dmastb multiword dma strobe timing register 0x01c6 6068 dmarcvr multiword dma recovery timing register 0x01c6 606c udmastb ultra-dma strobe timing register 0x01c6 6070 udmatrp ultra-dma ready-to-pause timing register 0x01c6 6074 udmatenv ultra-dma timing envelope register 0x01c6 6078 iordytmp primary i/o ready timer configuration register 0x01c6 607c - 0x01c6 67ff ? reserved submit documentation feedback peripheral information and electrical specifications 285
7.20.3 ata electrical data/timing 7.20.3.1 ata pio data transfer ac timing tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com all ata ac timing data described in section 7.20.3.1 ? section 7.20.3.3 is provided at the dm6467 device pins. for more details, see section 7.1 , parameter information. the ac timing specifications described in section 7.20.3.1 ? section 7.20.3.3 assume correct configuration of the ata memory-mapped control registers for the selected ata frequency of operation. table 7-92. timings for ata module ? pio data transfer (1) (2) (see figure 7-65 ) -594, -729 no. unit mode min max 1 t 0 cycle time 0-4 (3) (datstb + datrcvr + 2)p -0.5 ns 2 t 1 address valid to diow/ dior setup 0-4 (3) 12p - 1.6 ns 3 t 2 diow/ dior pulse duration low 0-4 (3) (datstb + 1)p - 1 ns 0-2 ? ns 4 t 2i diow/ dior recovery time, pulse duration high 3-4 (3) (datrcvr + 1)p - 1 ns diow data setup time, dd[15:0] valid before 5 t 3 0-4 (3) (datstb + 1)p ns diow rising edge diow data hold time, dd[15:0] valid after diow 6 t 4 0-4 (3) (hwnhld + 1)p + 1 ns rising edge 0 50 ns dior data setup time, dd[15:0] valid before dior 7 t 5 1 35 ns rising edge 2-4 (3) 20 ns dior data hold time, dd[15:0] valid after dior 8 t 6 0-4 (3) 5 ns rising edge output data 3-state, dd[15:0] 3-state after dior 9 t 6z 0-4 (3) 30 ns rising edge 10 t 9 diow/ dior to address valid hold 0-4 (3) (hwnhld + 1)p - 2.1 ns read data setup time, dd[15:0] valid before 11 t rd 0-4 (3) 0 ns iordy active 12 t a iordy setup 0-4 (3) (4) 35 ns 13 t b iordy pulse width 0-4 (3) 1250 ns 14 t c iordy assertion to release 0-4 (3) 5 ns (1) p = sysclk4 period, in ns, for ata. for example, when running the dsp cpu at 594 mhz, use p = 10.1 nsand when running the dsp cpu at 729 mhz, use p = 9.6 ns. (2) datstb equals the value programmed in the datstbxp bit field in the datstb register. datrcvr equals the value programmed in the datrcvrxp bit field in the datrcvr register. hwnhld equals the value programmed in the hwnhldxp bit field in the miscctl register. for more detailed information, see the tms320dm646x dmsoc ata controller user's guide (literature number sprueq3 ). (3) the sustained throughput for pio modes 3 and 4 is limited to the throughput equivalent of pio mode 2. for more detailed information, see the tms320dm646x dmsoc ata controller user's guide (literature number sprueq3 ). (4) the t a parameter must be met only when the iordy timer is enabled to allow a device to insert wait states during a transaction. in order to meet the t a parameter, a minimum frequency for sysclk4 is specified for each pio as follows: pio mode 0, min frequency = 15 mhz pio mode 1, min frequency = 22 mhz pio mode 2, min frequency = 31 mhz pio mode 3, min frequency = 45 mhz pio mode 4, min frequency = 57 mhz peripheral information and electrical specifications 286 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 figure 7-65. ata pio data transfer timing submit documentation feedback peripheral information and electrical specifications 287 da[2:0], ata_cs0 , ata_cs1 t 4 t 0 iordy (a) diow /dior dd[15:0](out) dd[15:0] (in) iordy (b) iordy (c) t 1 t 2 t 9 t 2i t 3 t 6 t 5 t 6z t rd t c t a t c t b a. iordy is not negated for transfer (no wait generated) b. iordy is negative but is re-asserted before t a (no wait is generated) c. iordy is negative before t a and remains asserted until t b ; data is driven valid at t rd (wait is generated)
7.20.3.2 ata multiword dma timing tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-93. timings for ata module ? multiword dma ac timing (1) (2) (see figure 7-66 ) -594, -729 no. unit mode min max 1 t 0 cycle time 0-2 (dmastb + dmarcvr + 2)p - 0.5 ns 2 t d diow/ dior active low pulse duration 0-2 (dmastb + 1)p - 1 ns 0 150 ns dior data access, dior falling edge to dd[15:0] 3 t e 1 60 ns valid 2 50 ns dior data hold time, dd[15:0] valid after dior 4 t f 0-2 5 ns rising edge diow/ dior data setup time, dd[15:0] ( out) valid 0-2 (dmastb)p ns before diow/ dior rising edge 0 100 ns 5 t g diow/ dior data setup time, dd[15:0] ( in) valid 1 30 ns before diow/ dior rising edge 2 20 ns diow data hold time, dd[15:0] valid after diow 6 t h 0-2 (hwnhld + 1)p + 1 ns rising edge 7 t i dmack to diow/ dior setup 0-2 (dmarcvr + 1)p - 1.7 ns 8 t j diow/ dior to dmack hold 0-2 5p - 5.9 ns 9 t kr dior negated pulse width 0-2 (dmarcvr + 1)p - 1 ns 10 t kw diow negated pulse width 0-2 (dmarcvr + 1)p - 1 ns 0 120 ns 11 t lr dior to dmarq delay 1 45 ns 2 35 ns 0-1 40 ns 12 t lw diow to dmarq delay 2 35 ns 13 t m ata_csx valid to diow/ dior setup 0-2 (datrcvr)p - 1.7 ns 14 t n ata_csx valid after diow/ dior rising edge hold 0-2 5p - 1.7 ns 0 20 ns 15 t z dmack to read data (dd[15:0]) released 1-2 25 ns (1) p = sysclk4 period, in ns, for ata. for example, when running the dsp cpu at 594 mhz, use p = 10.1 nsand when running the dsp cpu at 729 mhz, use p = 9.6 ns (2) dmastb equals the value programmed in the dmastbxp bit field in the dmastb register. dmarcvr equals the value programmed in the dmarcvrxp bit field in the dmarcvr register. hwnhld equals the value programmed in the hwnhldxp bit field in the miscctl register. for more detailed information, see the tms320dm646x dmsoc ata controller user's guide (literature number sprueq3 ). peripheral information and electrical specifications 288 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 figure 7-66. ata multiword dma timing submit documentation feedback peripheral information and electrical specifications 289 da[2:0], ata_cs0 , ata_cs1 t m t 0 t n t l t j t z t k t h t f t d t i t g t e t g dmarq dmack diow /dior dd[15:0](out) dd[15:0] (in)
7.20.3.3 ata ultra dma timing tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-94. timings for ata module ? ultra dma ac timing (1) (2) (see figure 7-67 through figure 7-76 ) -594, -729 no. unit mode min max 28 f (sysclk4) operating frequency, sysclk4 0-5 25 mhz 0 240 ns 1 160 ns 2 120 ns 1 t 2cyctyp typical sustained average two cycle time 3 90 ns 4 60 ns 5 40 ns 2 t cyc cycle time, strobe edge to strobe edge 0-5 (udmastb + 1)p ns two cycle time, rising to rising edge or falling to 3 t 2cyc 0-5 2(udmastb + 1)p ns falling edge 0 15 ns 1 10 ns 4 t ds data setup, data valid before strobe edge 2-3 7 ns 4 5 ns 5 4 ns 0-4 5 ns 5 t dh data hold, data valid after strobe edge 5 4.6 ns 0 70 ns 1 48 ns 2 31 ns data valid input setup time, data valid before strobe 3 20 ns 6 t dvs 4 6.7 ns 5 4.8 ns data valid output setup time, data valid before 0-5 (udmastb)p - 3.1 ns strobe 0-4 6.2 ns data valid input hold time, data valid after strobe 5 4.8 ns 7 t dvh data valid output hold time, data valid after 0-5 1p - 2 ns strobe crc word valid setup time at host, crc valid 10 t cvs 0-5 p ns before dmack negation crc word valid hold time at sender, crc valid 11 t cvh 0-5 2p ns after dmack negation 0-4 0 ns time from strobe output released-to-driving 12 t zfs until the first transition of critical timing 5 35 ns (1) p = sysclk4 period, in ns, for ata. for example, when running the dsp cpu at 594 mhz, use p = 10.1 ns and when running the dsp cpu at 729 mhz, use p = 9.6 ns (2) udmastb equals the value programmed in the udmstbxp bit field in the udmastb register. udmatrp equals the value programmed in the udmtrpxp bit field in the udmatrp register. tenv equals the value programmed in the udmatnvxp bit field in the udmatenv register. for more detailed information, see the tms320dm646x dmsoc ata controller user's guide (literature number sprueq3 ). 290 peripheral information and electrical specifications submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-94. timings for ata module ? ultra dma ac timing (see figure 7-67 through figure 7-76 ) (continued) -594, -729 no. unit mode min max 0 70 ns 1 48 ns 2 31 ns time from data output released-to-driving until 13 t dzfs the first transition of critical timing 3 20 ns 4 6.7 ns 5 25 ns 0 230 ns 1 200 ns 2 170 ns 14 t fs first strobe time 3 130 ns 4 120 ns 5 90 ns 0-2 0 150 ns 15 t li limited interlock time 3-4 0 100 ns 5 0 75 ns 16 t mli interlock time with minimum 0-5 20 ns 17 t ui unlimited interlock time 0-5 0 ns maximum time allowed for output drivers to 18 t az 0-5 10 ns release 19 t zah minimum delay time required for output 0-5 20 ns minimum delay time for driver to assert or negate 20 t zad 0-5 0 ns (from released) envelope time, dmack to stop and dmack to 21 t env hdmardy during in-burst initiation and from 0-5 (tenv + 1)p - 0.5 (tenv + 1)p + 1.4 ns dmack to stop during data out burst initiation 0 75 ns 1 70 ns 22 t rfs ready-to-final-strobe time 2-4 60 ns 5 50 ns ready to pause time, (hdmardy ( dior) to 0-5 (udmatrp + 1)p - 0.8 ns stop ( diow)) 0 160 ns 23 t rp 1 125 ns ready to pause time, (ddmardy (iordy) to dmarq) 2-4 100 ns 5 85 ns 24 t iordyz maximum time before releasing iordy 0-5 20 ns 25 t ziordy minimum time before driving iordy 0-5 0 ns setup and hold time for dmack (before 26 t ack 0-5 20 ns assertion or negation) strobe edge to negation of dmarq or 27 t ss assertion of stop (when sender terminates a 0-5 50 ns burst) submit documentation feedback peripheral information and electrical specifications 291
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com a. the definitions for the diow:stop, dior:hdmardy, and iordy:dstrobe signal lines are not in effect until dmarq and dmack are asserted. figure 7-67. ata initiating an ultra dma data-in burst timing a. while dstrobe (iordy) timing is t cyc at the device, it may be different at the host due to propagation delay differences on the cable. figure 7-68. ata sustained ultra dma data-in data transfer timing 292 peripheral information and electrical specifications submit documentation feedback dmarq t dvh t env dstrobe (iordy) (a) st op (diow ) (a) hdmardy (dior ) (a) dd[15:0] da[2:0], ata_cs0 , ata_cs1 t fs t env t zfs t dzfs t dvs t zad t zad t fs t ui t ack t ack t ziordy t az t ack dmack t 2cyc t dh t ds t dh t ds t dh dstrobe (iordy) dd[15:0] t cyc (a) t cyc (a)
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 figure 7-69. ata host pausing an ultra dma data-in burst timing figure 7-70. ata device terminating an ultra dma data-in burst timing submit documentation feedback peripheral information and electrical specifications 293 dmarq t mli dstrobe (iordy) st op (diow ) hdmardy (dior ) dd[15:0] dmack da[2:0], ata_cs0 , ata_cs1 t ack t ack t iordyz t cvh t cvs crc t ack t zah t az t li t li t li t ss dmarq t rp dstrobe (iordy) st op (diow ) hdmardy (dior ) dd[15:0] dmack t rfs
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com figure 7-71. ata host terminating an ultra dma data-in burst timing a. the definitions for the diow:stop, iordy:ddmardy, and dior:hstrobe signal lines are not in effect until dmarq and dmack are asserted. figure 7-72. ata initiating an ultra dma data-out burst timing peripheral information and electrical specifications 294 submit documentation feedback dmarq dstrobe (iordy) st op (diow ) hdmardy (dior ) dd[15:0] dmack da[2:0], ata_cs0 , ata_cs1 t cvh t li crc t iordyz t az t mli t zah t ack t ack t li t rp t rfs t ack t cvs t mli dmarq hstrobe (dior ) (a) st op (diow ) (a) ddmardy (iordy) (a) dd[15:0] dmack da[2:0], ata_cs0 , ata_cs1 t ui t ziordy t env t ack t ack t ack t dzfs t li t ui t dvs t dvh
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 a. while hstrobe ( dior) timing is t cyc at the host, it may be different at the device due to propagation delay differences on the cable. figure 7-73. ata sustained ultra dma data-out transfer timing figure 7-74. ata device pausing an ultra dma data-out burst timing submit documentation feedback peripheral information and electrical specifications 295 hstrobe (dior ) dd[15:0] (out) t 2cyc t cyc (a) t cyc (a) t 2cyc t dvh t dvs t dvh t dvs t dvh dmarq dmack t rfs t rp st op (diow ) ddmardy (iordy) hstrobe (dior ) dd[15:0]
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com figure 7-75. ata host terminating an ultra dma data-out burst timing figure 7-76. ata device terminating an ultra dma data-out burst timing peripheral information and electrical specifications 296 submit documentation feedback dmarq dmack t li st op (diow ) ddmardy (iordy) hstrobe (dior ) dd[15:0] t li t li t ss t mli t ack t iordyz t ack t cvs t cvh crc da[2:0], ata_cs0 , a ta_cs1 t ack dmarq dmack st op (diow ) ddmardy (iordy) hstrobe (dior ) dd[15:0] t mli da[2:0], ata_cs0 , ata_cs1 t li t rp t rfs t li t mli t cvs t iordyz t ack t ack t ack t cvh crc
7.20.3.4 ata hddir timing tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 figure 7-77 through figure 7-80 show the behavior of hddir for the different types of transfers. table 7-95. timing requirements for hddir (1) -594, -729 no. unit min max 1 t c cycle time, ata_cs[1:0] to hddir low e - 3.1 ns (1) e = ata clock cycle figure 7-77. ata hddir taskfile write/single pio write timing figure 7-78. ata hddir pio postwrite start timing submit documentation feedback peripheral information and electrical specifications 297 da[2:0], ata_cs0 , ata_cs1 hddir diow dd[15:0] (out) t c (a) t c (a) a. t c one cycle da[2:0], ata_cs0 , ata_cs1 t c (a) hddir diow dd[15:0] (out) t c (a) a. t c one cycle
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com figure 7-79. ata hddir multiword dma write transfer timing figure 7-80. ata hddir ultra dma write transfer timing 298 peripheral information and electrical specifications submit documentation feedback da[2:0], ata_cs0 , ata_cs1 hddir diow dd[15:0] (out) dmack crc t c (a) a. t c one cycle da[2:0], ata_cs0 , ata_cs1 t c (a) hddir diow dd[15:0] (out) dmack t c (a) a. t c one cycle
7.21 vlynq 7.21.1 vlynq bus master memory map tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the dm6467 vlynq peripheral provides a high speed serial communications interface with the following features. low pin count scalable performance/support simple packet based transfer protocol for memory mapped access ? write request/data packet ? read request packet ? read response data packet ? interrupt request packet supports both symmetric and asymmetric operation ? tx pins on first device connect to rx pins on second device and vice versa ? data pin widths are automatically detected after reset ? request packets, response packets, and flow control information are all multiplexed and sent across the same physical pins ? supports both host/peripheral and peer-to-peer communication simple block code packet formatting (8-bit/10-bit) in band flow control ? no extra pins needed ? allows receiver to momentarily throttle back transmitter when overflow is about to occur ? uses built in special code capability of block code to seamlessly interleave flow control information with user data ? allows system designer to balance cost of data buffering versus performance multiple outstanding transactions automatic packet formatting optimizations internal loop-back mode the vlynq peripheral includes a bus master interface that allows external device initiated transfers to access the dm6467 system bus. table 7-96 shows the memory map for the vlynq master interface. table 7-96. vlynq master memory map size start address end address hpi access (bytes) 0x0000 0000 0x01bf ffff 28m reserved 0x01c0 0000 0x0fff ffff 228m cfg bus peripherals 0x1000 0000 0x1000 ffff 64k reserved 0x1001 0000 0x1001 3fff 16k arm ram 0 (data) 0x1001 4000 0x1001 7fff 16k arm ram 1 (data) 0x1001 8000 0x1001 ffff 32k arm rom (data) submit documentation feedback peripheral information and electrical specifications 299
7.21.2 vlynq peripheral register description(s) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-96. vlynq master memory map (continued) size start address end address hpi access (bytes) 0x1002 0000 0x10ff ffff 16256k 0x1100 0000 0x113f ffff 4m 0x1140 0000 0x114f ffff 1m 0x1150 0000 0x115f ffff 1m reserved 0x1160 0000 0x116f ffff 1m 0x1170 0000 0x117f ffff 1m 0x1180 0000 0x1180 ffff 64k 0x1181 0000 0x1181 7fff 32k 0x1181 8000 0x1183 7fff 128k c64x+ l2 ram/cache 0x1183 8000 0x118f ffff 800k reserved 0x1190 0000 0x11df ffff 5m 0x11e0 0000 0x11e0 7fff 32k c64x+ l1p ram/cache 0x11e0 8000 0x11ef ffff 992k reserved 0x11f0 0000 0x11f0 7fff 32k c64x+ l1d ram/cache 0x11f0 8000 0x11ff ffff 992k reserved 0x1200 0000 0x41ff ffff 768m 0x4200 0000 0x43ff ffff 32m emifa data ( cs2) 0x4400 0000 0x45ff ffff 32m emifa data ( cs3) 0x4600 0000 0x47ff ffff 32m emifa data ( cs4) 0x4800 0000 0x49ff ffff 32m emifa data ( cs5) 0x4a00 0000 0x7fff ffff 864m reserved 0x8000 0000 0x9fff ffff 512m ddr2 memory controller 0xa000 0000 0xbfff ffff 512m reserved 0xc000 0000 0xffff ffff 1g reserved table 7-97. vlynq registers hex address range acronym register name 0x2001 0000 revid vlynq revision register 0x2001 0004 ctrl vlynq local control register 0x2001 0008 stat vlynq local status register 0x2001 000c intpri vlynq local interrupt priority vector status/clear register 0x2001 0010 intstatclr vlynq local unmasked interrupt status/clear register 0x2001 0014 intpendset vlynq local interrupt pending/set register 0x2001 0018 intptr vlynq local interrupt pointer register 0x2001 001c xam vlynq local transmit address map register 0x2001 0020 rams1 vlynq local receive address map size 1 register 0x2001 0024 ramo1 vlynq local receive address map offset 1 register 0x2001 0028 rams2 vlynq local receive address map size 2 register 0x2001 002c ramo2 vlynq local receive address map offset 2 register 0x2001 0030 rams3 vlynq local receive address map size 3 register 0x2001 0034 ramo3 vlynq local receive address map offset 3 register 0x2001 0038 rams4 vlynq local receive address map size 4 register 0x2001 003c ramo4 vlynq local receive address map offset 4 register 0x2001 0040 chipver vlynq local chip version register peripheral information and electrical specifications 300 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-97. vlynq registers (continued) hex address range acronym register name 0x2001 0044 autngo vlynq local auto negotiation register 0x2001 0048 ? reserved 0x2001 004c ? reserved 0x2001 0050 - 0x2001 005c ? reserved 0x2001 0060 ? reserved 0x2001 0064 ? reserved 0x2001 0068 - 0x2001 007c ? reserved for future use 0x2001 0080 rrevid vlynq remote revision register 0x2001 0084 rctrl vlynq remote control register 0x2001 0088 rstat vlynq remote status register 0x2001 008c rintpri vlynq remote interrupt priority vector status/clear register 0x2001 0090 rintstatclr vlynq remote unmasked interrupt status/clear register 0x2001 0094 rintpendset vlynq remote interrupt pending/set register 0x2001 0098 rintptr vlynq remote interrupt pointer register 0x2001 009c rxam vlynq remote transmit address map register 0x2001 00a0 rrams1 vlynq remote receive address map size 1 register 0x2001 00a4 rramo1 vlynq remote receive address map offset 1 register 0x2001 00a8 rrams2 vlynq remote receive address map size 2 register 0x2001 00ac rramo2 vlynq remote receive address map offset 2 register 0x2001 00b0 rrams3 vlynq remote receive address map size 3 register 0x2001 00b4 rramo3 vlynq remote receive address map offset 3 register 0x2001 00b8 rrams4 vlynq remote receive address map size 4 register 0x2001 00bc rramo4 vlynq remote receive address map offset 4 register vlynq remote chip version register (values on the device_id and 0x2001 00c0 rchipver device_rev pins of remote vlynq) 0x2001 00c4 rautngo vlynq remote auto negotiation register 0x2001 00c8 rmanngo vlynq remote manual negotiation register 0x2001 00cc rngostat vlynq remote negotiation status register 0x2001 00d0 - 0x2001 00dc ? reserved vlynq remote interrupt vectors 3 - 0 (sourced from vlynq_int_i[3:0] port of 0x2001 00e0 rintvec0 remote vlynq) vlynq remote interrupt vectors 7 - 4 (sourced from vlynq_int_i[7:4] port of 0x2001 00e4 rintvec1 remote vlynq) 0x2001 00e8 - 0x2001 00fc ? reserved for future use 0x2001 0100 - 0x2001 0fff ? reserved vlynq remote devices 64 mb remote data region. translated into one of four mapped registers on 0x4c00 0000 - 0x4fff ffff vlynqremote the remote device. submit documentation feedback peripheral information and electrical specifications 301
7.21.3 vlynq electrical data/timing tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-98. timing requirements for vlynq_clock input (see figure 7-81 ) -594 -729 no. unit min max min max 1 t c(vclk) cycle time, vlynq_clock 10 9.6 ns 2 t w(vclkh) pulse duration, vlynq_clock high 3 3 ns 3 t w(vclkl) pulse duration, vlynq_clk low 3 3 ns 4 t t(vclk) transition time, vlynq_clock 3 3 ns table 7-99. switching characteristics over recommended operating conditions for vlynq_clock output (see figure 7-81 ) -594 -729 no parameter unit . min max min max 1 t c(vclk) cycle time, vlynq_clock 10 9.6 ns 2 t w(vclkh) pulse duration, vlynq_clock high 4 4 ns 3 t w(vclkl) pulse duration, vlynq_clock low 4 4 ns 4 t t(vclk) transition time, vlynq_clock 3 3 ns figure 7-81. vlynq_clock timing for vlynq table 7-100. switching characteristics over recommended operating conditions for transmit data for the vlynq module (see figure 7-82 ) -594, -729 no parameter fast mode slow mode unit . min max min max t d(vclkh- 1 delay time, vlynq_clock high to vlynq_txd[3:0] invalid 1 2.21 ns txdi) t d(vclkh- 2 delay time, vlynq_clock high to vlynq_txd[3:0] valid 7.14 8.5 ns txdv) peripheral information and electrical specifications 302 submit documentation feedback vlynq_clock 3 1 2 4 4
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-101. timing requirements for receive data for the vlynq module (1) (see figure 7-82 ) -594, -729 no. unit min max rtm disabled, rtm sample = 3 0.2 ns setup time, vlynq_rxd[3:0] valid before 3 t su(rxdv-vclkh) vlynq_clock high rtm enabled (1) ns rtm disabled, rtm sample = 3 2 ns hold time, vlynq_rxd[3:0] valid after 4 t h(vclkh-rxdv) vlynq_clock high rtm enabled (1) ns (1) the vlynq receive timing manager (rtm) is a serial receive logic designed to eliminate setup and hold violations that could occur in traditional input signals. rtm logic automatically selects the setup and hold timing from one of eight data flops (see table 7-102 ). when rtm logic is disabled, the setup and hold timing from the default data flop (3) is used. table 7-102. rtm rx data flop hold/setup timing constraints rx data flop hold (y) setup (x) 0 0.62 1.3 1 1.43 0.8 2 1.66 0.4 3 2.12 0.2 4 2.5 0 5 3.18 -0.3 6 3.87 -0.5 7 4.25 -0.7 figure 7-82. vlynq transmit/receive timing submit documentation feedback peripheral information and electrical specifications 303 vlynq_clock vlynq_txd[3:0] vlynq_rxd[3:0] 1 2 3 4 datadata
7.22 multichannel audio serial port (mcasp0/1) peripherals 7.22.1 mcasp device-specific information tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the multichannel audio serial port (mcasp) functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. the mcasp is useful for time-division multiplexed (tdm) stream, inter-integrated sound (i2s) protocols, and intercomponent digital audio interface transmission (dit). the dm6467 device includes two multichannel audio serial port (mcasp) interface peripherals (mcasp0 and mcasp1). the mcasp0 module consists of a transmit and receive section. these sections can operate completely independently with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit and receive sections may be synchronized. the mcasp0 module also includes a pool of 4 shift registers that may be configured to operate as either transmit data or receive data. the transmit section of the mcasp0 can transmit data in either a time-division-multiplexed (tdm) synchronous serial format or in a digital audio interface (dit) format where the bit stream is encoded for s/pdif, aes-3, iec-60958, cp-430 transmission. the receive section of the mcasp0 peripheral supports the tdm synchronous serial format. the mcasp0 module can support one transmit data format (either a tdm format or dit format) and one receive format at a time. all transmit shift registers use the same format and all receive shift registers use the same format. however, the transmit and receive formats need not be the same. both the transmit and receive sections of the mcasp also support burst mode which is useful for non-audio data (for example, passing control information between two dsps). the mcasp0 peripheral has additional capability for flexible clock generation, and error detection/handling, as well as error management. the dm6467 mcasp1 module is a reduced feature version of the mcasp peripheral. the mcasp1 module provides a single transmit-only shift register and can transmit data in dit format only. for more detailed information on and the functionality of the mcasp peripheral, see the tms320dm646x dmsoc multichannel audio serial port (mcasp) user's guide (literature number spruer1 ). 304 peripheral information and electrical specifications submit documentation feedback
7.22.2 mcasp0 and mcasp1 peripheral register description(s) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-103. mcasp0 control registers hex address range acronym register name 01d0 1000 pid peripheral identification register [register value: 0x0010 0101] 01d0 1004 ? reserved 01d0 1008 ? reserved 01d0 100c ? reserved 01d0 1010 pfunc pin function register 01d0 1014 pdir pin direction register 01d0 1018 ? reserved 01d0 101c ? reserved 01d0 1020 ? reserved 01d0 1024 ? 01d0 1040 ? reserved 01d0 1044 gblctl global control register 01d0 1048 amute mute control register 01d0 104c dlbctl digital loop-back control register 01d0 1050 ditctl dit mode control register 01d0 1054 ? 01d0 105c ? reserved alias of gblctl containing only receiver reset bits, allows transmit to be reset 01d0 1060 rgblctl independently from receive. 01d0 1064 rmask receiver format unit bit mask register 01d0 1068 rfmt receive bit stream format register 01d0 106c afsrctl receive frame sync control register 01d0 1070 aclkrctl receive clock control register 01d0 1074 ahclkrctl high-frequency receive clock control register 01d0 1078 rtdm receive tdm slot 0?31 register 01d0 107c rintctl receiver interrupt control register 01d0 1080 rstat status register ? receiver 01d0 1084 rslot current receive tdm slot register 01d0 1088 rclkchk receiver clock check control register 01d0 108c revtctl receiver dma event control register 01d0 1090 ? 01d0 109c ? reserved alias of gblctl containing only transmitter reset bits, allows transmit to be reset 01d0 10a0 xgblctl independently from receive. 01d0 10a4 xmask transmit format unit bit mask register 01d0 10a8 xfmt transmit bit stream format register 01d0 10ac afsxctl transmit frame sync control register 01d0 10b0 aclkxctl transmit clock control register 01d0 10b4 ahclkxctl high-frequency transmit clock control register 01d0 10b8 xtdm transmit tdm slot 0?31 register 01d0 10bc xintctl transmit interrupt control register 01d0 10c0 xstat status register ? transmitter 01d0 10c4 xslot current transmit tdm slot 01d0 10c8 xclkchk transmit clock check control register 01d0 10cc xevtctl transmit dma event control register submit documentation feedback peripheral information and electrical specifications 305
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-103. mcasp0 control registers (continued) hex address range acronym register name 01d0 10d0 ? 01d0 10fc ? reserved 01d0 1100 ditcsra0 left (even tdm slot) channel status register file 01d0 1104 ditcsra1 left (even tdm slot) channel status register file 01d0 1108 ditcsra2 left (even tdm slot) channel status register file 01d0 110c ditcsra3 left (even tdm slot) channel status register file 01d0 1110 ditcsra4 left (even tdm slot) channel status register file 01d0 1114 ditcsra5 left (even tdm slot) channel status register file 01d0 1118 ditcsrb0 right (odd tdm slot) channel status register file 01d0 111c ditcsrb1 right (odd tdm slot) channel status register file 01d0 1120 ditcsrb2 right (odd tdm slot) channel status register file 01d0 1124 ditcsrb3 right (odd tdm slot) channel status register file 01d0 1128 ditcsrb4 right (odd tdm slot) channel status register file 01d0 112c ditcsrb5 right (odd tdm slot) channel status register file 01d0 1130 ditudra0 left (even tdm slot) user data register file 01d0 1134 ditudra1 left (even tdm slot) user data register file 01d0 1138 ditudra2 left (even tdm slot) user data register file 01d0 113c ditudra3 left (even tdm slot) user data register file 01d0 1140 ditudra4 left (even tdm slot) user data register file 01d0 1144 ditudra5 left (even tdm slot) user data register file 01d0 1148 ditudrb0 right (odd tdm slot) user data register file 01d0 114c ditudrb1 right (odd tdm slot) user data register file 01d0 1150 ditudrb2 right (odd tdm slot) user data register file 01d0 1154 ditudrb3 right (odd tdm slot) user data register file 01d0 1158 ditudrb4 right (odd tdm slot) user data register file 01d0 115c ditudrb5 right (odd tdm slot) user data register file 01d0 1160 ? 01d0 117c ? reserved 01d0 1180 srctl0 serializer 0 control register 01d0 1184 srctl1 serializer 1 control register 01d0 1188 srctl2 serializer 2 control register 01d0 118c srctl3 serializer 3 control register 01d0 1190 ? 01d0 11fc ? reserved 01d0 1200 xbuf0 transmit buffer for serializer 0 01d0 1204 xbuf1 transmit buffer for serializer 1 01d0 1208 xbuf2 transmit buffer for serializer 2 01d0 120c xbuf3 transmit buffer for serializer 3 01d0 1210 ? 01d0 127c ? reserved 01d0 1280 rbuf0 receive buffer for serializer 0 01d0 1284 rbuf1 receive buffer for serializer 1 01d0 1288 rbuf2 receive buffer for serializer 2 01d0 128c rbuf3 receive buffer for serializer 3 01d0 1290 ? 01d0 13ff ? reserved 306 peripheral information and electrical specifications submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-104. mcasp0 data registers hex address range acronym register name comments (used when rsel or xsel mcasp0 receive buffers or mcasp0 transmit buffers via bits = 0 [these bits are located 01d0 1400 ? 01d0 17ff rbuf0/xbuf0 the peripheral data bus. in the rfmt or xfmt registers, respectively].) submit documentation feedback peripheral information and electrical specifications 307
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-105. mcasp1 control registers hex address range acronym register name 01d0 1800 pid peripheral identification register [register value: 0x0010 0101] 01d0 1804 ? reserved 01d0 1808 ? reserved 01d0 180c ? reserved 01d0 1810 pfunc pin function register 01d0 1814 pdir pin direction register 01d0 1818 ? reserved 01d0 181c ? reserved 01d0 1820 ? reserved 01d0 1824 ? 01d0 1843 ? reserved 01d0 1844 gblctl global control register 01d0 1848 ? reserved 01d0 184c dlbctl digital loop-back control register 01d0 1850 ditctl dit mode control register 01d0 1854 ? 01d0 185f ? reserved alias of gblctl containing only receiver reset bits, allows transmit to be reset 01d0 1860 rgblctl independently from receive. 01d0 1864 ? reserved 01d0 1868 ? reserved 01d0 186c ? reserved 01d0 1870 ? reserved 01d0 1874 ? reserved 01d0 1878 ? reserved 01d0 187c rintctl receiver interrupt control register 01d0 1880 rstat status register ? receiver 01d0 1884 ? 01d0 1888 ? 01d0 188c ? 01d0 1890 ? 01d0 189f ? reserved alias of gblctl containing only transmitter reset bits, allows transmit to be reset 01d0 18a0 xgblctl independently from receive. 01d0 18a4 xmask transmit format unit bit mask register 01d0 18a8 xfmt transmit bit stream format register 01d0 18ac afsxctl transmit frame sync control register 01d0 18b0 aclkxctl transmit clock control register 01d0 18b4 ahclkxctl high-frequency transmit clock control register 01d0 18b8 xtdm transmit tdm slot 0?31 register 01d0 18bc xintctl transmit interrupt control register 01d0 18c0 xstat status register ? transmitter 01d0 18c4 xslot current transmit tdm slot 01d0 18c8 xclkchk transmit clock check control register 01d0 18cc xevtctl transmit dma event control register 308 peripheral information and electrical specifications submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-105. mcasp1 control registers (continued) hex address range acronym register name 01d0 18d0 ? 01d0 18ff ? reserved 01d0 1900 ditcsra0 left (even tdm slot) channel status register file 01d0 1904 ditcsra1 left (even tdm slot) channel status register file 01d0 1908 ditcsra2 left (even tdm slot) channel status register file 01d0 190c ditcsra3 left (even tdm slot) channel status register file 01d0 1910 ditcsra4 left (even tdm slot) channel status register file 01d0 1914 ditcsra5 left (even tdm slot) channel status register file 01d0 1918 ditcsrb0 right (odd tdm slot) channel status register file 01d0 191c ditcsrb1 right (odd tdm slot) channel status register file 01d0 1920 ditcsrb2 right (odd tdm slot) channel status register file 01d0 1924 ditcsrb3 right (odd tdm slot) channel status register file 01d0 1928 ditcsrb4 right (odd tdm slot) channel status register file 01d0 192c ditcsrb5 right (odd tdm slot) channel status register file 01d0 1930 ditudra0 left (even tdm slot) user data register file 01d0 1934 ditudra1 left (even tdm slot) user data register file 01d0 1938 ditudra2 left (even tdm slot) user data register file 01d0 193c ditudra3 left (even tdm slot) user data register file 01d0 1940 ditudra4 left (even tdm slot) user data register file 01d0 1944 ditudra5 left (even tdm slot) user data register file 01d0 1948 ditudrb0 right (odd tdm slot) user data register file 01d0 194c ditudrb1 right (odd tdm slot) user data register file 01d0 1950 ditudrb2 right (odd tdm slot) user data register file 01d0 1954 ditudrb3 right (odd tdm slot) user data register file 01d0 1958 ditudrb4 right (odd tdm slot) user data register file 01d0 195c ditudrb5 right (odd tdm slot) user data register file 01d0 1960 ? 01d0 197f ? reserved 01d0 1980 srctl0 serializer 0 control register 01d0 1984 ? 01d0 19ff ? reserved 01d0 1a00 xbuf0 transmit buffer for serializer 0 01d0 1a04 ? 01d0 13ff ? reserved table 7-106. mcasp1 data registers hex address range acronym register name comments (used when xsel bits = 0 01d0 1c00 ? 01d0 1fff xbuf1 mcasp1 transmit buffers via the peripheral data bus. [these bits are located in the xfmt register].) submit documentation feedback peripheral information and electrical specifications 309
7.22.3 mcasp0 and mcasp1 electrical data/timing 7.22.3.1 multichannel audio serial port (mcasp0) timing tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-107. timing requirements for mcasp0 (see figure 7-83 and figure 7-84 ) (1) -594, -729 no. unit min max 1 t c(ahckrx) cycle time, ahclkr/x 20.8 ns 2 t w(ahckrx) pulse duration, ahclkr/x high or low 8.3 ns 3 t c(ckrx) cycle time, aclkr/x aclkr/x ext 37 ns 4 t w(ckrx) pulse duration, aclkr/x high or low aclkr/x ext 15 ns aclkr/x int 15 ns 5 t su(frx-ckrx) setup time, afsr/x input valid before aclkr/x latches data aclkr/x ext 3 ns aclkr/x int 0 ns 6 t h(ckrx-frx) hold time, afsr/x input valid after aclkr/x latches data aclkr/x ext 3 ns aclkr int 15 ns 7 t su(axr-ckrx) setup time, axr input valid before aclkr/x latches data aclkx int 14 ns aclkr/x ext 3 ns aclkr/x int 3 ns 8 t h(ckrx-axr) hold time, axr input valid after aclkr/x latches data aclkr/x ext 3 ns (1) aclkx internal: aclkxctl.clkxm=1, pdir.aclkx = 1 aclkx external input: aclkxctl.clkxm=0, pdir.aclkx=0 aclkx external output: aclkxctl.clkxm=0, pdir.aclkx=1 aclkr internal: aclkrctl.clkrm=1, pdir.aclkr = 1 aclkr external input: aclkrctl.clkrm=0, pdir.aclkr=0 aclkr external output: aclkrctl.clkrm=0, pdir.aclkr=1 peripheral information and electrical specifications 310 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-108. switching characteristics over recommended operating conditions for mcasp0 (1) (2) (3) (see figure 7-83 and figure 7-84 ) -594, -729 no. parameter unit min max 9 t c(ahckrx) cycle time, ahclkr/x 41.7 ns 10 t w(ahckrx) pulse duration, ahclkr/x high or low ah - 2.5 ns 11 t c(ckrx) cycle time, aclkr/x aclkr/x int 41.7 ns 12 t w(ckrx) pulse duration, aclkr/x high or low aclkr/x int a - 2.5 ns aclkr int -2 5 ns aclkx int -1 5 ns 13 t d(ckrx-frx) delay time, aclkr/x transmit edge to afsx/r output valid aclkr ext 0 15 ns aclkx ext 0 16 ns aclkx int -2 5 ns 14 t d(ckx-axrv) delay time, aclkx transmit edge to axr output valid aclkx ext 0 16 ns aclkr/x int -3 8 ns disable time, axr high impedance following last data bit 15 t dis(ckrx-axrhz) from aclkr/x transmit edge aclkr/x ext -3 15 ns (1) a = (aclkr/x period)/2 in ns. for example, when aclkr/x period is 25 ns, use a = 12.5 ns. (2) ah = (ahclkr/x period)/2 in ns. for example, when ahclkr/x period is 25 ns, use ah = 12.5 ns. (3) aclkx internal: aclkxctl.clkxm=1, pdir.aclkx = 1 aclkx external input: aclkxctl.clkxm=0, pdir.aclkx=0 aclkx external output: aclkxctl.clkxm=0, pdir.aclkx=1 aclkr internal: aclkrctl.clkrm=1, pdir.aclkr = 1 aclkr external input: aclkrctl.clkrm=0, pdir.aclkr=0 aclkr external output: aclkrctl.clkrm=0, pdir.aclkr=1 submit documentation feedback peripheral information and electrical specifications 311
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com a. for clkrp = clkxp = 0, the mcasp transmitter is configured for rising edge (to shift data out) and the mcasp receiver is configured for falling edge (to shift data in). b. for clkrp = clkxp = 1, the mcasp transmitter is configured for falling edge (to shift data out) and the mcasp receiver is configured for rising edge (to shift data in). figure 7-83. mcasp0 and mcasp1 input timings 312 peripheral information and electrical specifications submit documentation feedback 8 7 4 4 3 2 2 1 a0 a1 b0 b1 a30 a31 b30 b31 c0 c1 c2 c3 c31 ahclkr/x (falling edge polarity) ahclkr/x (rising edge polarity) afsr/x (bit width, 0 bit delay)afsr/x (bit width, 1 bit delay) afsr/x (bit width, 2 bit delay) afsr/x (slot width, 0 bit delay)afsr/x (slot width, 1 bit delay) afsr/x (slot width, 2 bit delay) axr[n] (data in/receive) 6 5 aclkr/x (clkrp = clkxp = 0) (a) aclkr/x (clkrp = clkxp = 1) (b)
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 a. for clkrp = clkxp = 1, the mcasp transmitter is configured for falling edge (to shift data out) and the mcasp receiver is configured for rising edge (to shift data in). b. for clkrp = clkxp = 0, the mcasp transmitter is configured for rising edge (to shift data out) and the mcasp receiver is configured for falling edge (to shift data in). figure 7-84. mcasp0 and mcasp1 output timings submit documentation feedback peripheral information and electrical specifications 313 15 14 13 13 13 13 13 13 13 12 12 11 10 10 9 a0 a1 b0 b1 a30 a31 b30 b31 c0 c1 c2 c3 c31 ahclkr/x (falling edge polarity) ahclkr/x (rising edge polarity) afsr/x (bit width, 0 bit delay) afsr/x (bit width, 1 bit delay) afsr/x (bit width, 2 bit delay) afsr/x (slot width, 0 bit delay) afsr/x (slot width, 1 bit delay) afsr/x (slot width, 2 bit delay) axr[n] (data out/t ransmit) aclkr/x (clkrp = clkxp = 0) (b) aclkr/x (clkrp = clkxp = 1) (a)
7.22.3.2 multichannel audio serial port (mcasp1) dit timing tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-109. timing requirements for mcasp1 (see figure 7-83 and figure 7-84 ) (1) -594, -729 no. unit min max 1 t c(ahckrx) cycle time, ahclkx 20.8 ns 2 t w(ahckrx) pulse duration, ahclkx high or low 8.3 ns 3 t c(ckrx) cycle time, aclkx aclkx ext 37 ns 4 t w(ckrx) pulse duration, aclkx high or low aclkx ext 15 ns (1) aclkx internal: aclkxctl.clkxm=1, pdir.aclkx = 1 aclkx external input: aclkxctl.clkxm=0, pdir.aclkx=0 aclkx external output: aclkxctl.clkxm=0, pdir.aclkx=1 peripheral information and electrical specifications 314 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-110. switching characteristics over recommended operating conditions for mcasp1 (1) (2) (3) (see figure 7-83 and figure 7-84 ) -594, -729 no. parameter unit min max 9 t c(ahckrx) cycle time, ahclkx 41.7 ns 10 t w(ahckrx) pulse duration, ahclkx high or low ah - 2.5 ns 11 t c(ckrx) cycle time, aclkx 41.7 ns 12 t w(ckrx) pulse duration, aclkx high or low aclkr/x int a - 2.5 ns aclkx int -1 5 ns 14 t d(ckx-axrv) delay time, aclkx transmit edge to axr output valid aclkx ext 0 16 ns aclkx int -3 8 ns disable time, axr high impedance following last data bit 15 t dis(ckrx-axrhz) from aclkx transmit edge aclkx ext -3 15 ns (1) a = (aclkx period)/2 in ns. for example, when aclkx period is 25 ns, use a = 12.5 ns. (2) ah = (ahclkx period)/2 in ns. for example, when ahclkx period is 25 ns, use ah = 12.5 ns. (3) aclkx internal: aclkxctl.clkxm=1, pdir.aclkx = 1 aclkx external input: aclkxctl.clkxm=0, pdir.aclkx=0 aclkx external output: aclkxctl.clkxm=0, pdir.aclkx=1 submit documentation feedback peripheral information and electrical specifications 315
7.23 serial peripheral interface (spi) 7.23.1 spi device-specific information 7.23.2 spi peripheral register description(s) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the spi is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (2-to-16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. the spi is normally used for communication between the tms320dm646x dmsoc and external peripherals. typical applications inlcude a interface to external i/o or peripheral expansion via devices such as shift regisers, display drivers, spi eeproms, and analog-to-digital converters (adcs). the dm6467 spi supports the following features: master/slave operation 2 chip selects for interfacing/control to multiple spi slave devices 3-, 4-, 5-wire interface [the dm6467 supports 3-pin mode, 2 4-pin modes, and the 5-pin mode.] 16-bit shift register receive buffer register 8-bit clock prescaler programmable spi clock frequency range, character length, and clock phase and polarity table 7-111 shows the spi registers. table 7-111. spi registers hex address range acronym register name 01c6 6800 spigcr0 spi global control register 0 01c6 6804 spigcr1 spi global control register 1 01c6 5808 spiint spi interrupt register 01c6 680c spiilvl spi interrupt level register 01c6 6810 spiflg spi flag status register 01c6 6814 spipc0 spi pin control register 0 01c6 6818 ? reserved 01c6 681c spipc2 spi pin control register 2 01c6 6820 ? 01c6 6838 ? reserved 01c6 683c spidat1 spi shift register 1 01c6 6840 spibuf spi buffer register 01c6 6844 spiemu spi emulation register 01c6 6848 spidelay spi delay register 01c6 684c spidef spi default chip select register 01c6 6850 spifmt0 spi data format register 0 01c6 6854 spifmt1 spi data format register 1 01c6 6858 spifmt2 spi data format register 2 01c6 685c spifmt3 spi data format register 3 01c6 6860 intvec0 spi interrupt vector register 0 01c6 6864 intvec1 spi interrupt vector register 1 01c6 6868 ? 01c6 6fff ? reserved peripheral information and electrical specifications 316 submit documentation feedback
7.23.3 spi electrical data/timing tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 master mode ? general table 7-112. general switching characteristics in master mode (1) no. parameter min max unit 1 t c(clk) cycle time, spi_clk 2p ns 2 t w(clkh) pulse width, spi_clk high p ns 3 t w(clkl) pulse width, spi_clk low p ns output setup time, spi_simo valid (1st bit) before initial spi_clk rising edge, 3-/4-/5-pin mode, 2p polarity = 0, phase = 0 output setup time, spi_simo valid (1st bit) before initial spi_clk rising edge, 3-/4-/5-pin mode, 0.5t + 2p polarity = 0, phase = 1 4 t osu(simo-clk) ns output setup time, spi_simo valid (1st bit) before initial spi_clk falling edge, 3-/4-/5-pin mode, 2p polarity = 1, phase = 0 output setup time, spi_simo valid (1st bit) before initial spi_clk falling edge, 3-/4-/5-pin mode, 0.5t + 2p polarity = 1, phase = 1 delay time, spi_clk transmit rising edge to spi_simo output valid 5 (subsequent bit driven), 3-/4-/5-pin mode, polarity = 0, phase = 0 delay time, spi_clk transmit falling edge to spi_simo output valid (subsequent bit driven), 3-/4-/5-pin mode, polarity = 0, phase 5 = 1 5 t d(clk-simo) ns delay time, spi_clk transmit falling edge to spi_simo output valid (subsequent bit driven), 3-/4-/5-pin mode, polarity = 1, phase 5 = 0 delay time, spi_clk transmit rising edge to spi_simo output valid 5 (subsequent bit driven), 3-/4-/5-pin mode, polarity = 1, phase = 1 output hold time, spi_simo valid (except final bit) after receive falling edge of spi_clk, 0.5t ? 4 3-/4-/5-pin mode, polarity = 0, phase = 0 output hold time, spi_simo valid (except final bit) after receive rising edge of spi_clk, 0.5t ? 4 3-/4-/5-pin mode, polarity = 0, phase = 1 6 t oh(clk-simo) ns output hold time, spi_simo valid (except final bit) after receive rising edge of spi_clk, 0.5t ? 4 3-/4-/5-pin mode, polarity = 1, phase = 0 output hold time, spi_simo valid (except final bit) after receive falling edge of spi_clk, 0.5t ? 4 3-/4-/5-pin mode, polarity = 1, phase = 1 (1) t = period of spi_clk; p = period of spi core clock submit documentation feedback peripheral information and electrical specifications 317
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-113. general input timing requirements in master mode no. min max unit setup time, spi_somi valid before receive falling edge of spi_clk, 3-/4-/5-pin mode, 4 polarity = 0, phase = 0 setup time, spi_somi valid before receive rising edge of spi_clk, 3-/4-/5-pin mode, 4 polarity = 0, phase = 1 7 t su(somi-clk) ns setup time, spi_somi valid before receive rising edge of spi_clk, 3-/4-/5-pin mode, 4 polarity = 1, phase = 0 setup time, spi_somi valid before receive falling edge of spi_clk, 3-/4-/5-pin mode, 4 polarity = 1, phase = 1 hold time, spi_somi valid after receive falling edge of spi_clk, 2 3-/4-/5-pin mode, polarity = 0, phase = 0 hold time, spi_somi valid after receive rising edge of spi_clk, 2 3-/4-/5-pin mode, polarity = 0, phase = 1 8 t h(clk-somi) ns hold time, spi_somi valid after receive rising edge of spi_clk, 2 3-/4-/5-pin mode, polarity = 1, phase = 0 hold time, spi_somi valid after receive falling edge of spi_clk, 2 3-/4-/5-pin mode, polarity = 1, phase = 1 peripheral information and electrical specifications 318 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 slave mode ? general table 7-114. general switching characteristics in slave mode (for 3-/4-/5-pin modes) (1) no. parameter min max unit delay time, transmit rising edge of spi_clk to spi_somi output 15 valid, 3-/4-/5-pin mode, polarity = 0, phase = 0 delay time, transmit falling edge of spi_clk to spi_somi output 15 valid, 3-/4-/5-pin mode, polarity = 0, phase = 1 13 t d(clk-somi) ns delay time, transmit falling edge of spi_clk to spi_somi output 15 valid, 3-/4-/5-pin mode, polarity = 1, phase = 0 delay time, transmit rising edge of spi_clk to spi_somi output 15 valid, 3-/4-/5-pin mode, polarity = 1, phase = 1 output hold time, spi_somi valid (except final bit) after receive 0.5t ? 4 falling edge of spi_clk, 3-/4-/5-pin mode, polarity = 0, phase = 0 output hold time, spi_somi valid (except final bit) after receive 0.5t ? 4 rising edge of spi_clk, 3-/4-/5-pin mode, polarity = 0, phase = 1 14 t oh(clk-somi) ns output hold time, spi_somi valid (except final bit) after receive 0.5t ? 4 rising edge of spi_clk, 3-/4-/5-pin mode, polarity = 1, phase = 0 output hold time, spi_somi valid (except final bit) after receive 0.5t ? 4 falling edge of spi_clk, 3-/4-/5-pin mode, polarity = 1, phase = 1 (1) t = period of spi_clk submit documentation feedback peripheral information and electrical specifications 319
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-115. general input timing requirements in slave mode (1) no. min max unit 9 t c(clk) cycle time, spi_clk 2p ns 10 t w(clkh) pulse width, spi_clk high p ns 11 t w(clkl) pulse width, spi_clk low p ns setup time, spi_simo data valid before receive falling edge of spi_clk, 3-/4-/5-pin mode, 2p polarity = 0, phase = 0 setup time, spi_simo data valid before receive rising edge of spi_clk, 3-/4-/5-pin mode, 2p polarity = 0, phase = 1 15 t su(simo-clk) ns setup time, spi_simo data valid before receive rising edge of spi_clk, 3-/4-/5-pin mode, 2p polarity = 1, phase = 0 setup time, spi_simo data valid before receive falling edge of spi_clk, 3-/4-/5-pin mode, 2p polarity = 1, phase = 1 hold time, spi_simo data valid after receive falling edge of spi_clk, 3-/4-/5-pin mode, 2 polarity = 0, phase = 0 hold time, spi_simo data valid after receive rising edge of spi_clk, 3-/4-/5-pin mode, 2 polarity = 0, phase = 1 16 t h(clk-simo) ns hold time, spi_simo data valid after receive rising edge of spi_clk, 3-/4-/5-pin mode, 2 polarity = 1, phase = 0 hold time, spi_simo data valid after receive falling edge of spi_clk, 3-/4-/5-pin mode, 2 polarity = 1, phase = 1 (1) p = period of spi core clock peripheral information and electrical specifications 320 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 master mode ? additional table 7-116. additional output switching characteristics of 4-pin enable option in master mode (1) (2) no. parameter min max unit delay time, slave assertion of spi_en active to first spi_clk 3p + 6 rising edge from master, 4-pin mode, polarity = 0, phase = 0 delay time, slave assertion of spi_en active to first spi_clk 0.5t + 3p + 6 rising edge from master, 4-pin mode, polarity = 0, phase = 1 17 t d(en-clk) ns delay time, slave assertion of spi_en active to first spi_clk 3p + 6 falling edge from master, 4-pin mode, polarity = 1, phase = 0 delay time, slave assertion of spi_en active to first spi_clk 0.5t + 3p + 6 falling edge from master, 4-pin mode, polarity = 1, phase = 1 (1) t = period of spi_clk; p = period of spi core clock (2) figure 7-87 shows only polarity = 0, phase = 0 as an example. in this case, the master spi is ready with new data before spi_en assertion. table 7-117. additional input timing requirements of 4-pin enable option in master mode (1) (2) no. min max unit delay time, max delay for slave to deassert spi_en after final spi_clk falling edge, 4-pin mode, 0.5t + p polarity = 0, phase = 0 delay time, max delay for slave to deassert spi_en after final spi_clk falling edge, 4-pin mode, p polarity = 0, phase = 1 18 t d(clk-en) ns delay time, max delay for slave to deassert spi_en after final spi_clk rising edge, 4-pin mode, 0.5t + p polarity = 1, phase = 0 delay time, max delay for slave to deassert spi_en after final spi_clk rising edge, 4-pin mode, p polarity = 1, phase = 1 (1) t = period of spi_clk; p = period of spi core clock (2) figure 7-87 shows only polarity = 0, phase = 0 as an example. in this case, the master spi is ready with new data before spi_en deassertion. submit documentation feedback peripheral information and electrical specifications 321
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-118. additional output switching characteristics of 4-pin chip-select option in master mode (1) (2) no. parameter min max unit output setup time, spi_cs[n] active before first spi_clk rising edge, polarity = 0, phase = 0, (c2tdelay + 2) * p - 6 spidelay.c2tdelay = 0 output setup time, spi_cs[n] active before first spi_clk rising edge, polarity = 0, phase = 1, (c2tdelay + 2) * p - 6 spidelay.c2tdelay = 0 19 t osu(cs-clk) (3) ns output setup time, spi_cs[n] active before first spi_clk falling edge, polarity = 1, phase = 0, (c2tdelay + 2) * p - 6 spidelay.c2tdelay = 0 output setup time, spi_cs[n] active before first spi_clk falling edge, polarity = 1, phase = 1, (c2tdelay + 2) * p - 6 spidelay.c2tdelay = 0 delay time, final spi_clk falling edge to master deasserting spi_cs[n], polarity = 0, phase = 0, (t2cdelay + 1) * p - 6 spidelay.t2cdelay = 0, spidat1.cshold not enabled delay time, final spi_clk falling edge to master deasserting spi_cs[n], polarity = 0, phase = 1, (t2cdelay + 1) * p - 6 spidelay.t2cdelay = 0, spidat1.cshold not enabled 20 t d(clk-cs) ns delay time, final spi_clk rising edge to master deasserting spi_cs[n], polarity = 1, phase = 0, (t2cdelay + 1) * p - 6 spidelay.t2cdelay = 0, spidat1.cshold not enabled delay time, final spi_clk rising edge to master deasserting spi_cs[n], polarity = 1, phase = 1, (t2cdelay + 2) * p - 6 spidelay.t2cdelay = 0, spidat1.cshold not enabled (1) p = period of spi core clock (2) figure 7-87 shows only polarity = 0, phase = 0 as an example. (3) the master spi is ready with new data before spi_cs[n] assertion. 322 peripheral information and electrical specifications submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-119. additional output switching characteristics of 5-pin option in master mode (1) no. parameter min max unit delay time, final spi_clk falling edge to master deasserting spi_cs[n], (t2cdelay + 2) * p - 6 polarity = 0, phase = 0, spidelay.t2cdelay = 0, spidat1.cshold not enabled delay time, final spi_clk rising edge to master deasserting spi_cs[n], polarity = 0, phase = 1, (t2cdelay + 2) * p - 6 spidelay.t2cdelay[4:0] = 0, spidat1.cshold not enabled 32 t d(clk-cs) (2) ns delay time, final spi_clk rising edge to master deasserting spi_cs[n], (t2cdelay + 2) * p - 6 polarity = 1, phase = 0, spidelay.t2cdelay = 0, spidat1.cshold not enabled delay time, final spi_clk falling edge to master deasserting spi_cs[n], (t2cdelay + 2) * p - 6 polarity = 1, phase = 1, spidelay.t2cdelay = 0, spidat1.cshold not enabled output setup time, spi_cs[n] active before first spi_clk rising edge, polarity = 0, (c2tdelay + 2) * p - 6 phase = 0, spidelay.c2tdelay = 0 output setup time, spi_cs[n] active before first spi_clk rising edge, polarity = 0, (c2tdelay + 2) * p - 6 phase = 1, spidelay.c2tdelay = 0 22 t osu(cs-clk) (2) (3) ns output setup time, spi_cs[n] active before first spi_clk falling edge, polarity = 1, (c2tdelay + 2) * p - 6 phase = 0, spidelay.c2tdelay = 0 output setup time, spi_cs[n] active before first spi_clk falling edge, polarity = 1, (c2tdelay + 2) * p - 6 phase = 1, spidelay.c2tdelay = 0 delay time, spi_en assertion low to first spi_clk rising edge, polarity = 0, 0.5t + p phase = 0, spi_en was initially deasserted and spi_clk delayed delay time, spi_en assertion low to first spi_clk rising edge, polarity = 0, p phase = 1, spi_en was initially deasserted and spi_clk delayed 23 t d(clk-en) (2) ns delay time, spi_en assertion low to first spi_clk falling edge, polarity = 1, 0.5t + p phase = 0, spi_en was initially deasserted and spi_clk delayed delay time, spi_en assertion low to first spi_clk falling edge, polarity = 1, p phase = 1, spi_en was initially deasserted and spi_clk delayed (1) t = period of spi_clk; p = period of spi core clock (2) figure 7-87 shows only polarity = 0, phase = 0 as an example. (3) spi_en is immediately asserted, the spi master is ready with new data before spi_cs[n] assertion. submit documentation feedback peripheral information and electrical specifications 323
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-120. additional input timing requirements of 5-pin option in master mode (1) no. min max min max unit delay time, max delay for slave spi to drive spi_ena valid after 21 t d(csl-ena) master asserts spi_cs[n] to 0.5p 0.5d ns delay the master from beginning the next transfer delay time, max delay for slave to deassert spi_ena after final 0.5t 0.5t spi_clk falling edge, 5-pin mode, polarity = 0, phase = 0 delay time, max delay for slave to deassert spi_ena after final 0 0 spi_clk falling edge, 5-pin mode, polarity = 0, phase = 1 31 t d(clk-ena) (2) (3) ns delay time, max delay for slave to deassert spi_ena after final 0.5t 0.5t spi_clk rising edge, 5-pin mode, polarity = 1, phase = 0 delay time, max delay for slave to deassert spi_ena after final 0 0 spi_clk rising edge, 5-pin mode, polarity = 1, phase = 1 (1) t = period of spi_clk; p = period of spi core clock; d = period of 24-mhz clock (2) spi master is ready with new data before spi_ena deassertion. (3) figure 7-87 shows only polarity = 0, phase = 0 as an example. slave mode ? additional table 7-121. additional output switching characteristics of 4-pin enable option in slave mode (1) no. parameter min max unit delay time, final spi_clk falling edge to slave deasserting spi_en, polarity = 0, p ? 6 3p + 15 phase = 0 delay time, final spi_clk falling edge to slave deasserting spi_en, polarity = 0, 0.5t + p ? 6 0.5t + 3p + 15 phase = 1 spi24 t d(clk-en) (2) ns delay time, final spi_clk rising edge to slave deasserting spi_en, polarity = 1, p ? 6 3p + 15 phase = 0 delay time, final spi_clk rising edge to slave deasserting spi_en, polarity = 1, 0.5t + p ? 6 0.5t + 3p + 15 phase = 1 (1) t = period of spi_clk; p = period of spi core clock (2) figure 7-88 shows only polarity = 0, phase = 0 as an example. table 7-122. additional output switching characteristics of 4-pin chip-select option in slave mode (1) no. parameter min max unit delay time, master asserting spi_cs[n] to slave driving spi_somi 27 t d(csl-somi) p + 6 ns data valid disable time, master deasserting spi_cs[n] to slave driving 28 t dis(csh-somi) p + 6 ns spi_somi high impedance (1) t = period of spi_clk; p = period of spi core clock 324 peripheral information and electrical specifications submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-123. additional input timing requirements of 4-pin chip-select option in slave mode (1) no. min max unit setup time, spi_cs[n] asserted at slave to first spi_clk edge 25 t su(csl-clk) 2p + 6 ns (rising or falling) at slave delay time, final falling edge spi_clk to spi_cs[n] deasserted, 0.5t + p + 6 polarity = 0, phase = 0 delay time, final falling edge spi_clk to spi_cs[n] deasserted, p + 6 polarity = 0, phase = 1 26 t d(clk-csh) (2) ns delay time, final rising edge spi_clk to spi_cs[n] deasserted, 0.5t + p + 6 polarity = 1, phase = 0 delay time, final rising edge spi_clk to spi_cs[n] deasserted, p + 6 polarity = 1, phase = 1 (1) t = period of spi_clk; p = period of spi core clock (2) figure 7-88 shows only polarity = 0, phase = 0 as an example. table 7-124. additional output switching characteristics of 5-pin option in slave mode (1) no. parameter min max unit enable time, master asserting spi_cs[n] to slave driving spi33 t en(csl-somi) p + 6 ns spi_somi valid disable time, master deasserting spi_cs[n] to slave driving spi34 t dis(csh-somi) p + 6 ns spi_somi high impedance spi29 t en(csl-en) enable time, master asserting spi_cs[n] to slave driving spi_en 6 ns disable time, final clock receive falling edge of spi_clk to slave drive spi_en high impedance, polarity = 0, phase = 0, 1.5p + 6 spiint0.enable highz = 1 disable time, final clock receive rising edge of spi_clk to slave drive spi_en high impedance, polarity = 0, phase = 1, 1.5p + 6 spiint0.enable highz = 1 spi30 t dis(clk-enz) (2) ns disable time, final clock receive rising edge of spi_clk to slave drive spi_en high impedance, polarity = 1, phase = 0, 1.5p + 6 spiint0.enable highz = 1 disable time, final clock receive falling edge of spi_clk to slave drive spi_en high impedance, polarity = 1, phase = 1, 1.5p + 6 spiint0.enable highz = 1 disable time, spi_cs[n] deassertion to slave drive spi_en high impedance, polarity = 0, phase = 0, p + 6 spiint0.enable highz = 1 disable time, spi_cs[n] deassertion to slave drive spi_en high impedance, polarity = 0, phase = 1, p + 6 spiint0.enable highz = 1 37 t dis(csh-enh) (2) ns disable time, spi_cs[n] deassertion to slave drive spi_en high impedance, polarity = 1, phase = 0, p + 6 spiint0.enable highz = 1 disable time, spi_cs[n] deassertion to slave drive spi_en high impedance, polarity = 1, phase = 1, p + 6 spiint0.enable highz = 1 (1) t = period of spi_clk; p = period of spi core clock (2) figure 7-88 shows only polarity = 0, phase = 0 as an example. submit documentation feedback peripheral information and electrical specifications 325
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-124. additional output switching characteristics of 5-pin option in slave mode (continued) no. parameter min max unit delay time, final clock receive edge on spi_clk to slave deasserting spi_en, polarity = 0, phase = 0, 3p + 15 spiint0.enable highz = 0 delay time, final clock receive edge on spi_clk to slave 0.5t + 3p + deasserting spi_en, polarity = 0, phase = 1, 15 spiint0.enable highz = 0 38 t d(clk-enz) (2) ns delay time, final clock receive edge on spi_clk to slave deasserting spi_en, polarity = 1, phase = 0, 3p + 15 spiint0.enable highz = 0 delay time, final clock receive edge on spi_clk to slave 0.5t + 3p + deasserting spi_en, polarity = 1, phase = 1, 15 spiint0.enable highz = 0 delay time, spi_cs[n] deassertion to slave deasserting spi_en, 6 polarity = 0, phase = 0, spiint0.enable highz = 0 delay time, spi_cs[n] deassertion to slave deasserting spi_en, 6 polarity = 0, phase = 1, spiint0.enable highz = 0 39 t d(csh-enh) (2) ns delay time, spi_cs[n] deassertion to slave deasserting spi_en, 6 polarity = 1, phase = 0, spiint0.enable highz = 0 delay time, spi_cs[n] deassertion to slave deasserting spi_en 6 polarity = 1, phase = 1, spiint0.enable highz = 0 table 7-125. additional input timing requirements of 5-pin option in slave mode (1) no. min max unit delay time, spi_cs[n] asserted at slave to first clock edge (rising 35 t d(csl-clk) p ns or falling) of spi_clk at slave delay time, spi_clk falling edge to spi_cs[n] deasserted, 0.5t + p + 6 polarity = 0, phase = 0 delay time, spi_clk falling edge to spi_cs[n] deasserted, p + 6 polarity = 0, phase = 1 36 t d(clk-csh) (2) ns delay time, spi_clk rising edge to spi_cs[n] deasserted, polarity 0.5t + p + 6 = 1, phase = 0 delay time, spi_clk rising edge to spi_cs[n] deasserted, polarity p + 6 = 1, phase = 1 (1) t = period of spi_clk; p = period of spi core clock (2) figure 7-88 shows only polarity = 0, phase = 0 as an example. peripheral information and electrical specifications 326 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 figure 7-85. spi timings?master mode submit documentation feedback peripheral information and electrical specifications 327 spi_clk spi_simo spi_somi spi_clk spi_simo spi_somi spi_clk spi_simo spi_somi spi_clk spi_simo spi_somi mo(0) mo(1) mo(n-1) mo(n) mi(0) mi(1) mi(n-1) mi(n) mo(n) mi(n-1) mo(1) 6 7 7 7 7 8 8 8 8 3 2 6 1 4 4 4 4 5 5 5 6 master modepolarity = 0 phase = 0 master modepolarity = 0 phase = 1 master modepolarity = 1 phase = 0 master modepolarity = 1 phase = 1 5 mo(0) mo(1) mo(n-1) mi(n) mi(n-1) mi(1) mi(0) mo(0) mo(1) mo(n-1) mo(n) mi(n) mi(1) mi(0) mo(0) mo(n-1) mo(n) mi(n) mi(n-1) mi(1) mi(0) 6
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com a. the first bit of transmit data becomes valid on the spi_somi pin when software writes to the spidat0/1 register(s). see the tms320dm646x dmsoc serial peripheral interface (spi) user's guide (literature number spruer4 ). figure 7-86. spi timings?slave mode peripheral information and electrical specifications 328 submit documentation feedback spi_clk spi_simo spi_somi spi_clk spi_simo spi_somi spi_clk spi_simo spi_somi spi_clk spi_simo spi_somi si(1) si(n-1) si(n) so(0) so(1) so(n-1) so(n) si(0) si(1) si(n) so(0) so(1) 14 14 15 15 15 15 16 16 16 16 11 10 14 9 13 13 13 13 14 slave mode polarity = 0 phase = 0 slave mode polarity = 0 phase = 1 slave mode polarity = 1 phase = 0 slave mode polarity = 1 phase = 1 si(1) si(0) si(n-1) so(n-1) so(n) so(n-1) si(n) si(n-1) si(1) si(0) so(n) so(1) so(0) si(n) si(n-1) so(n-1) so(n) so(1) so(0) si(0)
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 figure 7-87. spi timings?master mode (4-pin and 5-pin) submit documentation feedback peripheral information and electrical specifications 329 master mode 4 pin with chip select spi_clk spi_simo spi_somi spi_en spi_clk spi_simo spi_somi spi_cs[n] spi_clk spi_simo spi_somi spi_en spi_cs[n] mo(0) 17 19 21 22 23 32 31 20 18 master mode 4 pin with enable master mode 5 pin a. deselected is programmable either high or 3-state (requires external pullup) desel (a) desel (a) mo(0) mo(1) mo(n-1) mo(n) mi(n) mi(n-1) mi(1) mi(0) mo(0) mo(1) mo(n-1) mo(n) mi(n) mi(n-1) mi(1) mi(0) mo(1) mo(n-1) mo(n) mi(n-1) mi(1) mi(0) mi(n)
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com figure 7-88. spi timings?slave mode (4-pin and 5-pin) 330 peripheral information and electrical specifications submit documentation feedback 27 spi_clk spi_somi spi_simo spi_en spi_clk spi_somi spi_simo spi_cs[n] spi_clk spi_somi spi_simo spi_en spi_cs[n] so(1) so(n-1) so(n) so(0) si(1) so(0) so(n-1) so(n) 24 26 28 36 30, 38 34 35 25 33 29 slave mode 4 pin with enable slave mode 4 pin with chip select slave mode 5 pin desel (a) desel (a) 37, 39 a. deselected is programmable either high or 3-state (requires external pullup) so(n) so(0) si(0) si(1) si(n-1) si(n) so(n-1) si(0) si(n-1) si(n) si(0) si(1) si(n-1) si(n) so(1) so(1)
7.24 universal asynchronouse receiver/transmitter (uart) 7.24.1 uart device-specific information tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the uart performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the cpu. dm6467 provides up to 3 uart peripheral interfaces depending on the selected pin multiplexing. each uart has the following features: selectable uart/irda (sir/mir)/cir modes dual 64 entry fifos for received and transmitted data payload programmable and selectable transmit and receive fifo trigger levels for dma and interrupt generation frequency prescaler values from 0 to 16 383 it generate the appropriate baud rates two dma requests and one interrupt request to the system uart functions include: baud-rate up to 1.8432 mbit/s software/hardware flow control ? programmable xon/xoff characters ? programmable auto- rts and auto- cts programmable serial interfaces characteristics ? 5, 6, 7, or 8-bit characters ? even, odd, mark, space, or no parity bit generation and detection ? 1, 1.5, or 2 stop bit generation additional modem control functions ( udtr0, udsr0, udcd0, and urin0) [uart0 only] ir-irda functions include: both slow infrared (sir, baud-rate up to 115.2 kbit/s) and medium infrared (mir, baud-rate up to 0.576 mbits/s) supported supports framing error, cyclic redundancy check (crc) error, and abort pattern (sir, mir) detection 8-entry status fifo (with selectable trigger levels) available to monitor frame length and frame errors ir-cir functions include: consumer infrared (cir) remote control mode with programmable data encoding submit documentation feedback peripheral information and electrical specifications 331
7.24.2 uart peripheral register description(s) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-126 shows the uart register name summary. table 7-127 , table 7-128 , and table 7-129 show the uart0/1/2 registers, respectively along with their configuration requirements. table 7-126. uart register summary acronym register name acronym register name rhr receive holding register rxflh receive frame length high register thr transmit holding register blr bof control register ier interrupt enable register acreg auxilliary control register iir interrupt identification register scr supplementary control register fcr fifo control register ssr supplementary status register lcr line control register eblr bof length register mcr modem control register mvr module version register lsr line status register sysc system configuration register msr modem status register syss system status register spr scratchpad register wer wake-up enable register tcr transmission control register cfps carrier frequency prescaler register tlr trigger level register dll divisor latch low register mdr1 mode definition register 1 dlh divisor latch high register mdr2 mode definition register 2 uasr uart autobauding status register sflsr status fifo line status register efr enhanced feature register resume resume register xon1 uart xon1 character register sfregl status fifo register low xon2 uart xon2 character register sfregh status fifo register high xoff1 uart xoff1 character register txfll transmit frame length low register xoff2 uart xoff2 character register txflh transmit frame length high register addr1 irda address 1 register rxfll receive frame length low register addr2 irda address 2 register peripheral information and electrical specifications 332 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-127. uart0 ? uart/irda/cir register program map hex address register range lcr[7] = 0 lcr[7] = 1 & lcr[7:0] 1 0xbf lcr[7:0] = 0xbf read write read write read write 0x01c2 0000 rhr thr dll dll dll dll 0x01c2 0004 ier (1) ier (1) dlh dlh dlh dlh 0x01c2 0008 iir fcr (2) iir fcr (2) efr efr 0x01c2 000c lcr lcr lcr lcr lcr lcr 0x01c2 0010 mcr (2) mcr (2) mcr (2) mcr (2) xon1/addr1 xon1/addr1 0x01c2 0014 lsr ? lsr ? xon2/adr2 xon2/addr2 0x01c2 0018 msr/tcr (3) tcr (3) msr/tcr (3) tcr (3) xoff1/tcr (3) xoff1/tcr (3) 0x01c2 001c spr/tlr (3) spr/tlr (3) spr/tlr (3) spr/tlr (3) xoff2/tlr (3) xoff2/tlr (3) 0x01c2 0020 mdr1 mdr1 mdr1 mdr1 mdr1 mdr1 0x01c2 0024 mdr2 mdr2 mdr2 mdr2 mdr2 mdr2 0x01c2 0028 sflsr txfll sflsr txfll sflsr txfll 0x01c2 002c resume txflh resume txflh resume txflh 0x01c2 0030 sfregl rxfll sfregl rxfll sfregl rxfll 0x01c2 0034 sfregh rxflh sfregh rxflh sfregh rxflh 0x01c2 0038 blr blr uasr ? uasr ? 0x01c2 003c acreg acreg ? ? ? ? 0x01c2 0040 scr scr scr scr scr scr 0x01c2 0044 ssr ? ssr ? ssr ? 0x01c2 0048 eblr eblr ? ? ? ? 0x01c2 004c ? ? ? ? ? ? 0x01c2 0050 mvr ? mvr ? mvr ? 0x01c2 0054 sysc sysc sysc sysc sysc sysc 0x01c2 0058 syss ? syss ? syss ? 0x01c2 005c wer wer wer wer wer wer 0x01c2 0060 cfps cfps cfps cfps cfps cfps 0x01c2 0064 - ? ? ? ? ? ? 0x01c2 007f (1) in uart modes, ier.[7:4] can only be written when enhanced_en in efr = 1. in irda/cir modes, enhanced_en in efr has no impact on the access to ier.[7:4]. (2) mcr.[7:5] and the tx_fifo_trig bits in fcr can only be written to when the enhanced_en bit in efr = 1. (3) transmission control register (tcr) and trigger level register (tlr) are accessible only when the enhanced_en bit in the efr =1 and the tcr_tlr bit in the mcr = 1. submit documentation feedback peripheral information and electrical specifications 333
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-128. uart1 ? uart/irda/cir register program map hex address register range lcr[7] = 0 lcr[7] = 1 & lcr[7:0] 1 0xbf lcr[7:0] = 0xbf read write read write read write 0x01c2 0400 rhr thr dll dll dll dll 0x01c2 0404 ier (1) ier (1) dlh dlh dlh dlh 0x01c2 0408 iir fcr (2) iir fcr (2) efr efr 0x01c2 040c lcr lcr lcr lcr lcr lcr 0x01c2 0410 mcr (2) mcr (2) mcr (2) mcr (2) xon1/addr1 xon1/addr1 0x01c2 0414 lsr ? lsr ? xon2/adr2 xon2/addr2 0x01c2 0418 msr/tcr (3) tcr (3) msr/tcr (3) tcr (3) xoff1/tcr (3) xoff1/tcr (3) 0x01c2 041c spr/tlr (3) spr/tlr (3) spr/tlr (3) spr/tlr (3) xoff2/tlr (3) xoff2/tlr (3) 0x01c2 0420 mdr1 mdr1 mdr1 mdr1 mdr1 mdr1 0x01c2 0424 mdr2 mdr2 mdr2 mdr2 mdr2 mdr2 0x01c2 0428 sflsr txfll sflsr txfll sflsr txfll 0x01c2 042c resume txflh resume txflh resume txflh 0x01c2 0430 sfregl rxfll sfregl rxfll sfregl rxfll 0x01c2 0434 sfregh rxflh sfregh rxflh sfregh rxflh 0x01c2 0438 blr blr uasr ? uasr ? 0x01c2 043c acreg acreg ? ? ? ? 0x01c2 0440 scr scr scr scr scr scr 0x01c2 0444 ssr ? ssr ? ssr ? 0x01c2 0448 eblr eblr ? ? ? ? 0x01c2 044c ? ? ? ? ? ? 0x01c2 0450 mvr ? mvr ? mvr ? 0x01c2 0454 sysc sysc sysc sysc sysc sysc 0x01c2 0458 syss ? syss ? syss ? 0x01c2 045c wer wer wer wer wer wer 0x01c2 0460 cfps cfps cfps cfps cfps cfps 0x01c2 0464 - ? ? ? ? ? ? 0x01c2 047f (1) in uart modes, ier.[7:4] can only be written when enhanced_en in efr = 1. in irda/cir modes, enhanced_en in efr has no impact on the access to ier.[7:4]. (2) mcr.[7:5] and the tx_fifo_trig bits in fcr can only be written to when the enhanced_en bit in efr = 1. (3) transmission control register (tcr) and trigger level register (tlr) are accessible only when the enhanced_en bit in the efr =1 and the tcr_tlr bit in the mcr = 1. 334 peripheral information and electrical specifications submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-129. uart2 ? uart/irda/cir register program map hex address register range lcr[7] = 0 lcr[7] = 1 & lcr[7:0] 1 0xbf lcr[7:0] = 0xbf read write read write read write 0x01c2 0800 rhr thr dll dll dll dll 0x01c2 0804 ier (1) ier (1) dlh dlh dlh dlh 0x01c2 0808 iir fcr (2) iir fcr (2) efr efr 0x01c2 080c lcr lcr lcr lcr lcr lcr 0x01c2 0810 mcr (2) mcr (2) mcr (2) mcr (2) xon1/addr1 xon1/addr1 0x01c2 0814 lsr ? lsr ? xon2/adr2 xon2/addr2 0x01c2 0818 msr/tcr (3) tcr (3) msr/tcr (3) tcr (3) xoff1/tcr (3) xoff1/tcr (3) 0x01c2 081c spr/tlr (3) spr/tlr (3) spr/tlr (3) spr/tlr (3) xoff2/tlr (3) xoff2/tlr (3) 0x01c2 0820 mdr1 mdr1 mdr1 mdr1 mdr1 mdr1 0x01c2 0824 mdr2 mdr2 mdr2 mdr2 mdr2 mdr2 0x01c2 0828 sflsr txfll sflsr txfll sflsr txfll 0x01c2 082c resume txflh resume txflh resume txflh 0x01c2 0830 sfregl rxfll sfregl rxfll sfregl rxfll 0x01c2 0834 sfregh rxflh sfregh rxflh sfregh rxflh 0x01c2 0838 blr blr uasr ? uasr ? 0x01c2 083c acreg acreg ? ? ? ? 0x01c2 0840 scr scr scr scr scr scr 0x01c2 0844 ssr ? ssr ? ssr ? 0x01c2 0848 eblr eblr ? ? ? ? 0x01c2 084c ? ? ? ? ? ? 0x01c2 0850 mvr ? mvr ? mvr ? 0x01c2 0854 sysc sysc sysc sysc sysc sysc 0x01c2 0858 syss ? syss ? syss ? 0x01c2 085c wer wer wer wer wer wer 0x01c2 0860 cfps cfps cfps cfps cfps cfps 0x01c2 0864 - ? ? ? ? ? ? 0x01c2 087f (1) in uart modes, ier.[7:4] can only be written when enhanced_en in efr = 1. in irda/cir modes, enhanced_en in efr has no impact on the access to ier.[7:4]. (2) mcr.[7:5] and the tx_fifo_trig bits in fcr can only be written to when the enhanced_en bit in efr = 1. (3) transmission control register (tcr) and trigger level register (tlr) are accessible only when the enhanced_en bit in the efr =1 and the tcr_tlr bit in the mcr = 1. submit documentation feedback peripheral information and electrical specifications 335
7.24.3 uart electrical data/timing [receive/transmit] tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-130. timing requirements for uartx receive (1) (see figure 7-89 ) -594, -729 no. unit min max 4 t w(urxdb) pulse duration, receive data bit (urxdx) [15/30/100 pf] 0.96u 1.05u ns 5 t w(urxsb) pulse duration, receive start bit [15/30/100 pf] 0.96u 1.05u ns (1) u = uart baud time = 1/programmed baud rate. table 7-131. switching characteristics over recommended operating conditions for uartx transmit (1) (see figure 7-89 ) -594, -729 no. parameter unit min max 1 f (baud) maximum programmable baud rate 128 khz 2 t w(utxdb) pulse duration, transmit data bit (utxdx) [15/30/100 pf] u - 2 u + 2 ns 3 t w(utxsb) pulse duration, transmit start bit [15/30/100 pf] u - 2 u + 2 ns (1) u = uart baud time = 1/programmed baud rate. figure 7-89. uart transmit/receive timing 336 peripheral information and electrical specifications submit documentation feedback 3 2 start bit data bits utxdx 5 data bits bit start 4 urxdx
7.24.4 irda interface receive/transmit timings tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-132. signaling rate and pulse duration specification in receive mode electrical pulse duration signaling rate unit max nom min sir mode 2.4 kbit/s (kbps) 1.41 78.1 88.55 m s 9.6 kbps 1.41 19.5 22.13 m s 19.2 kbps 1.41 9.75 11.07 m s 38.4 kbps 1.41 4.87 5.96 m s 57.6 kbps 1.41 3.25 4.34 m s 115.2 kbps 1.41 1.62 2.23 m s mir mode 0.576 mbit/s (mbps) 297.2 416 518.8 ns table 7-133. timing requirements for irda receive -594, -729 no. unit min max 1 t r(urxd) rise time, receive data bit urxdx 200 ns 2 t f(urxd) fall time, receive data bit urxdx 200 ns table 7-134. signaling rate and pulse duration specification in transmit mode electrical pulse duration signaling rate unit max nom min sir mode 2.4 kbit/s (kbps) 78.10 78.1 78.10 m s 9.6 kbps 19.50 19.5 19.50 m s 19.2 kbps 9.75 9.75 9.75 m s 38.4 kbps 4.87 4.87 4.87 m s 57.6 kbps 3.25 3.25 3.25 m s 115.2 kbps 1.62 1.62 1.62 m s mir mode 0.576 mbit/s (mbps) 414.0 416.0 419.0 ns submit documentation feedback peripheral information and electrical specifications 337
7.25 inter-integrated circuit (i2c) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the inter-integrated circuit (i2c) module provides an interface between dm6467 and other devices compliant with philips semiconductors inter-ic bus (i 2 c-bus?) specification version 2.1. external components attached to this 2-wire serial bus can transmit/receive 2 to 8-bit data to/from the dmsoc through the i2c module. the i2c port does not support cbus compatible devices. the i2c port supports the following features: compatible with philips i2c specification revision 2.1 (january 2000) standard and fast modes from 10 ? 400 kbps (no fail-safe i/o buffers) noise filter to remove noise 50 ns or less seven- and ten-bit device addressing modes master (transmit/receive) and slave (transmit/receive) functionality events: dma, interrupt, or polling slew-rate limited open-drain output buffers for more detailed information on the i2c peripheral, see the tms320dm646x dmsoc inter-integrated circuit (i2c) module user's guide (literature number spruer0 ). 338 peripheral information and electrical specifications submit documentation feedback
7.25.1 i2c peripheral register description(s) tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-135. i2c registers hex address range acronym register name 0x1c2 1000 icoar i2c own address register 0x1c2 1004 icimr i2c interrupt mask register 0x1c2 1008 icstr i2c interrupt status register 0x1c2 100c icclkl i2c clock divider low register 0x1c2 1010 icclkh i2c clock divider high register 0x1c2 1014 iccnt i2c data count register 0x1c2 1018 icdrr i2c data receive register 0x1c2 101c icsar i2c slave address register 0x1c2 1020 icdxr i2c data transmit register 0x1c2 1024 icmdr i2c mode register 0x1c2 1028 icivr i2c interrupt vector register 0x1c2 102c icemdr i2c extended mode register 0x1c2 1030 icpsc i2c prescaler register 0x1c2 1034 icpid1 i2c peripheral identification register 1 0x1c2 1038 icpid2 i2c peripheral identification register 2 submit documentation feedback peripheral information and electrical specifications 339
7.25.2 i2c electrical data/timing tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-136. timing requirements for i2c timings (1) (see figure 7-90 ) -594, -729 standard no. fast mode unit mode min max min max 1 t c(scl) cycle time, scl 10 2.5 s setup time, scl high before sda low (for a repeated start 2 t su(sclh-sdal) 4.7 0.6 s condition) hold time, scl low after sda low (for a start and a repeated 3 t h(scll-sdal) 4 0.6 s start condition) 4 t w(scll) pulse duration, scl low 4.7 1.3 s 5 t w(sclh) pulse duration, scl high 4 0.6 s 6 t su(sdav-sclh) setup time, sda valid before scl high 250 100 (2) ns 7 t h(sda-scll) hold time, sda valid after scl low 0 (3) 0 (3) 0.9 (4) s pulse duration, sda high between stop and start 8 t w(sdah) 4.7 1.3 s conditions 9 t r(sda) rise time, sda 1000 20 + 0.1c b (5) 300 ns 10 t r(scl) rise time, scl 1000 20 + 0.1c b (5) 300 ns 11 t f(sda) fall time, sda 300 20 + 0.1c b (5) 300 ns 12 t f(scl) fall time, scl 300 20 + 0.1c b (5) 300 ns 13 t su(sclh-sdah) setup time, scl high before sda high (for stop condition) 4 0.6 s 14 t w(sp) pulse duration, spike (must be suppressed) 0 50 ns 15 c b (5) capacitive load for each bus line 400 400 pf (1) the i2c pins sda and scl do not feature fail-safe i/o buffers. these pins could potentially draw current when the device is powered down. (2) a fast-mode i 2 c-bus? device can be used in a standard-mode i 2 c-bus system, but the requirement t su(sda-sclh) 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max + t su(sda-sclh) = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. (3) a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. (4) the maximum t h(sda-scll) has only to be met if the device does not stretch the low period [t w(scll) ] of the scl signal. (5) c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times are allowed. figure 7-90. i2c receive timings peripheral information and electrical specifications 340 submit documentation feedback 10 8 4 3 7 12 5 6 14 2 3 13 stop start repeated start stop sda scl 1 11 9
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-137. switching characteristics for i2c timings (1) (see figure 7-91 ) -594, -729 standard no. parameter fast mode unit mode min max min max 16 t c(scl) cycle time, scl 10 2.5 s delay time, scl high to sda low (for a repeated start 17 t d(sclh-sdal) 4.7 0.6 s condition) delay time, sda low to scl low (for a start and a repeated 18 t d(sdal-scll) 4 0.6 s start condition) 19 t w(scll) pulse duration, scl low 4.7 1.3 s 20 t w(sclh) pulse duration, scl high 4 0.6 s 21 t d(sdav-sclh) delay time, sda valid to scl high 250 100 ns 22 t v(scll-sdav) valid time, sda valid after scl low 0 0 0.9 s pulse duration, sda high between stop and start 23 t w(sdah) 4.7 1.3 s conditions 24 t r(sda) rise time, sda 1000 20 + 0.1c b (1) 300 ns 25 t r(scl) rise time, scl 1000 20 + 0.1c b (1) 300 ns 26 t f(sda) fall time, sda 300 20 + 0.1c b (1) 300 ns 27 t f(scl) fall time, scl 300 20 + 0.1c b (1) 300 ns 28 t d(sclh-sdah) delay time, scl high to sda high (for stop condition) 4 0.6 s 29 c p capacitance for each i2c pin 10 10 pf (1) c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times are allowed. figure 7-91. i2c transmit timings submit documentation feedback peripheral information and electrical specifications 341 25 23 19 18 22 27 20 21 17 18 28 stop start repeated start stop sda scl 16 26 24
7.26 pulse width modulator (pwm) 7.26.1 pwm device-specific information 7.26.2 pwm peripheral register description(s) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the pwm provides a way to generate a pulse periodic waveform for motor control or can act as a digital-to-analog converter with some external components. the 2 dm6467 pulse width modulator (pwm) peripherals support the following features: 32-bit period counter 32-bit first-phase duration counter 32-bit repeat count for one-shot operation. one-shot operation generates n+1 periods of waveform, n being the repeat count register value. configurable to operate in either one-shot or continuous mode programmable buffered period and first-phase duration registers one-shot operation triggerable by vpif or gpio with programmable edge transitions. (low-to-high or high-to-low). one-shot operation generates n+1 periods of waveform, n being the repeat count register value configurable pwm output pin inactive state interrupt and edma synchronization events emulation support for stop or free-run operation table 7-138 and table 7-139 show the register memory maps for pwm0/1. table 7-138. pwm0 register hex address range acronym register name 0x01c2 2000 pid pwm0 peripheral identification register 0x01c2 2004 pcr pwm0 peripheral control register 0x01c2 2008 cfg pwm0 configuration register 0x01c2 200c start pwm0 start register 0x01c2 2010 rpt pwm0 repeat count register 0x01c2 2014 per pwm0 period register 0x01c2 2018 ph1d pwm0 first-phase duration register 0x01c2 201c - 0x01c2 23ff - reserved table 7-139. pwm1 register memory map hex address range acronym register name 0x01c2 2400 pid pwm1 peripheral identification register 0x01c2 2404 pcr pwm1 peripheral control register 0x01c2 2408 cfg pwm1 configuration register 0x01c2 240c start pwm1 start register 0x01c2 2410 rpt pwm1 repeat count register 0x01c2 2414 per pwm1 period register 0x01c2 2418 ph1d pwm1 first-phase duration register 0x01c2 241c -0x01c2 27ff - reserved peripheral information and electrical specifications 342 submit documentation feedback
7.26.3 pwm0/1 electrical data/timing tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-140. switching characteristics over recommended operating conditions for pwm0/1 outputs (1) (see figure 7-92 and figure 7-93 ) -594, -729 no. parameter unit min max 1 t w(pwmh) pulse duration, pwmx high 37 ns 2 t w(pwml) pulse duration, pwmx low 37 ns 3 t t(pwm) transition time, pwmx 5 ns 4 t d(vpif-pwmv) delay time, vpif (vsync) or gpio trigger event to pwmx valid 4p 6p + 20 ns (1) p = sysclk3 period in ns. figure 7-92. pwm output timing figure 7-93. pwm output delay timing submit documentation feedback peripheral information and electrical specifications 343 pwm0/1 1 3 3 2 4 vpif(vsync) 4 invalid invalid valid valid pwm0 pwm1
7.27 timers 7.27.1 timers device-specific information 7.27.2 timer peripheral register description(s) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the timers support four modes of operation: a 64-bit general-purpose (gp) timer, dual-unchained 32-bit gp timers, dual-chained 32-bit timers, or a watchdog timer. the gp timer mode can be used to generate periodic interrupts or edma synchronization events. the watchdog timer mode is used to provide a recovery mechanism for the device in the event of a fault condition, such as a non-exiting code loop. the dm6467 device has 3 64-bit general-purpose timers which have the following features: 64-bit count-up counter timer modes: ? 64-bit general-purpose timer mode (timer 0 and 1) ? dual 32-bit general-purpose timer mode (timer 0 and 1) ? watchdog timer mode (timer 2) [mainly controlled by the arm] 2 possible clock sources: ? internal clock ? external clock input via timer input pin tinp0u, tinp0l, and tinp1l, (timer 0 and 1 only) 2 operation modes: ? one-time operation (timer runs for one period then stops) ? continuous operation (timer automatically resets after each period) generates interrupts to the dsp and the arm cpus generates sync event to edma causes device global reset upon watchdog timer timeout (timer 2 only) for more detailed information, see the tms320dm646x dmsoc 64-bit timer user's guide (literature number spruer5 ). table 7-141 , table 7-142 , and table 7-143 show the registers for timer 0, timer 1, and timer 2 (watchdog). table 7-141. timer 0 registers hex address range acronym description 0x01c2 1400 pid12 timer 0 peripheral identification register 12 0x01c2 1404 emumgt timer 0 emulation management 0x01c2 1410 tim12 timer 0 counter register 12 0x01c2 1414 tim34 timer 0 counter register 34 0x01c2 1418 prd12 timer 0 period register 12 0x01c2 141c prd34 timer 0 period register 34 0x01c2 1420 tcr timer 0 control register 0x01c2 1424 tgcr timer 0 global control register 0x01c2 1428 - 0x01c2 17ff - reserved peripheral information and electrical specifications 344 submit documentation feedback
tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-142. timer 1 registers hex address range acronym description 0x01c2 1800 pid12 timer 1 peripheral identification register 12 0x01c2 1804 emumgt timer 1 emulation management 0x01c2 1810 tim12 timer 1 counter register 12 0x01c2 1814 tim34 timer 1 counter register 34 0x01c2 1818 prd12 timer 1 period register 12 0x01c2 181c prd34 timer 1 period register 34 0x01c2 1820 tcr timer 1 control register 0x01c2 1824 tgcr timer 1 global control register 0x01c2 1828 - 0x01c2 1bff - reserved table 7-143. timer 2 (watchdog) registers hex address range acronym description 0x01c2 1c00 pid12 timer 2 peripheral identification register 12 0x01c2 1c04 emumgt timer 2 emulation management 0x01c2 1c10 tim12 timer 2 counter register 12 0x01c2 1c14 tim34 timer 2 counter register 34 0x01c2 1c18 prd12 timer 2 period register 12 0x01c2 1c1c prd34 timer 2 period register 34 0x01c2 1c20 tcr timer 2 control register 0x01c2 1c24 tgcr timer 2 global control register 0x01c2 1c28 wdtcr timer 2 watchdog timer control register 0x01c2 1c2c - 0x01c2 1fff - reserved submit documentation feedback peripheral information and electrical specifications 345
7.27.3 timer electrical data/timing tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-144. timing requirements for timer input (1) (see figure 7-94 ) -594, -729 no. unit min max 1 t w(tinph) pulse duration, tinpxl/tinp0u high 2p ns 2 t w(tinpl) pulse duration, tinpxl/tinp0u low 2p ns (1) p = dev_mxi/dev_clkin cycle time in ns. for example, when dev_mxi/dev_clkin frequency is 27 mhz, use p = 37.0 37 ns. table 7-145. switching characteristics over recommended operating conditions for timer output (1) (see figure 7-94 ) -594, -729 no. unit min max 3 t w(touth) pulse duration, toutxl/toutxu/tout2 high p ns 4 t w(toutl) pulse duration, toutxl/toutxu/tout2 low p ns (1) p = dev_mxi/dev_clkin cycle time in ns. for example, when dev_mxi/dev_clkin frequency is 27 mhz, use p = 37.0 37 ns. figure 7-94. timer timing 346 peripheral information and electrical specifications submit documentation feedback tinpxl/tinpxu toutxl/toutxu 1 2 3 4
7.28 general-purpose input/output (gpio) 7.28.1 gpio device-specific information tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the gpio peripheral provides general-purpose pins that can be configured as either inputs or outputs. when configured as an output, a write to an internal register can control the state driven on the output pin. when configured as an input, the state of the input is detectable by reading the state of an internal register. in addition, the gpio peripheral can produce cpu interrupts and edma events in different interrupt/event generation modes. the gpio peripheral provides generic connections to external devices. the gpio pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of gp[0:15]). the dm6467 gpio peripheral supports the following: up to 33 3.3-v gpio pins, gp[0:47; not all pinned out] interrupts: ? up to 8 unique gp[0:7] interrupts from bank 0 ? 3 gpio bank (aggregated) interrupt signals from each of the 3 banks of gpios ? interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable gpio signal dma events: ? up to 8 unique gpio dma events from bank 0 ? 3 gpio bank (aggregated) dma event signals from each of the 3 banks of gpios set/clear functionality: software writes 1 to corresponding bit position(s) to set or to clear gpio signal(s). this allows multiple software processes to toggle gpio output signals without critical section protection (disable interrupts, program gpio, re-enable interrupts, to prevent context switching to anther process during gpio programming). separate input/output registers output register in addition to set/clear so that, if preferred by software, some gpio output signals can be toggled by direct write to the output register(s). output register, when read, reflects output drive status. this, in addition to the input register reflecting pin status and open-drain i/o cell, allows wired logic be implemented. although, the dm6467 device implements three gpio banks, not all gpios from all banks are available externally (pinned out). the following gpios are not pinned out on the dm6467 device: bank 0 ? gp[9] ? gp[14] ? gp[15] bank 1 ? gp[27:31] bank 2 gp[34] gp[35] gp[43:47] for more detailed information on gpios, see the tms320dm646x dmsoc general-purpose input/output (gpio) user's guide (literature number sprueq8 ). submit documentation feedback peripheral information and electrical specifications 347
7.28.2 gpio peripheral register description(s) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com table 7-146 shows the gpio peripheral registers. table 7-146. gpio registers hex address range acronym register name 0x01c6 7000 pid peripheral identification register 0x01c6 7004 - reserved 0x01c6 7008 binten gpio interrupt per-bank enable gpio banks 0 and 1 0x01c6 700c - reserved 0x01c6 7010 dir01 gpio banks 0 and 1 direction register (gp[0:31]) 0x01c6 7014 out_data01 gpio banks 0 and 1 output data register (gp[0:31]) 0x01c6 7018 set_data01 gpio banks 0 and 1 set data register (gp[0:31]) 0x01c6 701c clr_data01 gpio banks 0 and 1 clear data for banks 0 and 1 (gp[0:31]) 0x01c6 7020 in_data01 gpio banks 0 and 1 input data register (gp[0:31]) 0x01c6 7024 set_ris_trig01 gpio banks 0 and 1 set rising edge interrupt register (gp[0:31]) 0x01c6 7028 clr_ris_trig01 gpio banks 0 and 1 clear rising edge interrupt register (gp[0:31]) 0x01c6 702c set_fal_trig01 gpio banks 0 and 1 set falling edge interrupt register (gp[0:31]) 0x01c6 7030 clr_fal_trig01 gpio banks 0 and 1 clear falling edge interrupt register (gp[0:31]) 0x01c6 7034 instat01 gpio banks 0 and 1 interrupt status register (gp[0:31]) gpio bank 2 0x01c6 7038 dir2 gpio bank 2 direction register (gp[32:47]) 0x01c6 703c out_data2 gpio bank 2 output data register (gp[32:47]) 0x01c6 7040 set_data2 gpio bank 2 set data register (gp[32:47]) 0x01c6 7044 clr_data2 gpio bank 2 clear data register (gp[32:47]) 0x01c6 7048 in_data2 gpio bank 2 input data register (gp[32:47]) 0x01c6 704c set_ris_trig2 gpio bank 2 set rising edge interrupt register (gp[32:47]) 0x01c6 7050 clr_ris_trig2 gpio bank 2 clear rising edge interrupt register (gp[32:47]) 0x01c6 7054 set_fal_trig2 gpio bank 2 set falling edge interrupt register (gp[32:47]) 0x01c6 7058 clr_fal_trig2 gpio bank 2 clear falling edge interrupt register (gp[32:47]) 0x01c6 705c instat2 gpio bank 2 interrupt status register (gp[32:47]) 0x01c6 7060 - 0x01c6 77ff - reserved peripheral information and electrical specifications 348 submit documentation feedback
7.28.3 gpio peripheral input/output electrical data/timing tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-147. timing requirements for gpio inputs (1) (see figure 7-95 ) -594, -729 no. unit min max 1 t w(gpih) pulse duration, gp[x] input high 2c (2) ns 2 t w(gpil) pulse duration, gp[x] input low 2c (2) ns (1) the pulse width given is sufficient to generate a cpu interrupt or an edma event. however, if a user wants to have dm6467 recognize the gp[x] input changes through software polling of the gpio register, the gp[x] input duration must be extended to allow dm6467 enough time to access the gpio register through the internal bus. (2) c = sysclk3 period in ns. for example, when running parts at 594 mhz, use c = 6.7 ns. table 7-148. switching characteristics over recommended operating conditions for gpio outputs (see figure 7-95 ) -594, -729 no. parameter unit min max 3 t w(gpoh) pulse duration, gp[x] output high c (1) (2) ns 4 t w(gpol) pulse duration, gp[x] output low c (1) (2) ns (1) this parameter value should not be used as a maximum performance specification. actual performance of back-to-back accesses of the gpio is dependent upon internal bus activity. (2) c = sysclk3 period in ns. for example, when running parts at 594 mhz, use c = 6.7 ns. figure 7-95. gpio port timing submit documentation feedback peripheral information and electrical specifications 349 gp[x] input gp[x] output 4 3 2 1
7.29 ieee 1149.1 jtag 7.29.1 jtag id (jtagid) register description(s) tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com the jtag (3) interface is used for bsdl testing and emulation of the dm6467 device. trst only needs to be released when it is necessary to use a jtag controller to debug the device or exercise the device's boundary scan functionality. reset must be released only in order for boundary-scan jtag to read the variant field of idcode correctly. other boundary-scan instructions work correctly independent of current state of reset. for maximum reliability, dm6467 includes an internal pulldown (ipd) on the trst pin to ensure that trst will always be asserted upon power up and the device's internal emulation logic will always be properly initialized. jtag controllers from texas instruments actively drive trst high. however, some third-party jtag controllers may not drive trst high but expect the use of a pullup resistor on trst. when using this type of jtag controller, assert trst to initialize the device after powerup and externally drive trst high before attempting any emulation or boundary scan operations. (3) ieee standard 1149.1-1990 standard-test-access port and boundary scan architecture. table 7-149. jtag id register hex address range acronym register name comments read-only. provides 32-bit 0x01c4 0028 jtagid jtag identification register jtag id of the device. the jtag id register is a read-only register that identifies to the customer the jtag/device id. for the dm6467 device, the jtag id register resides at address location 0x01c4 0028. the register hex value for dm6467 is: 0x 1b77 002f [for silicon revision 3.0 and later] and 0x 0b77 002f [for silicon revision 1.1 and earlier]. for the actual register bit names and their associated bit field descriptions, see figure 7-96 and table 7-150 . 31-28 27-12 11-1 0 variant (4-bit) part number (16-bit) manufacturer (11-bit) lsb r-000 x r-1011 0111 0111 0000 r-0000 0010 111 r-1 legend: r = read, w = write, n = value at reset, x = silicon revision dependent figure 7-96. jtag id register description - dm6467 register value - 0xxb77 002f peripheral information and electrical specifications 350 submit documentation feedback
7.29.2 jtag test-port electrical data/timing tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 table 7-150. jtag id register selection bit descriptions bit name description variant (4-bit) value. dm6467 value: 0000 [silicon revision 1.1 and earlier] and 0001 [silicon 31:28 variant revision 3.0 and later]. 27:12 part number part number (16-bit) value. dm6467 value: 1011 0111 0111 0000. 11-1 manufacturer manufacturer (11-bit) value. dm6467 value: 0000 0010 111. 0 lsb lsb. this bit is read as a "1" for dm6467. table 7-151. timing requirements for jtag test port (1) (2) (see figure 7-97 ) -594, -729 no. unit min max 1 t c(tck) cycle time, tck 20 ns 2 t w(tckh) pulse duration, tck high 0.4t ns 3 t w(tckl) pulse duration, tck low 0.4t ns 4 t c(rtck) cycle time, rtck 20 ns 5 t w(rtckh) pulse duration, rtck high 0.4r ns 6 t w(rtckl) pulse duration, rtck low 0.4r ns 7 t su(tdiv-rtckh) setup time, tdi/tms/ trst valid before rtck high 12 ns 8 t h(rtckh-tdiv) hold time, tdi/tms/ trst valid after rtck high 0 ns 9 t su(emuv-tckh) setup time, emu[1:0] valid before tck high 1.5 ns 10 t h(tckh-emuv) hold time, emu[1:0] valid after tck high 4 ns (1) t = tck cycle time in ns. for example, when tck frequency is 20 mhz, use t = 50 ns. (2) r = rtclk cycle time in ns. for example, when rtck frequency is 20 mhz, use t = 50 ns. table 7-152. switching characteristics over recommended operating conditions for jtag test port (1) (see figure 7-97 ) -594, -729 no. parameter unit min max 11 t d(rtckl-tdov) delay time, rtck low to tdo valid -1 8 ns 12 t d(tckh-emuv) delay time, tck high to emu[1:0] valid 2.5 t - 2.5 ns (1) t = tck cycle time in ns. for example, when tck frequency is 20 mhz, use t = 50 ns. submit documentation feedback peripheral information and electrical specifications 351
tms320dm6467 digital media system-on-chip sprs403f ? december 2007 ? revised october 2009 www.ti.com figure 7-97. jtag test-port timing peripheral information and electrical specifications 352 submit documentation feedback tck tdo tdi/tms/trst 1 7 2 3 rtck 4 5 6 11 8 emu[1:0](input) 9 10 emu[1:0](output) 12
8 mechanical packaging and orderable information 8.1 thermal data for zut 8.1.1 packaging information tms320dm6467 digital media system-on-chip www.ti.com sprs403f ? december 2007 ? revised october 2009 the following table(s) show the thermal resistance characteristics for the pbga?zut mechanical package. table 8-1. thermal resistance characteristics (pbga package) [zut] no. c/w (1) air flow (m/s) (2) 1 r jc junction-to-case 1.5 n/a 2 r jb junction-to-board 9.9 n/a 3 r ja junction-to-free air 19.2 0.00 4 14.8 0.50 5 13.8 1.00 r jma junction-to-moving air 6 12.7 2.00 7 11.9 3.00 8 0.3 0.00 9 0.4 0.50 10 psi jt junction-to-package top 0.4 1.00 11 0.4 2.00 12 0.5 3.00 13 9.0 0.00 14 8.0 0.50 15 psi jb junction-to-board 7.7 1.00 16 7.3 2.00 17 7.0 3.00 (1) these measurements were conducted in a jedec defined 2s2p system and will change based on environment as well as application. for more information, see these eia/jedec standards ? eia/jesd51-2, integrated circuits thermal test method environment conditions - natural convection (still air) and jesd51-7, high effective thermal conductivity test board for leaded surface mount packages. (2) m/s = meters per second the following packaging information and addendum reflect the most current data available for the designated device(s). this data is subject to change without notice and without revision of this document. submit documentation feedback mechanical packaging and orderable information 353
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) tms320dm6467czut active fcbga zut 529 84 pb-free (rohs exempt) call ti level-4-245c-72hr tms320dm6467czut7 active fcbga zut 529 1 pb-free (rohs exempt) call ti level-4-245c-72hr tms320dm6467czuta active fcbga zut 529 84 pb-free (rohs exempt) call ti level-4-245c-72hr tms320dm6467czutav active fcbga zut 529 84 pb-free (rohs exempt) call ti level-4-245c-72hr tms320dm6467czutd7 active fcbga zut 529 84 pb-free (rohs exempt) call ti level-4-245c-72hr tms320dm6467czutv active fcbga zut 529 84 pb-free (rohs exempt) call ti level-4-245c-72hr tms320dm6467zut active fcbga zut 529 1 pb-free (rohs exempt) call ti level-4-245c-72hr tms320dm6467zut7 active fcbga zut 529 84 pb-free (rohs exempt) call ti level-4-245c-72hr tms320dm6467zuta active fcbga zut 529 84 pb-free (rohs exempt) call ti level-4-245c-72hr tms320dm6467zutav active fcbga zut 529 84 pb-free (rohs exempt) call ti level-4-245c-72hr tms320dm6467zutd7 active fcbga zut 529 84 pb-free (rohs exempt) call ti level-4-245c-72hr TMS320DM6467ZUTV active fcbga zut 529 84 pb-free (rohs exempt) call ti level-4-245c-72hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. package option addendum www.ti.com 25-jan-2010 addendum-page 1
in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 25-jan-2010 addendum-page 2

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